JPS6033595A - Vibrato adding apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a vibrato adding device for an electronic musical instrument, and more particularly to a vibrato adding device capable of changing the vibrato frequency with a simple configuration.

Conventional configuration and its problems Conventionally, vibrato adding devices have been configured to perform analog frequency modulation on the main oscillator.

In order to change the vibrato frequency, it is necessary to change the frequency of the modulation signal, which has the drawbacks that the modulation signal generation circuit is large and its output frequency is unstable. OBJECT OF THE INVENTION An object of the present invention is to provide a vibrato adding device that can change the vibrato frequency with a simple configuration.Structure of the Invention The vibrato adding device of the present invention stores vibrato data in one frequency modulation booter. a memory, an address generator for generating an address for the vibrato data memory, a note clock generator for frequency modulating a musical tone signal using the output data of the vibrato data memory, and a note clock generator for controlling the length of the address generated by the address generator. This device is equipped with an address length control section and is configured to change the vibrato frequency by controlling the address length of the address generation section, and the vibrato frequency can be changed with a simple configuration.〇Explanation of an Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an electronic musical instrument employing the vibrato adding device of the present invention.

1o1 is a keyboard section (KB), 102 is an operation section (T) consisting of a tone tablet switch, a vibrato effect on/off switch, a glide effect on/off switch, etc.
AB), 1o3 is a central processing unit (CPU) similar to that used in computers, and 104 is a read/write storage device (Random access memory).
105 is a read-only memory (read-only memory, called ROM) in which a program that determines the operation of the CPU 103 is stored; 106 is a read-only memory that performs waveform sample data and waveform interpolation for synthesizing musical tones; This is a ROM that stores temporary control data and the like. 1
07 is a musical tone generating section that generates musical tones using waveform sample data and control data stored in the ROM 106;
8 is a filter for removing sampling noise, and 1o9 is an electroacoustic transducer.

Keyboard section 101, operation section 102, CPU 103° RAM 1
04, ROM105.106. The musical tone generator 107 is connected to a data bus, an address bus, and an Otahi control line. The method of connecting data buses, address buses, and control lines in this way is a well-known configuration method mainly for minicomputers and microcomputers. ◎8 to 16 lines are used as data buses, and this Data is transmitted and received on the bus line not in two directions but in multiple directions in a time-division manner. A plurality of address buses, for example 16, are prepared, and normally the cPu1o8 outputs the address code, and the other parts receive the address code. The control line is usually the memory request line (MREQ)
, Ilo Request line (IORQ), read line (Hinoki), write line (WR), etc. are used. RD indicates the timing to read data from the memory or 1.10, and WR indicates the timing to write data to the memory or Ilo.As for using such control lines.

One example is the microprocessor Zso from Zilog.

Next, the operation of the electronic musical instrument shown in FIG. 1 will be described.

The keyboard section 101 is configured to be able to divide a plurality of key switches into a plurality of groups and send the on/off states of the key switches in the group all at once to the data bus. For example 6
In the case of a one-key keyboard, it is divided into 10 groups of 6 keys (half an octave) and 11 groups of 1 key, and one address code is assigned to each group. When an address code indicating one of the key switches in the corresponding group arrives and the signal l0RQ and signal RD are applied, the keyboard section 101 decodes the address code and inputs the 6-bit or Outputs 1-bit data to the data bus. These can be constructed using decoders, bus drivers and some gate circuits.

Regarding the tablet switch in the operation unit 102,
It can have the same configuration as the keyboard section 1o1.

The CPU 103 reads the instruction code from the address of the ROM 105 that corresponds to the code of the program counter inside it, decodes it, and performs arithmetic operations, logical operations, reading and writing data, jumping instructions by changing the contents of the program counter, etc. Perform this work. The procedures for these operations are written in the ROM1oes. First, the CPU 103 reads a command to import the data of the keyboard section 101 from the ROM 1oes, and imports the code indicating the on/off of each weight of the keyboard section 101 for each group. , the musical tone generation data corresponding to the assigned key code is sent to a finite channel of the musical tone generating section 107.Next, the CPU 103 sequentially sends a group of commands for importing data from the operation section 102.
Read from OM105, decode these and send to operation unit 10.
Address code and control signal I O corresponding to 2
RQ and RD are output, a code representing the state of the switch of the operation unit 102 is output to the data bus, and the CPU 103
Based on the data read into the CPU 103, tone selection and predetermined effect control data are generated, and the tone selection data and musical tone generation section 10 are stored in the ROM 106.
Effect control data is sent to 7. The method of allocating the pressed key code to a finite channel of the tone generator 107 is known as a generator assigner function.

Based on the musical sound generation data supplied from the CPU 103, the musical sound generating section 107 takes in predetermined waveform sample data and control data from the musical sound synthesis data ROM 106, performs waveform interpolation processing, generates a musical sound waveform, and then outputs the musical sound waveform to the filter 10.
A musical tone is generated from the electroacoustic transducer 109 via B.

FIG. 2 shows a time chart when data is supplied from the CPU 103 to the musical tone generator 107. The I10 port address is supplied to the address bus, and musical tone generation data, effect control data, etc. are supplied to the data bus. Then, at the timing when the control signals l0RQ and WR change from logic low level (hereinafter abbreviated as "o") to logic high level (abbreviated as "eng"), the contents of the data bus are latched into the channel specified by the I10 port address. do.

Next, various data supplied to the musical tone generation section 107 will be explained. Table 1 shows the Ilo port address and the contents of the various data. The I10 port address is displayed in hexadecimal. Ilo port address (oO) 16 to (o7) 1
The data corresponding to 6 is musical tone generation data for 8 channels, that is, it is possible to generate 8 tones.・Ilo
The port address (oB) 16 is sustain data that specifies the attenuation characteristic of the envelope signal. Il
o Port address (oO) 16 is damper data that becomes effective when the envelope characteristic is piano type, and is 9/. The I10 port address (OA) 16 is pitch control data and is used to shift the note clock from its normal value.

0 I10 port address (oB) 1 e is effect control data, which is composed of vibrato on/off signals, glide on/off signals, and the like.

The I10 port address (OC) 16 is data for specifying one vibrato data among the vibrato data.

The I10 port address (OD) 16 is vibrato speed data, which is data that specifies the vibrato frequency.

Table 2 Table 3 Table 2 shows the composition of the musical tone generation data. Pit positions DO to D3 are note clock designation data that designates the scale frequency, and 0 bit positions D4 to D6 are waveform sample number designation data that designates the generation range. Pit position D
Reference numeral 7 indicates a key on/off signal accompanying the on/off operation of the key switch, which is "'0" when off and @1 when on.

Table 3 shows the code contents of the waveform sample number specification data SDO to SD2 and the number of samples in one period of the waveform specified by the code. The waveform sample number specification data SD is (oOo
)2 to (111)2, and in this example, up to 612 samples are specified. Table 6 shows the relationship between the contents of the chord represented by the specified data NDo-ND3 and the specified scale specified by that code. Table 6 shows the composition of the effect control data. The 0 bit position Do is the vibrato on/off signal VIB. , operation section 10
When the vibrato on/off switch in 2 is off +j
ON, becomes "1" when turned on. Bit position D1 is the delay vibrato on/off signal DVIB, which is a delay vibrato effect control signal, and when the delay vibrato on/off switch in the operation unit 102 is turned off, "'0"", when it is on, it becomes "1".

The pit position D2 is a glide on/off signal GL, which is "0" when the glide switch in the operating section 102 is off, and "1" when it is on.

Pit position D3 is an organ type/piano type designation signal ops
This specifies the envelope characteristics, and is 1o'' for an organ type, and 1' for a piano type.

Pit position D4 is damper on/off signal DMP16.
,・, which is valid only when the envelope characteristic is piano-shaped, is "o" when the damper is off, and "1" when it is on.

Table 6 JP-A-33595(5) FIG. 3 is a block diagram of the musical tone generating section 107. In FIG. 3, 301 is a main oscillator, 302 is a sequencer that controls the operation contents of musical tone generator 107, and 303 is CPU 103.
3o4 is a timer; 305 is a comparison register part; 3o
6 is a frequency data processor (hereinafter abbreviated as FDP) 30 that generates frequency data corresponding to the frequency to be generated;
7 is a waveform data processor that performs waveform interpolation processing and below W
308 is a data read processor (hereinafter abbreviated as DRP) that reads waveform sample data, control data, etc. from the musical tone synthesis data ROM 106, 309
310 is a calculation request flag generation unit that requests arithmetic processing to the WDP 307, DRP 308, etc.; 311 is a digital/digital signal generator that converts a digital signal into an analog signal;
An analog converter (hereinafter abbreviated as DAC), 312 is a 1-channel analog buffer memory section, and 313 is an integrator.

Here, the waveform interpolation method executed by the WDP 207 will be explained.

The waveform interpolation method is as follows: ■ Divide and select sample wave position i to i+1 (i=o, 1.2°..., l-
It is assumed that one cycle of the musical sound wave repeats M times during the period 1), and the waveform sample value at the waveform sample f(xin) combination point is calculated to obtain an approximate value. The interpolation formula is shown below. 0f(xi, m, n)=ge(X, 10,
, n)-, f(Xi, n) 11 is the sample position extracted by dividing into ■, and the waveform number is 0 (l=0,1
,2. . . , Il-1) represents a position in the middle of a repeating transition between waveform number i and i+1 M times, and is 18. (m==o, 1, 2, -., M-1) n is a sample position obtained by dividing one cycle of the musical sound waveform into N, and is a waveform sample NAND. (n=o.

1.2. ..., N-1) In addition, WDP207. The operation around the DRP 208 is described in detail in Japanese Patent Application No. 57-231482 "Musical Sound Generator".

Reference numeral 310 constitutes a mate clock generation section that determines the tone scale, and based on the output signal thereof, DRPsos, which is a data reading section, reads data from the musical tone synthesis data ROM 1oa.

In addition, the input register section 303. Comparison register section 306,
Procedures for processing the FDP 306, WDP 307, DRP 308, and calculation request flag generation unit 310 are determined by the sequencer 302.

When musical tone generation data is supplied from the CPU 103 to a predetermined channel, for example, channel 1, the input register section 303
From there, musical tone generation data is supplied to F D Paoe, WDP 307, and DRP 308. Then, DRP3o
At s, waveform sample data and control data are read from the musical tone synthesis data ROM 1o6. Then, let fcX, n) shown in equation (1) be data WD), and f(Xi
+1 is supplied to the WDP 307 as data. Further, the numerator term (Nrn + n) of the interpolation coefficient shown in equation (1) based on the read control data is supplied to the WDP 307 as data MLP. Also, when the final waveform data is reached, the WEF signal instructing the final waveform data is transmitted to WDP3.
◎ The WDP 307 "t' uses the data WD l , WD[, MLP supplied from the DRP 308, performs waveform calculation processing of equation (1), and supplies the processed data to the DAC 311.

Then, the DAC 311 converts the digital signal supplied from the WDP 307 into an analog signal, and supplies it to the analog buffer memory section 312 as an analog signal.
Capacitor charge corresponding to channel 1 is stored.

On the other hand, the FDP 306 generates frequency data based on the musical tone generation data supplied from the input register section 303, and supplies it to the register corresponding to channel 1 of the comparison register section 305. Then, the data supplied to the comparison register 306 and the time data supplied from the timer 304 are compared, and if a match is detected, a matching pulse is read out and supplied to the pulse forming section 309 and the calculation request flag generating section 310. .

Then, the read pulse forming section 309 generates a read signal with a predetermined pulse width and supplies it to the analog buffer memory section 312. Analog buffer memory section 3
The charge stored in the capacitor corresponding to channel 1 in 12 flows into the integrator 313 by the read signal.

The calculation request flag generating section 310 generates and holds a division request flag for calculating the next waveform sample, that is, the virtual sample point f(Xi, m, n+1).

Then, when the processing timing becomes channel 1 again, the calculation request flag has been generated, so the processing timing is 21.

Waveform interpolation processing is performed in the same manner as described above, and charges are stored in the capacitor in the analog buffer memory section 312. Thereafter, waveform interpolation processing is performed in response to the calculation request flag, and a musical tone waveform is generated.

△ Note that the charge stored in the capacitor is f(xi, m, n-
1) Corresponds to the difference between Δ and the waveform sample value f(xi9m, n) obtained this time. The operation of the 0 analog buffer memory section 312 and the integrator 313, in which the waveform sample value f(xi9m, n) obtained this time is restored by the integrator 313, is described in Japanese Patent Application No. 57-12641.
3 “Waveform Reading Device” FIG. 4 is a block diagram of a specific example of the sequencer 302. In the figure, 4o
1 is a two-phase lock generation unit that generates a two-phase lock signal φ1 and a signal φ2, 402 is a 11-decimal counter that determines the operation sequence for each channel, and 4o3 generates a channel code that is currently being processed. counter.

404 is a ROM in which operating procedures are stored, and 405 is a decoder. 22/ of the sequencer 302 in FIG.
- Show a timing chart.

The master clock (MCK) signal from the main oscillator 301 is 2
The signal is supplied to the matching lock generating section 401.

In the two-phase lock generating section 401, the two-phase lock generating section 401 generates two phases as shown in FIG.
Phase lock signal φ1. Generates φ2. Signal φ1 is 11
It is supplied to the advance counter 402 and counter 403.

The 11-decimal counter 402 has a 4-bit configuration, and the count-up process is performed at the timing when the signal φ1 changes from 0' to @1', the output signal becomes (1111)2, and then the count-up is performed. As a result, the output signal of the hexadecimal counter 402 is in the state of 11, that is, (01o1)2 to (1111).
) becomes 2. This is used as a command step signal.

The counter 403 has a 3-bit configuration, and the output signal of the 11 counter 402 is from (1111)2 to (01o1
As a result, the output signal of the counter 403 is in the state of 8, that is, (ooO)2 to (111)2 and 23, . Use this as the channel code.

ROM 404 reads out an instruction code based on the instruction step signal supplied from decimal counter 402 and supplies it to decoder 406 . Decoder 405 is ROM 4
It decodes the instruction code supplied from 04 and supplies processing control signals to each section.

As a result, the calculation time per channel is 2.76 μs, and each calculation process is performed in 11 instruction steps. Then, the calculation timing is repeated every 22 μs.

FIG. 6 shows a configuration diagram of a specific example of the analog buffer memory section 312. In the figure, 6o1 is an input terminal.

602 is an output terminal, 603 to 608 are analog switches,
01~C3 are capacitors @Analog switch 60
Signals AW1 to AWs supplied to the gate inputs of 3.605.607 are supplied from WDP307. In addition, the signals AR1 to ARs supplied to the gate inputs of the analog switches 604, 606, and 608 are read out.
is applied to analog switches 603, 605, and 607. If the data corresponds to channel 1, only the analog switch 603 is turned on, and the charge corresponding to the analog signal applied to the input terminal 601 is stored in the capacitor C1.

Thereafter, a read pulse AR1 corresponding to channel 1 is transmitted from the read pulse generator 309 to the analog switch 60.
4, the charge stored in the capacitor C4 is supplied to the integrator 313 via the output terminal 602.

Analog switch 603.605.607 is W D P
Since it is synchronized with the operation timing of 307, multiple analog switches 604 will not be on at the same time.
．． Since 606 and 608 are turned on in synchronization with the musical scale frequency, a plurality of them can be turned on at the same time. FIG. 7 is an internal excitation timing chart of musical tone generation 9307. Figure 7 shows the timing for 4 channels at 25:.

Explanation of Abbreviations in the Figure CRF is a calculation request signal for each channel. Then, the request start time is synchronized with the coincidence signal supplied from the comparison register unit 306. In other words, it is synchronized with the scale frequency, and for example, in the C scale, it occurs every 59.74 μs.

CLC indicates waveform calculation timing 0DAC indicates DA
〇0T (Jj:), which indicates the timing at which the charge is stored in the capacitor in the analog buffer memory 312 via C311, is the timing at which the charge stored in the capacitor in the analog buffer memory 312 is supplied to the integrator 313, and CRF and Similarly, the calculation timing corresponding to channel 1, which occurs in synchronization with the scale frequency, is sequence 26.
This is determined by the channel code generated by the Vegetarian 302, and as shown in the figure, calculation timing occurs every 22 μs.

(2) Signal CRF1 is generated in the middle of channel code 1. Waveform interpolation processing and frequency data updating are not performed at the generated timing. □■...At the same time as the signal CRF1 is generated, the signal 0TC1 is generated, and the charge of the capacitor C1 in the analog buffer memory 312 is supplied to the integrator 313. The pulse width of the signal OTC is about 2 μs.

(2) When the channel code becomes 1 again, reading processing of waveform sample data, waveform interpolation processing, frequency data updating processing, etc. are performed.

■...When the arithmetic processing of channel 1 is completed, the signal DA
C1 is generated, and charge is stored in the capacitor C1 via the DAC 311.

■...When the arithmetic processing of channel 1 is completed, the signal CR
Reset F1 and cancel the calculation request.

■...Similar to the above ■, at the timing when the signal CRF1 is generated again, at the timing of the above ■, the capacitor C
The charge stored at 1 is supplied to an integrator 313.

From then on, as described above, each time the signal CRF is generated, 1
The temporary phase waveform sample value calculation process and the frequency data update process are performed twice, and the waveform calculation result is supplied to the integrator 313 in synchronization with the generation timing of the signal CRF, that is, the musical scale period.

Regarding the relationship between the calculation cycle and the scale period, it is sufficient that the calculation timing of the same channel can be performed twice within the minimum scale period and that the calculation result can be stored in a capacitor in the analog buffer memory section 312. That is, it is sufficient to provide calculation timings corresponding to 10 channels within the minimum scale period in consideration of vibrato, glide, etc.

Description of how to generate pitches Regarding notes, a clock signal corresponding to a 12-tone scale is generated. Regarding the octave relationship, the octave relationship is generated by changing the number of samples in one period of the musical sound waveform stored in the musical tone synthesis data ROM 1oe.

If the coson tone (32,708 Hz) is 612 samples, the note clock signal is 32.708 Hz x 512 samples '-1 6.74 klk. Table 6 shows the note clock frequency, and Table 7 shows the number of waveform samples and the octave relationship. 〇 Explanation of the scale cycle generation method . timer 3 0
4 consists of a 10-pit binary counter, and the output status is expressed in hexadecimal notation from (oOo)16 to (3F
F) Count up sequentially until 16. (3FF)
16 becomes (oOo) 16 again, and from (oOo) 16 to (3FF), 6 is repeated based on the signal MCK supplied from the main oscillator 301.

29 spaces below Table 6 ・ Fylo = 8. OO096Rt & 30 - Table 7 In other words, the repetition period TR of the timer 304 is as shown in the following formula.・As a method of generating the scale period, the output signal of the timer 304 and the FDP3
A comparison is made with the frequency data supplied from 06, and if a match is detected, a match pulse is sent out from the comparison register section 305.

The generation cycle of the matching pulse becomes the scale cycle of the scale to be sounded. As shown in FIG. 8, a note clock signal can be generated by updating the frequency data.

That is, the FDP 306 performs arithmetic processing as shown in the following formula: NFD=MOD(OFD-1-PD, TDmax)...
...(3) NFD is the new frequency data 0
0FD is frequency data before updating, OPD is scale data determined by the generated scale, and O TD is the number of output states of the timer 304 ax . In this example, TDmax is 210, that is, 1o2
4◎'', 2P Table 8 shows the scale data PD corresponding to the 12-tone scale.

FIG. 9 of Table 8 is a configuration diagram of a specific example of FDP3Q6. In FIG. 9, 9o1 is a cent scale data generation unit (hereinafter referred to as CPD generation path) that generates scale data expressed in cent scale (referred to as CPD), and is composed of a ROM that stores cent scale data. C based on note clock designation data (ND), waveform sample number designation data (SD), and organ type/piano type designation signal (OPS).
PD is selectively generated. ◎902 is a pitch control data gate that selects pitch control data, 903 is a vibrato signal generation section that generates a vibrato signal, 904 is a glide signal generation section that generates a glide signal, and 9o5 is a pitch control data gate that selects pitch control data. An exponential converter that converts a frequency value expressed in cent scale into frequency data directly proportional to the frequency, 906 is an arithmetic unit, and 9o7 is a latch (AL)
, 908 is a latch (BL), and 909 is an adder (F
A), 910 is a buffer, and 911 is a gate. 912, 913, 914 are pass lines, 912 is F
The AC bus 913 is an FB bus, and the FC bus 914 is an FC bus.

Note that the pitch control data CPCD, vibrato data CVD, and glide data COD are also expressed in cent scale.

Structure of various data Cent pitch data (CPD) It is composed of 11 bits, with the upper 4 pits representing 12-tone equal temperament, and the lower 7 bits representing each point of the chromatic scale divided into 128 equal parts.

Pitch control data (CPCD), vibrato data (CVD), and glide data (CGD) Each bit structure is 8 bits, and chromatic scale is 128 using two's complement representation.
It has an equally divided resolution ◎ and represents positive and negative pitch control components, vibrato components, and glide components.

Description of vibrato signal generation section 903 Fig. 10 shows a configuration diagram of a specific example of vibrato signal generation section 903. In the figure, 1oo1 is vibrato data CV
1002 is a vibrato ROM that stores a plurality of vibrato data; 1002 is a vibrato address register 2 that stores address data for reading out vibrato data stored in ROM 1001; 1004 is the shifter 10 by the signal RDCVD.
03 output signal (vibrato data CVD) is supplied to the FB bus), 1005 is the signal KD, signal VIB, and signal DVIB supplied from the input register section 303.
and a condition setting unit that sets the operating conditions of the vibrato signal generation unit 903 based on the signal CHC supplied from the sequencer 302; 1006 a selector that selects data to be stored in the hallesister 1002;
0o8 is an AND game), and 1009 is a carry detection unit that detects carry of vibrato data (CVD).

Principle of vibrato signal generation Figure 11 is a data map diagram showing the contents of the vibrato ROM 1001.One vibrato data memory has a structure of 2048 words with 8 bits per word, and stores data representing the vibrato waveform. has been done.

The vibrato ROM 1001 is constituted by 16 such vibrato data memories, and the vibrato select data V supplied from the input register section 308
One vibrato data memory is selected for the 4-bit signal.

Normally, 14-bit vibrato address data is sent from the FC bus to register 100 via selector 1006.
2. The lower 11 bits of the 14-bit vibrato address data are supplied as address data to the vibrato ROM 10o1, and the second three bits are supplied as shift data to the shifter 1o03.

The vibrato ROM 1o01 supplies vibrato data to the FB bus via the gate 1004 according to the address supplied from the register 1002. On the other hand, vibrato address data in a 14-bit configuration is directly supplied to the FB bus via the gate 1007, and is used for calculation. The signal is incremented by 1 in section 906 and supplied to the FC bus again. Through this repetition, the vibrato address data increments by 1. Therefore, the vibrato address data supplied from the FC bus is added to the vibrato ROM 1001 as a read address, and the vibrato address data is added to the vibrato ROM 1001 as a read address.
- For the purpose of executing the increment processing of the address itself, the FC
The selector 1o06 transferred from the FB bus has the role of setting the initial value of the vibrato address data added to the vibrato ROM 1001 and shifter 1003. In other words, selector 10
06 selects the vibrato address data normally supplied from the FC bus, and the vibrato address data is
The address is incremented by one by the address increment processing described above.

When the address data corresponding to the lower 11 bits of the vibrato address data overflows, the carry detection unit 10
09 is set, an initial value selection signal is sent to the selector 1006, and the selector 10o6 selects the input register section 30.
Select the initial value VH3 (vibrato speed data) supplied from 3. After that, the selector 1006 selects the vibrato address data supplied from the FC bus and selects the vibrato address data supplied from the FC bus.
Normal increment processing is performed. Therefore, the address data, which is the lower 11 bits of the vibrato address data, increments between the initial value VBS and the final value (2048)10.

The method of setting Vipler 1 and frequency will be explained below.

Note that the initial address value VH8 to the final address value (2
048) The number of addresses up to 1° is called the address length.

The reason why the initial value of the vibrato address data is called VBS (vibrato speed data) is that the initial value determines the frequency of the vibrato. In other words, since the time required for one step of vibrato address data is constant, the time required for one cycle of vibrato is determined by the value of the address length. In other words,
The address length value determines the vibrato frequency.

FIG. 12 is an example of vibrato data for one period stored in the vibrato ROM 1001. Note that the horizontal axis represents addresses, and the vertical axis represents the size of vibrato data.

In this case, the vibrato speed data VBS is (000
)16-(o)1o to (2A○)16-(”2)10
By changing the address length between 2048 and
Since it changes up to 1376, a change in vibrato frequency of 48.8% is obtained.

However, as the vibrato frequency changes, the vibrato waveform also changes. Also, the vibrato speed data VB8
In other words, if the initial value of the address exceeds (2AO)16=672, the data corresponding to the initial value of the address and the data corresponding to the final value will not match, causing discontinuity in the vibrato waveform.

The maximum value of the vibrato speed data VBS must be kept within a range in which discontinuity of the vibrato waveform does not cause any audible problem. Below, we will explain the method for selecting vibrato data that corresponds to the vibrato speed data VBS. FIG. 13 shows an example of vibrato data stored in the vibrato ROM 1001.
Assume that the data in Figure 3 ('') and the data in Figure 13 (b) are stored in the vibrato memory 2. The left horizontal axis is the address value expressed in decimal. The vertical axis represents the size of vibrato data. In Fig. 13, data in (a) is vibrato speed data vBs
= (ooo) 16 and address length = 2048. The data in (b) is V HS
= (1oo) = (256) 1°6 This is vibrato data corresponding to address length = 1792. At this time, CPU1oa is VBS, = (ooo)1
6, vibrato select data VBD = (o
o) When 16°VBS=(100)16 ■BD=(0
1) Control is performed so that the number is 16. Then VBs=
(ooo), 6 and when VBS=(100)16, sine wave vibrato can be added.

Using this method, regardless of the vibrato frequency,
A constant vibrato waveform is obtained, and no discontinuity occurs in the vibrato waveform.

The relationship between the vibrato speed data VBS and the vibrato frequency will be specifically shown below.

Assuming that the vibrato data is read out at the calculation timing of channel code 41/1 and once every four times, the readout period will be 88 μs, 0VBS=(
000) 1e, the address length is 2048, so fo = 1/(22p S X 4 X 2048)
=5,55HzVBS=(1oo) =(256
) 1o, the address 6 length is 1792, so fl-1/(22μs×4×1372)=6.34H2
becomes.

In this embodiment, the vibrato frequency is changed by changing the initial value of the vibrato address, but the final value of the address, the initial value,
A similar effect can be obtained by controlling both final values.

On the other hand, the shifter 10o3 controls the amplitude of the Hifrado data CVD supplied from the vibrato ROM 1001 based on the shift data.
The relationship between SFD and output data 08FD of shifter 1003 is as follows.

42 ・(001)2-O3FD-(CVD/64), VSFD
-(010)2-=O8FD=(CVD/32),...
..., VSFD=(110)2・08FD=(CV
D/2), VSFD=(111)2-O8FD=(CV
D) The condition setting unit 1005 sets the following operating conditions.

This is the case when the vibrato off vibrato on/off signal VIB is “O”, and the output of selector 1o06 is forced to always (oO) 1o
shall be. Then, the shift data of shifter 1003 will always be (000)2. As a result, the output data of chic 1o03 becomes (oO). That is, the vibrato data CVD is always (00)16.

Vibrato on Vibrato on/off signal VIB is 1” and signal DVIB
is 0'', the vibrato is on.Register 1
Goo the address data stored in 0o2) 1006
1007 and shifter 1o03.

Note that the upper 3 bits of the address data, that is, the shift data, are forcibly changed to (
111) 2. Then, the output of the vibrato ROM 1001 (vibrato data CVD) is supplied as is to the input of the gate 1004.

When the delay vibrato on/off signal VIB and the delay vibrato on/off signal DVIB are "1", a delay vibrato state is entered. 8 channel key on/off signal K
When any one key-on/off signal KD turns on from the off state of all D, the address data is changed to (Oo
O) Controls Goo) 1006 to set it to 16. Then, in the shifter 1003, the amplitude control (
Oy CVD/64t CVD/321 CVD/1
61CVD/8, CVD/4 + CVD/2
+ CV D) ljs row fx crack. and,
When the shift data becomes (111)2, the shift data is forcibly set to (111)2 as in the vibrato on state.

1N Kaisho GO-33595 (12) Explanations of the symbols listed in Table 9 are as follows.

AL latches data supplied from the FA bus at the falling edge of signal φ2.

BL latches the data supplied from the FB bus at the falling edge of signal φ2.

CRAL is an instruction to clear latch AL with signal φ2 being "1".

ADDl is an instruction to add 61# to FA909(7) carry manpower.

TCA is an instruction to supply the result of arithmetic processing in FA909 to FA bus.

RDCPD is a command for supplying cent pitch data CPD generated by the CPD generation unit 901 to FA.

RDCPCD is an instruction for supplying FB bus pitch control data CPCD using the pitch control gate 902.

J[)CVD is generated by the vibrato signal generator 903 46
--- Command to supply the generated vibrato data CVD to the FB bus.

RDCGD is glide data CGDff generated by the glide signal generation unit 904: a command to be supplied to the FB bus.

RDEXP is EXP converted in the exponent converter 905
Instruction to supply (CPD) to FA bus.

RDΔEXP is ΔEX converted in the exponential converter 906
Instruction to supply P(CPD) to FB Babasu.

RDFD is a command to read out the surrounding frequency data OFD from the comparison register unit 306 and supply it to the FB bus.

RDVAD is an instruction to supply the contents of the vibrato address register 1002 in the vibrato signal generating section 903 to the FB bus.

RDGAD is a command for supplying glide address data from the glide signal generation unit 904 to the FB bus.

WRVAD is an instruction to write the result calculated by the FA 909 to the vibrato address register 1o02 in the vibrato signal generating section 903 at the rising edge of the signal φ2.

WRGAD is an instruction to write the result calculated by the FA 909 to the glide signal generating section 904 at the rising edge of the signal φ2.

WREXP is an instruction to write the result calculated by the FA 909 to the exponent conversion unit 905 at the rising edge of the signal φ2.

WRFD is an instruction to write the result calculated by the FA 909 into the comparison register section 305 at the rising edge of the signal φ2.

Note that the state 11 occurring in the decimal counter 402 in the sequencer 302 shown in FIG. 4 corresponds to the instruction step 11 shown in Table 9.

Vibrato address register 1002 in step 1 of vibrato address increment processing instruction
Write the address data stored in the latch BL908.

Then, in instruction step 2, +1 is added to the vibrato address data VAD, and the addition result is stored in the vibrato address register 1002 again.

As described in detail in the margin 49-8-page below, the vibrato adding device of the present invention changes the vibrato frequency by changing the address length when reading the vibrato data memory. It is possible to select any vibrato frequency in the configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an electronic musical instrument that employs the vibrato adding device of the present invention, FIG. 2 is a time chart when data is supplied from the CPU 1os to the musical tone generating section 107, and FIG. 3 is the configuration of the musical tone generating section 107. 4 is a block diagram of a specific example of the sequencer 302, and FIG. 6 is a block diagram of a specific example of the sequencer 302.
02, FIG. 6 is a configuration diagram of a specific example of the analog buffer memory section 312, FIG. 7 is an internal operation time chart of the musical tone generating section 107, and FIG. 8 is an FD
A transition diagram of the frequency data supplied from P306 to the comparison register section 305, FIG. 9 is a configuration diagram of a specific example of FDP P2O3, and FIG. 10 is a configuration diagram showing a specific example of the vibrato signal 6o/-r generation section 903. 11 is a data map of the vibrato 1-ROM, FIG. 12 is a diagram showing an example of vibrato data, and FIG. 13 is a diagram showing an example of vibrato data corresponding to vibrato speed. 101...keyboard section, 602...operation section, 1o3...central processing unit, 104...old...R
AM, 106... Musical tone synthesis data ROM, 10
7...Music sound generation section. 301... Main oscillator, 302... Sequencer, 3o3... Input register section, 304...
...Timer, 3o6...Comparison register section, 306...Frequency data processor, 3o
7... Waveform data processor, 308...
...Data read processor, 309... Read pulse forming section, 310... Calculation request flag generation section, 311... DAC, 312 Old... Analog buffer memory section, 313...Integrator,
901... CPD generation section, 902... River/pitch control data gate, 903... Vibrato signal generation section, 904... Glide signal generation section, 906... ...Exponent converter, 906...
...Arithmetic unit, 1o01...Vipla-51,:
,,・ )ROM, 1006...Selector. Name of agent: Patent attorney Toshio Nakao and one other person JP-A-33595 (14) Figure 9, 10, and 11;

Claims (1)

[Claims] a vibrato data memory that stores frequency modulation data, an address generator that generates an address for the vibrato data memory, a note lock generator that applies frequency modulation to a musical tone signal using output data of the vibrato data memory, and the address generator. 1. A vibrato adding device comprising: an address length control section for controlling an address length generated by the address generating section, the vibrato frequency being changed by controlling the address length generated by the address generating section.