JPS5912627A - Transistor circuit - Google Patents

Abstract

PURPOSE:To speed up the circuit without increasing the occupied area of the circuit, by inserting a level shift circuit between an input terminal and at least one of a P or an N-channel MOS transistor(TR) gate. CONSTITUTION:A signal from an input terminal IN is applied to a gate of an NMOSQ2N constituting an inverter and also to a gate of a PMOSQ2P constituting similarly the inverter from a contact 21 via the level shift circuit comprising the QS2P and a resistor R2. The NMOSQ2N is turned off when an input is at an L level, taking a VT of the NMOS and the PMOS respectively as +1.0V and -1.0V and a shift amount of the level shift circuit as 3.2V, and a difference between the VT and a gate-source voltage VGS of the PMOSQ2P is -1V, and then, the difference between the VT and the VGS of the NMOSQ2P is 1V when the input is at an H level. Thus, the increase in the occupied area is prevented by making the gm of the PMOS and the NMOS equal to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CMOS circuit, and in particular to a CMOS circuit that can handle a high (H) level input signal with a low voltage (for example, a TTL H level minimum voltage of 2.OV) without increasing the area occupied by the circuit. The present invention relates to a circuit that can output a low (L) level signal as an H level receiver and further reduces power consumption when the input signal level is an intermediate voltage.

In the conventional type of CMO8 circuit, an inverter circuit consisting of a P-channel MO8 transistor (PMO8) and an N-channel MOS transistor (NMO8) as shown in FIG. 1 has been used.

To explain with reference to the drawings, VDD is a power supply terminal that applies voltage to the circuit. GND is a ground terminal, IN is a signal input terminal, and OUT is an output terminal of an inverter consisting of PMO8QIP and NMO8QIN with IN as a gate input. In this circuit, when the input terminal is set to H level, N
MO8QIN is ON.

PMO8QtP is turned off and the multi-output terminal OUT becomes L level. On the other hand, when the input terminal is set to L level, PMO8Q
IP is ON, NMO8QIN is OFF', and multi-output terminal OUT is at H level. This circuit thus outputs an inverted signal of the input signal.

However, in this Figure 1, the gm of PMO8 and NMO8
The threshold voltage of this circuit is equal to 1 of the power supply voltage.
%p at /2, 5. to VDD. When Ov is applied,
The threshold voltage is 2.5V, so it cannot be directly connected to TTL. Set the threshold voltage to the minimum voltage 2 of TTL H level.
．． If you don't want to lower Ovyosi, use 2 NMO8QIN nogm.
It must be larger than MO8Q1p (for example, 3 times or more). As a result, the area occupied by the circuit is large, and the input terminal IN and output terminal OUT
1. The capacitance becomes large, and the time delay of the signal, especially the time required for the output to rise, becomes large. Furthermore, when the input signal is about 2.0■, NMO8QIN, PMO8
When both QIPs are ON, a large current flows.The present invention was made to solve the above-mentioned drawbacks, and its purpose is to lower the threshold voltage of the circuit without increasing the area occupied by the circuit, and to directly perform TTL. The present invention provides a circuit that can increase the speed of the circuit and reduce the power consumption of the circuit when the input signal is at an intermediate potential.

According to the present invention, in a CMOS inverter circuit in which a common input signal is applied to each gate of 2MO8 and NMO8, and each drain is commonly connected to serve as an output terminal, between the input terminal and at least one of the gates of PMO8 or NMO8. C, characterized in that a level shift circuit is inserted in the
An MO8 circuit' is obtained.

The operation of the embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a circuit showing one embodiment of the present invention.

VDD is a power supply terminal, GND is a ground terminal, IN is an input terminal, QUT is an output terminal, Q82P is a 2MO8, and forms a level shift circuit together with a resistor R2. In the figure, the signal at the input terminal IN is applied to the gate of NMO8Q2N constituting the inverter, and is also applied from contact 21 to the gate of PMO8Q2F, also constituting the inverter, via a level shift circuit made up of QS2P and R2. )NM
O8 and 2MO8 ■7 are +1.0■ and -1, O respectively.
If the shift amount of the level shift circuit is 3.2■, then Q, 2 when a TTL level signal is added to the circuit shown in Figure 2.
N and Q2P Table 1 In other words, when the input is at L level, NMO8Q2N is OFF and 2
The difference between the gate/source voltage VaS and VT of MO8Q2P is -1■, and when the input is H level, PMO8Q2
P is OF'Ii''-cThe difference between VGS and VT of NMO8Q2P is 1■.This means that either NMO8 or 2MO8 is OFF in either the H level or L level state of T 'I' L level human power. Therefore, there is no direct current path from VDD to GND, and the absolute value of Vcs-VT can still be almost the same, so by making the gm of 2MO8 and NMO8 about the same, it is possible to avoid an increase in the area occupied by the circuit. The short rise time and short output fall time can be made almost equal.

Figure 3 shows the circuit of the second embodiment of the present invention, with 2MO8QS3P for level shifting and 2MO8QC functioning as a constant current source.
3P constitutes a level shift circuit. In the figure, the voltage at the input terminal IN is directly applied to NMO8Q3N, level-shifted by Q83P, and applied from contact 31 to 2MO8Q3P, and Q3N and Q3
The inverter consisting of P operates similarly to the circuit of FIG.

FIG. 4 shows a circuit of the third embodiment of the present invention, in which NMO8QS
4N and a resistor R4. In Figure 1), the resistor R4 functions as a constant current source as in the example of Figure 3 (can be replaced with 2MO8).

As explained above, by inserting a level shift circuit between the input terminal and at least one of 2MO8 and NMOS, the present invention facilitates connection even when the level of the input signal is uneven and the amplitude is insufficient. Furthermore, a circuit with low power consumption and high operating speed can be obtained.

In the above explanation, we have used an example in which a level shift circuit is inserted between the input terminal and the gate of 2MO8 in case the input signal is biased toward the GND side, but conversely, when the input signal is biased toward the VDD side, A similar effect can be obtained by inserting a level shift circuit between the input terminal and the gate of NMO8. Further, when the input signal is between GND and VDD, a similar effect can be obtained by inserting level shift circuits on both the NMO8 side and the PMO8 side.

[Brief explanation of the drawing]

Figure 1 is a conventional CMOS inverter circuit, Figures 2 to 4 are circuit diagrams of an embodiment of the present invention, and Table 1 shows the state inside the circuit to show the operation of the circuit in Figure 2. It is. QIPIQ2P・・・PMO8+ Q+N, Q2
N...NMO8. Mukan Zuka 2nd Item 3 Tuliang 4 Procedural Amendment (Method) 1982, 1st 2nd - Commissioner of the Japan Patent Office, 1, Indication of Case 1982 Patent Application No. 1215
No. 81 No. 2, Title of the invention Transistor circuit 3, Relationship to the amended person's case Applicant 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative Tadahiro Sekimoto 4, Agent address 108 Sumitomo Mita Building 6, 37-8 Shiba 5-chome, Minato-ku, Tokyo, column 7 for a brief explanation of the drawings in the specification subject to amendment, "Table 1 is" on page 7, line 11 of the statement of contents of the amendment. Delete up to ``It is as shown.'' on the 13th line.

Claims (1)

[Claims] P channel MO8) transistor and N channel MO8
) In a CMOS inverter circuit in which a common input signal is applied to each gate of a transistor and each drain is commonly connected to serve as an output terminal, between the input terminal and at least one of the gates of the P-channel or N-channel transistors. A transistor circuit characterized by inserting a level shift circuit.