JPS59123974A - Vector data storage control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a vector data processing device, and particularly to a vector data processing device that can multiplex and process a plurality of vector instructions that process a plurality of data with one instruction. This invention relates to a storage control method for devices.

[Technology background]

A conventional vector data processing device has a configuration that continuously processes a large amount of data using an l instruction.

However, when consecutive instructions are executed serially, for example, when vector load instructions are executed consecutively as shown in Figure 1, the data fetched from the main memory of one instruction is written to the vector register, and after execution is completed, Then, the address of the next vector load instruction is generated, so
As shown in the figure, there is a problem in that a loss time TD occurs at the rise of each instruction.

Therefore, by overlapping consecutive instructions, processing efficiency can be improved. However, for this purpose, for example, for memory access instructions, it is desirable that a tr7 access pipeline including a data buffer can be shared multiple times by a plurality of instructions.

[Object and structure of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a storage control method for enabling multiple instructions to share an access pipeline in a vector data processing device. and an access pipeline that transfers data between the main memories, wherein the access pipeline includes a plurality of data buffers, a write control block to the data buffers, and a read control block. The write control block and the read control block operate independently, and the data buffer can be shared by multiple instructions.

[Embodiments of the invention]

In a vector data processing device equipped with a vector register whose access timing is determined in an interleaved format, when a vector load instruction is executed, the data read from main memory is transferred until the access timing to write it to the vector register is right. , a data buffer is required for temporary storage. When a plurality of vector instructions are executed consecutively, the data buffer must be controlled for multiple use so as to hold vector data of the plurality of instructions at the same time.

Also, in the vector store instruction, in order to absorb the access timing of the vector register, data read from the vector register is temporarily stored in a data buffer and then stored in the main memory.

In this case as well, multiple sharing control of data buffers is required in order to process instructions continuously.

In the present invention, write control and read control of the data buffer are made independent so that each can be used for different instructions at the same time, and furthermore, means is provided to manage the usage area of the data buffer for each instruction, so that multiple Controls multiple sharing of data buffers using instructions.

FIG. 2 is a block diagram of a data buffer mechanism according to an embodiment of the present invention, and FIG. 3 shows its control circuit.

In FIG. 2, l is a data buffer, which in the illustrated example is composed of 16 stages. 2 is a write address counter, 3 is a +1 step circuit, 4 is a read address counter, and 5 is a +1 step circuit.

Data is written to or read from the data buffer in units of 1 element or multiple elements such as 4 elements, with 4 bytes or 8 bytes serving as one element.

Write address register 2 and read address register 4 are combined with +1 increment circuits 5 and 7, respectively, to form a 4-bit counter. Also,
A write set address or a read set address is set at the start of writing or reading, respectively.

In the case of the write address register 2, the first element is written to the data buffer location indicated by the write set address, and thereafter, the register is incremented by +1 each time a write enable signal is applied to indicate the next write position. In the case of the read address register, the same function is performed for the read position of the data buffer.

Data buffer l is used for both loads and stores. Therefore, the input section and output section are
The direction of transfer to main memory and vector registers is selectively controlled.

Next, an embodiment of the data buffer control circuit will be described with reference to FIG. In the figure, 6 is a write control block, 7 is a read control block, 8 is a write set address register, 9 is an adder, IO is a write element counter, 11 is an adder/subtractor, 12 is an adder, 13 is a queue "'0""Address register, 14 is queue "l"
Address register, 15 is selector, 16 is read set address register, 17 is queue "O" element register, 18 is queue 61M element register, 1
9 is a selector, 20 is a read element counter, 21
indicates an adder.

Write control block 6 and read control block 7
are controlled by separate commands to indicate the write and read positions on the data buffer.
The read control block 7 sets the read start position and the number of read elements for each instruction using information from the write control block 6. The operation of each part will be explained below with reference to the time chart of FIG.

The write control block 6 operates when data is fetched from the main memory, sends a start address and a write permission signal to the data buffer, and activates the read control block 7 in the next cycle to inform it of the read start address.

The write set address register 8 accumulates the number of write elements of each instruction from the data buffer address "'O", and determines the start address on the data buffer for writing the first data of the next instruction. That is, a write set address to the write address register 2 shown in FIG. 2 is generated.

The write element counter lO is calculated for each instruction by the difference between the number of write elements during the write period to the data buffer and the number of read elements when the write period overlaps with the read period (in the illustrated example, “
7″).

In other words, when writing of all elements of one instruction is completed, the number of write elements remaining in the data buffer without being read out is displayed. '' address registers 13.14 and element registers 17.18 are for multiple shared management of the data of the instruction waiting for the write timing to the vector register in the vector load instruction, and are It temporarily holds the read start address and the number of elements that need to be read from that address, and when read permission is granted, it is used to control read in the order of instructions based on it. At this time, the selector 15 and register 16 select necessary register information.

The read set address register 16 supplies the read start address of the data buffer, ie, the read set address to the read address register 4 of FIG. If multiple instructions are not waiting,
The writing start position to the data buffer, that is, address @O'', becomes the reading start position. However, if the data buffer has a ring-shaped circular structure, the writing start position may not always be address ``'O''. do not have.

A read element counter 20 displays at each time the number of remaining elements that require reading of the instruction that is subject to read control.

That is, the number of unread elements existing in the data buffer for the instruction at the time of writing the element indicated by the write element counter 1o, and the number of unread elements that are sequentially decreased by reading execution after the writing is completed, are displayed. Used to control the number of elements read from the data buffer for one instruction.

FIG. 5 is a time chart in a state where a plurality of instructions multiplex and share a data buffer.

When instructions 1.2.3 are executed successively and the respective data are fetched in sequence, if the data buffer is free and available, the write control block 6 causes These data are sequentially written to the data buffer.

Here, if permission to read from the data buffer to the vector register is given at the timing shown in the figure, it is necessary to wait for the data of instructions 2 and 3,
The write start address of each instruction and the information on the number of elements that need to be read are extracted from the write set address register 8 and write element counter 10 in the write control block, and the address registers of queue "'ln" and hikue "'0" are retrieved. 13.14 and element registers 17.18.

On the other hand, the read control block 7 executes data read of sequential instructions each time read permission is granted, regardless of the write operation to the data buffer. For example, as shown in the figure, after executing the data read of instruction 1, the contents of the queue '''l'' register are retrieved and the contents of the instruction 2 are read.
Then, the contents of the queue "O" register are retrieved and the data of instruction 3 is processed.

〔Effect of the invention〕

As described above, according to the present invention, the write control block and the read control block of the data buffer can be operated independently of each other at their respective optimal timings, so that the data buffer can be multiplexed and shared by a plurality of instructions. can be done efficiently.

[Brief explanation of the drawings] Figure 1 is an explanatory diagram of continuous execution of vector load instructions;
FIG. 3 is a block diagram of a data buffer according to an embodiment of the present invention, FIG. 3 is a block diagram of its data buffer control circuit, and FIGS. 4 and 5 are time charts of operation examples. In the figure, l is a data buffer, 2V'T is a write address register, 4 is a read address register, 6 is a write control block, 7 is a read control block, 8 is a write set address register, lO is a write element counter, and 13 is a queue 10” address register, 1
4H queue "'l" address register, 16 represents read set address register, 17 represents queue @'0" element register, 18 represents queue "'1" element register, and 20 represents read element counter. Patent applicant: Fujitsu Limited Representative patent attorney: Hiroshi Fumi (1 other person)

Claims (1)

[Scope of Claims] (1) A vector data processing device including a vector register, a main memory, and an access pipeline that transfers data between the vector register and the main memory, wherein the access pipeline includes a plurality of access pipelines. It has a data buffer, a write control block to the data buffer, and a read control block, and the write control block and read control block operate independently, and the data buffer can be shared by multiple instructions. A vector data storage control method characterized by: (2) In the above item 1, the read control block of the independently operating control block includes a circuit that reads and retains the start address and element number information of the data buffer from the write control block for each instruction.
1. A vector data storage control system, wherein one or more read control blocks are provided, and the read control block sequentially controls reading of data buffers according to the information. (8) In the above paragraphs 1 and 2, in a control block that operates independently, the control block is managed only by writing and reading in and out, regardless of load or store instructions,
A vector data storage control method characterized by processing in the same way regardless of the type of instruction.