JPS59122225A - Detecting circuit of reference voltage - Google Patents

Abstract

PURPOSE:To detect reference voltage including earth voltage stably and highly accurately by using a pair of voltage dividing circuits practically having the same constitution as an input circuit and a reference voltage circuit. CONSTITUTION:When input voltage VIN crosses zero voltage from negative to possitive voltage, the impedance of depression IGFETQ2 in an input circuit 1 is reduced lower than that of a depression IGFETQ4 in a reference voltage circuit 2, the output level of an enhancement FETQ12 is increased and the output level of an enhancement FETQ14 is reduced. Consequently, an FETQ12 in an output buffer circuit 4 is turned on, an FETQ17 is turned off, an FETQ19 is turned on, and output voltage VOUT is reduced from the high level to the low level close to VSS=0V, so that the earth voltage can be detected highly accurately even at a crossing moment.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor integrated circuits, and more particularly to a reference voltage detection circuit that changes an output signal when an input signal crosses a reference voltage level within an integrated circuit.

In various electronic circuits, it may be necessary to detect the moment when an input signal crosses a predetermined quasi-voltage.

In particular, zero-cross detectors that detect the moment when an input signal crosses the ground voltage (zero voltage) are in high demand in phase control circuits, etc. However, ordinary integrated circuits (A) operate between the ground voltage and the power supply voltage. Therefore, there was no device within the engineering C chip that could detect a voltage with the opposite polarity to the ground voltage or operating voltage.These reference voltage detectors were assembled on a printed circuit board using individual components, resulting in low cost and reliability. In general, the reference voltage in logic circuits such as inverters is the given power supply voltage V (OV) and vDDS (positive polarity in 0-MOS, N-MOS, P-MO
S is set within the operating voltage range between (negative polarity).

Furthermore, there is a certain overdrive voltage determined by process parameters and circuit constants, and the output signal will not be inverted unless the input voltage exceeds (reference voltage element overdrive voltage).Therefore, in conventional circuits, zero voltage is applied as the reference voltage, Even if a signal that changes between positive and negative is applied as an input signal, it is not possible to accurately detect the point where the input signal crosses zero voltage.Furthermore, using a reference voltage with a polarity opposite to the operating voltage is also a problem for integrated circuits. It was structurally impossible.

SUMMARY OF THE INVENTION An object of the present invention is to provide a reference voltage detection circuit that can detect with high accuracy even the moment when an input signal crosses a ground voltage in an integrated circuit.

According to the invention, the compression mode insulation date a
A pair of voltage divider circuits with substantially the same configuration including an h-effect transistor (XG-FBGT) is used as an input circuit and a reference voltage circuit, and each output is compared and amplified by a comparator circuit to achieve stable and high precision. Reference voltage can be detected. Despite having a simple and economical circuit configuration, extremely stable operation can be achieved even with power supply voltage fluctuations and temperature changes. Furthermore, all the components can be constructed from G-FETs, and the process can be manufactured using conventional processes. If the input circuit and reference voltage circuit are composed only of depletion E-G-FETs, it will be stable against variations in parameters in the manufacturing process, variations in exposure and etching steps, etc., and manufacturing will be easy and yields will be high. Eat it.

The following will be explained along with examples. In FIG. 1, the zero voltage detection circuit includes an input circuit 1, a reference voltage circuit 2, a comparison circuit 3,
Includes an output buffer circuit 4. The input circuit 1 and the reference voltage circuit 2 are the input voltage of the input terminal 5 and the ground voltage of the Vss line. 4-o, the operating voltage range (VSS -
Generates a reference voltage (57°) for comparison within (vDD). ■Yo is an inverted signal that changes in the opposite direction EF from “IN”.Depression Xa-FK
T Ql + Q3 have exactly the same characteristics Q□==
Q3λ is zero biased and exhibits a predetermined resistance value. The depression G-11T Q2 and Q4 have exactly the same characteristics (Q2=Q4), and their respective dates are connected to the input terminal 5 and the ground line, and V, v = ov
Shows the impedance corresponding to SS Engineering G4. Each series connection of Ql-Q2 + Qs-Q4 constitutes a voltage divider circuit. For example, as shown in Fig. 2, G-FET Q, l r Q2 z Q3
rQ4 are arranged close to each other and along the same direction within the substrate. Q engineering + Q3 is the same - design dimension, Q21
94 also has the same design dimensions. Diffusion region 11.11' connected to power line 18 and ground line 19.

13 and 13' are formed, and further diffusion regions 12 and 12' are formed in the middle. Gate electrodes 15, 15' are provided on regions that will become channels between the diffusion regions.

16 and 16' are formed. Number 11, 12゜1
3.15.16 and numbers 11' and 12'.

The parts indicated by 13', 15', and 1 B' have the same dimensions,
Made of the same material and created by the same process. Therefore, variations in process parameters such as excess or deficiency in exposure or etching steps, errors in mask alignment, etc. affect each transistor equally and do not affect the relative relationship of voltage division. Therefore, manufacturing is easy and a high yield can be obtained. Also a transistor. Since xpQ2pQ3rQ4 are all depletion type and act as mere branch FE@paths, they are not easily affected by changes in operating conditions. The voltage division ratio is determined only by the size ratio (w/L) of the channels of each transistor, and is not easily affected by fluctuations in power supply voltage, temperature changes, etc., and extremely stable and highly accurate operation can be obtained.

・ Depression E G-FHT Q2. . ,QaG;
It is designed to exhibit a finite source-drain impedance at i when a predetermined date bias including a reverse bias is applied to i. Zarani Depression E G-FETC
The design constants of each transistor are selected so that each divided voltage of h - Q2 r Qs - Q4 becomes a voltage suitable for operating the comparison circuit 3 in the subsequent stage. The comparison circuit 3 compares the comparison voltage signal (1) and the reference voltage signal (2)REF.

(Depression G-FET G7, Enhancement) The series connection of XG-FETQs is
- Supply constant voltage bias to FETQ15. In other words, the date/source directly connected G-FET G7 supplies a constant current to the date/drain directly connected G -FE' Supply to G15. FET
The constant current flowing through G15 is the branch of Qll-Qlz and Qls
-G14 branch, and constitutes a current switching type differential amplifier.

Qll + G13 is the depreciation filter G-FIICT which is biased to zero, and Q□21Q is the enhancement filter G-FIICT which receives each input signal to the differential amplifier.
It is FIT. The two outputs of the current switching type differential amplifier change in opposite directions.

The output buffer circuit 4 is an enhancement G-FET.
Q. , Q engineering y + Q yu, and depression e G-FIC
It receives the two outputs of the differential amplifier and generates a rectangular wave output voltage having a desired voltage swing width.

Referring to FIG. 6, the case of N-channel MO3-MO0 will be explained as an example. It is assumed that the input voltage (input voltage) gradually increases from negative polarity to positive polarity. While ■ is negative polarity, the resistance value of G2 is higher than the resistance value of G4, and ■ is ■"゛
It is at a higher level. VIN is Q12N
REF inverted, G16. G19 turns off and output terminal 6
Set the voltage ■ to high level (■DD). When the input UT voltage crosses zero voltage, the impedance of G2 becomes G4.
becomes smaller than the impedance of Q, increases the output level of Q, and lowers the output level of Q.

Therefore, G16 is on, G17 is off, and G19 is on, resulting in an output voltage of V. UT falls to a low level close to V,=OV.

In other words, the reference voltage (R]lcF of the comparator circuit is OV and G1 is not present, but when (Eyo) crosses (O)), VU (VU) crosses (VYA), and an inverted output waveform is obtained. Engineering G-PET
Q2 and G4 have exactly the same configuration, and the engineering G-PET Q
Since G and G3 have exactly the same configuration, the comparison voltage R also crosses the reference voltages RB and F at the moment the input voltage V crosses the reference voltage 0 from positive to negative and from negative to positive.

Assume now that a sine wave voltage is applied to the input terminal 5 as shown in FIG. ■The period of tl for >0 is V >V
Next door is V. UT is high-repe IN close to ■DD
Output FtEF le. V crosses OV, ■work, <0
From the moment when period t2 begins, ■H<VRF, F, and the comparator is reversed. UT becomes low level. Therefore, t1=t2, and an output signal that accurately matches the phase of the input signal is obtained. The output rectangular wave signal can be used for timing and phase control of logic circuits, memory circuits, etc. on the same chip.

Since zero voltage can be detected accurately and the output signal can be quickly changed, dead time in the circuit while the signal level is changing can be eliminated, and the degree of freedom in circuit design can be greatly increased.

All the components of this example are designed using the G-FF1T, and can be created at the same time and in the same process as other circuit components on the chip. Once the mask is completed, the manufacturing process is the same as before. It is.

In the above embodiment, the reference voltage was OV, but reference voltages other than 0■ can also be easily detected.

FIG. 5 shows another embodiment. Resistors R1 and R3 are used in place of the G-FET Ql and G3 in the embodiment shown in FIG. 1, and the dates of the FET G and -FIT G4 are derived to the reference voltage input terminal 7. It is similar to In this case, the resistors R and R3 are made completely equal, and the resistor G-FE is
It is important to create TQ2 and G4 exactly the same. The resistors R1 and R3 can be formed of, for example, a diffused resistor, an ion implanted resistor, or a polysilicon resistor.

For example, set the VG4 voltage to minus 1. OV or something plus 1.5
Since it can be freely adjusted by setting a specific inverted output such as V to an expected value, it is possible to use a "minus 1 Ov detector" or a "plus 1.5 ■ detector". In this case, the reference voltage V. How to give 4: How to make it internally or externally■. Both methods of providing four terminals and applying a reference voltage from the outside are possible.

・As a protection means for inputting an input signal containing a voltage with a polarity opposite to the operating voltage to the C-chip, for example, a configuration as shown in FIG. 6 may be used.

In the illustrated N-channel MO3-C, ■U and ■D
A lateral bipolar transistor consisting of an N region 21 and 22F substrate is formed between the N region 21 and the 22F substrate.

When the voltage becomes a negative voltage, the electrons injected from the N region 21 are collected in the N region 22 without spreading into the substrate, and the negative voltage, ■, becomes the input G-FET Q2.
The voltage is applied to the gate of the gate to adjust its source-drain resistance. In the case of the embodiment shown in FIG. 5, if the protection means shown in FIG. 6 are provided for each of the input terminal 5 and the reference voltage terminal 7, the reference voltage having the opposite polarity to the operating voltage can be manually generated.

Although the present invention has been described above with reference to the embodiments, it will be obvious to those skilled in the art that various modifications, combinations, and changes can be made.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a partial top view of a chip incorporating the circuit of FIG. 1, FIGS.
The figure is a characteristic diagram of the circuit in Figure 1, and Figure 5. Explanation of symbols 1... Input circuit, 2... Reference voltage circuit, 3... Comparison circuit, 4... Output buffer circuit, 5... - Input terminal, 6... Output terminal. Agent Asamura Kōgai 4 people Figure 1 To □ - Niga 3 Figure 4

Claims (1)

[Claims] (1) In an integrated circuit that is supplied with a predetermined power supply voltage (XX) and a ground voltage (SS) and operates in a voltage range between the two voltages, (a) an input that includes a voltage level exceeding the above voltage range; an input circuit for receiving the signal; and a reference voltage circuit for receiving the selected reference voltage signal, both circuits including substantially identical voltage divider circuits including depression mode field effect transistors; The above voltage range ('v, v) depending on the input signal and reference voltage signal
an input circuit and a reference voltage circuit that generate a comparison voltage signal and a reference voltage signal; A reference voltage detection circuit including an amplification circuit detects and amplifies the moment it crosses the line and generates a rectangular wave within the voltage range (VSS'DD). (2. The reference voltage detection circuit according to claim 1, wherein each of the input circuit and the reference voltage circuit includes a depression mode field effect transistor connected in series, and the input signal or the reference voltage A reference voltage detection circuit in which a signal is applied to the gate of one of the field effect transistors connected in series. (3) The reference voltage detection circuit according to claim 1, wherein the field effect transistor is connected to the integrated circuit. Reference voltage detection circuits located close to each other and in the same direction within a circuit chip.