JPS59119921A - Analog/digital converter - Google Patents

Abstract

PURPOSE:To exclude a sampling/holding circuit with a serial-parallel type A/D converter by using the reference voltage having the 2nd highest and lowest levels close to the input signal which is decided by a comparator group of the preceding stage as the reference level to a comparator group of the following stage. CONSTITUTION:A serial-parallel type A/D converter decides high-order bits by the 1st comparator group 21 and at the same time controls the reference voltage (secondary reference voltage) to the 2nd comparator group 23 which decides low-order bits. In this case, the 2nd highest and lowest level voltages V1 and V4 close to an input signal Vin are used as the secondary reference voltage. As a result, the signal Vin is set between high and low levels of the secondary reference voltage even after the lapse of a time DELTAtpc during which the secondary reference voltage is set. This converter excludes a sampling/holding circuit and therefore simplifies the circuit constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an analog-to-digital converter with a simple configuration (number of elements) capable of performing high-speed, highly accurate analog-to-digital signal conversion.

[Technical background of the invention and its problems]

Conventional A/D converters that perform high-speed A/D conversion of television signals, etc. usually have (2''-') comparators arranged in parallel, where n is the number of conversion bits. However, in an A/D converter with such a configuration, as the number of conversion bits n increases, the number of required comparators increases exponentially, making integration extremely difficult. This not only makes the process difficult, but also increases power consumption.

To solve this problem, a series-parallel type comparator, in which the comparator is divided into a front stage and a rear stage, has been put into practical use, for example, as shown in FIG.

That is, the A/D converter shown here is of the so-called 2-bit glass 2-bit 4-bit type, and is composed of a front-stage conversion section and a rear-stage conversion section. That is, the analog signals sampled and held in the sample circuit are commonly input to the comparators 2aH2b+2c provided in parallel in the previous stage conversion section, and are input to the resistors 3a and 3b connected in series.
.

3 c v 3 d is driven by a constant current source 3 e to compare the level with a plurality of comparison reference voltages.

The comparison results of these comparators 2a + 2b y 2c are input to an encoder 4, and the analog signal level is coarsely discriminated, and the upper 2 bits of digital data are generated. The output of encoder 4 is still connected to local D/A.
A reproduced analog signal corresponding to the above-mentioned digital data is obtained by inputting it to a converter 5, and this is inputted to a subtractor 6 to find the difference between it and the previous analog signal. This analog signal difference consists of signal components below the minimum discrimination level that were not converted by the preceding digital conversion process. Therefore, the output of this differentiator 6 is commonly led to comparators 7a, 7b, and 7c arranged in parallel at the subsequent stage,
A resistor 8a connected in series.

The level is compared with a second comparison reference voltage obtained by driving 8b+8 (218d with a constant current source 8e).

The comparison results of the comparators 7a, 7b, and 7c are sent to the encoder 9.
Then, the lower two bits of digital data are obtained. still,
The comparison reference voltage difference of the front-stage conversion section is set to 2n times the comparison reference voltage difference of the rear-stage conversion section (where n is the number of lower bits). As outputs from the encoders 4 and 9, a total of 4-bit digital signal consisting of the upper 2 bits and the lower 2 bits is obtained.

According to the A/D converter configured in this way, high-speed and high-precision A/D conversion is achieved by parallel level comparison and level comparison in which reference levels corresponding to conversion accuracy are set in multiple stages.
Conversion processing can be performed. However, this A/D converter performs analog processing in which the local D/A converter 5 obtains the analog voltage indicated by the upper 2 bits of digital data, calculates the difference from the input analog voltage, and uses it to convert the lower bits. Requires. For example, as shown in FIG. 2(a), the local D/A converter 5 is constituted by current switches made of transistors and ladder resistors whose currents are switched by these current switches. Therefore, errors are likely to occur in the converted analog voltage due to variations in the ladder resistance and fluctuations in current. That is, the local D/A converter shown in FIG. 2(a) is shown as shown in FIG. 2(b) under equality constraints, and resistors Rc, R, and transistor T
Its output voltage V depends on the variation in the pace-emitter voltage vB8 of R. The following errors occur. That is, if the errors are expressed as ΔV, ΔR (+ΔRF, IΔvB8, respectively), an error of the following relationship will occur: ΔvoΔRc ΔR8ΔVBIi ■0RCREVE However, vIC is the voltage across the resistor island'), and 'c is the collector voltage of the transistor TR. It is. Therefore, the pairwise error of the resistor Rcf RE generally exists on the order of ±0.5 mV, and the variation in vBE exists on the order of ±1 mV. Therefore, even if Rc and RIC are equal, in the worst case, the output voltage V. An error of Δvo//'voy±1% occurs. In order to prevent A/D conversion errors caused by this error, it is necessary to suppress the output voltage error to less than ILSB, which requires an extremely highly accurate local D/A converter. In addition, if this error cannot be suppressed, a so-called connection error will occur at the bit data change point of the upper bits as shown in Figure 3, and it will not be possible to perform high-precision A/D conversion with good linearity. It disappears.

Therefore, the present inventors have first developed a method to perform high-precision A/D conversion with good linearity at high speed without causing connection errors due to errors in the local N/A converter. Patent application for a highly practical A/D converter on January 67, 1983
548, etc.

This analog-to-digital converter compares the analog input signal with multiple comparison reference voltages using multiple comparators installed in parallel, obtains the upper bit digital data from the comparison results, and converts the analog input signal to the analog signal according to the comparison results. Selectively extract a high-level reference voltage and a low-level reference voltage that are closest to the level of the input signal, input these reference voltages to both ends of a voltage divider, and divide the voltages to obtain multiple secondary reference voltages. By comparing the level with the analog input signal again to obtain dizotal data of the lower bits, connection errors are prevented and the A/D has good linearity and high precision.
This makes conversion possible.

The A/D converter will be briefly explained below.

FIG. 4 is a schematic diagram of the above-mentioned A/Di converter, which is a 4-bit conversion type of 2 bits plus 2 bits. The analog input signal is sampled and held by the sampling circuit 1 and three comparators 12a configured in parallel.
+ l 2 b + l 2 c are input in common. These comparators 12a, 12b, and 12C are each supplied with a comparison reference voltage of a predetermined level generated by the reference voltage generator 13, and the analog input voltage is level-compared with each of these comparison reference voltages. .

The reference voltage generator 13 includes four resistors 13a, 13 connected in series, each having one end fixed at a predetermined potential vr8f.
A constant current is supplied to b, 13ce13d by a constant current source 13e, and each resistor 13 a + 13 b v 13
A reference voltage of a predetermined level is generated from the e + l 3 d terminal.

Therefore, each reference voltage is, for example, vref *Vlt
+Vto, Vol, v. A constant level difference is set as 0. The level difference between vref and Voo is set equal to the dynamic range of the analog input voltage. Of these reference voltages, the comparators 12a+12b+12c respectively input Vll + vio f VOI and compare the levels with the analog input voltage level. For example, when vll, Vto, vOIn ≦■in, the logical °° A signal of "1" is output as the comparison result, and in other cases, a signal of logic "On" is output as the comparison result.

Therefore, the outputs of these comparators 12ae12b+12c are connected to four exclusive OR circuits (EX-
OR) l 4 a v l 4. b + 14c+
14d is given to each of the two adjacent threads. E
The X-OR 14a inputs the logic "1" signal and the output of the comparator 2a, and the EX-OR 74b inputs the logic "1" signal and the output of the comparator 2a.
b, and EX-OR14c is the comparator 12b.
, J2c, and EX-ORl 4 d
The output from the comparator 12c and the logic "0" signal are inputted to the respective logic processors. These EX ORl 4
a * 14 b +) 4c and 14d are input to the encoder 15 for encoding processing, and here the upper 2 bits of the digital data for the analog input voltage vin discriminated by the comparison reference potential v11 + VI Ol vo 1 are input. We are getting data.

Meanwhile, the comparison reference voltage Vr6ftV11 t VIOHVol , Vo generated by the reference voltage generator J3. is the above EX-OR14a t 14 b t 14 c
, 14d are input to switch circuits 16a, 16b, 16c, and 16d whose conduction is selectively controlled by the outputs of 14d. These switch circuits 16FL+16b*1
6c + l 6 d is the comparison reference voltage vr8f.

A resistor 17a connected in series selects a reference voltage which is higher in level than the analog input voltage vin among Vll +V10t v and has the lowest level among them;
17b, 17c, and 17d, and the comparison reference voltages V1□, v1°,
Analog input voltage vin from vo, , Voo
The reference voltage which is lower than the level of the reference voltage and has the highest level among them is selected and supplied to the other terminal of the voltage divider. Therefore, EX-ORl 4 a , l 4
Switch circuit 16 a + 16 b + 16 c + noro d controlled by the outputs of b * 14 e, 14 d
A high level reference voltage and a low level reference voltage that are closest to the level of the analog input voltage (in) are selected and applied to both gates of the voltage divider. Further, the resistors 17a+17b, Noah c, and 17d constituting this voltage divider have, for example, mutually equal resistance values, and equally divide the potential difference between the selected and applied reference voltages to generate a secondary reference voltage. The secondary reference voltage v119 vlo rυ
Each potential difference of 0□ is a converted minimum bit value, that is, the LSB. These secondary reference voltages υ□1°vlo and τ01 are applied to comparators J8a and 1Bbl18c which commonly input the analog input voltage, and are used to determine the level of the analog input voltage ■in. After obtaining the level determination results of these comparators 18aH18br)8c, the encoder 19 converts the analog input signal V
The lower two bits of digital data for in are obtained.

According to the A/D converter configured in this way, if the level of the analog input voltage vIn is between the reference voltage VIO+Vll, Vo o < Vo 1 < Vt o < V (n < Vl
From the relationship t < Vr, f, comparator) 2b, 1
2c outputs a logic "0", and the comparator 12a outputs a logic "1#". Therefore, based on the results of these comparisons, only the EX-ORl 4b obtains a logic "1" output, which causes the switch Circuit 16b is alternatively rendered conductive. As a result, the reference voltage Vll on the high level side and the reference voltage VIO on the low level side which are closest to the level of the analog input voltage V in are selected and applied to both ends of the voltage divider. Assuming that the potential difference between adjacent reference voltages is 4V, the voltage divider divides this into four equal parts to generate a secondary reference voltage v+11 vlo +τ0□. Therefore, these secondary reference voltages are vtt = υto +3 u υ10 =V1(1+'?u vot = V10+υ.The analog input voltage vin is 1, and the level is discriminated at a finer level by these secondary reference voltages τlitυlO+υ01. Ru.

Therefore, the analog input voltage vin is
, 12b, and 12c perform level discrimination in a coarse quantization step and convert it into high-order bit digital data, and then the subsequent comparators J8a, 18b+18c have finely set comparison level regions according to this converted data.
The level is discriminated by fine quantization steps and converted into lower bit digital data. Therefore, if the upper and lower bit data obtained by the encoder 15*19 are combined, the analog input voltage ■i
De(notal data) corresponding to the level n can be obtained.

Thus, according to this A/D converter, the reference voltage used for digital conversion of the upper bits is selectively extracted according to the conversion data of the upper bits, and this reference voltage is directly used to obtain the secondary reference voltage. Since the lower bits are used for digital conversion, the level relationship between the secondary reference voltage set according to the level of the analog input voltage vin and the reference voltage has very good linearity.

Moreover, unlike conventional methods, the upper bit data is locally D/D/
Unlike the method in which the voltage for lower bit conversion is obtained from the level difference with the analog input voltage vin through A conversion, analog signals are not handled in this processing, so there is no occurrence of connection errors. Since digital conversion is performed by directly determining the level of the analog input voltage (in), the conversion characteristics (linearity) are extremely good. Furthermore, since analog processing circuits such as conventional local D/A converters are not required, the configuration can be greatly simplified, and a great practical effect can be achieved.

By the way, when configuring the above A/D converter, EX
-OR and switch circuits may be configured as shown in FIG. 5 with equal constraints, for example. That is, the reference voltage Vr6f l ”
111 VIOt vot l voo is inputted through one follower transistors A and B, respectively, and the output thereof is given to current switch transistors C and D, respectively, which are formed by connecting the emitter and the rear in common. These current switch transistors C and D are connected to comparators 12 &
The conduction is selectively controlled through a switch transistor E r F which operates in 0N10FF mode upon receiving the outputs of e12b and e12c. A voltage divider is connected between the commonly connected emitters of the current switch transistors C and D to obtain secondary reference voltages.

According to the switch circuit constituted by such a transistor circuit, the conduction of the switch transistors E and F causes current to be sucked into the current switch transistors C and D, and the corresponding current switching transistor C9D eventually becomes energized. It will operate OFF. As a result,
The highest level of the reference voltages applied to the current switch transistors C and D in the conducting state will appear at their emitters, and the reference voltage will be selected under the conditions described above. .

Incidentally, when the reference voltage is selectively extracted in this way to generate the secondary reference voltage, the emic follower transistor A
9B and current switch transistors C and D over two stages, a level shift of the reference voltage occurs.

Therefore, when the switch circuit is configured in this way, the subsequent comparators 18a, II! For example, the analog input voltage ■in dedicated to llb and 18c is shown in FIG.
The signals may be applied via the Hiko level shift circuit as shown in b). Figure 6(,) shows a two-stage Darlint-connected transistor that applies the same level shift to the analog input voltage ■in as the previous reference voltage. A similar exhaustive shift is provided by an emitter follower transistor configured as follows.Regardless of which level shift circuit is used, the key is to provide the same amount of level shift to the analog input voltage and the selected reference voltage. , and maintain that level relationship.

If the switch circuit is still configured using a MOS transistor, it can be realized as shown in FIG. 7, for example. In this case, each reference voltage may be selected using a MOS transistor as a switch, and the selected reference voltage may be applied across the capacitors connected in series to divide the potential difference.

Even if the switch circuit is constituted by a transistor circuit or a MOS transistor circuit in this way, it is basically equivalent to the switch circuit shown in FIG. 4. Therefore, when constructing an actual circuit, it is only necessary to design it after considering the specifications required of the A/D converter and the characteristics of the constituent elements.

However, when realizing an A/D converter having such a configuration, the existence of the sample and hold circuit 1 is extremely important. Despite this, in order to realize the sample-and-hold circuit 11 that can cope with high-speed operation of A/D conversion processing, it is necessary to configure a high-speed switching circuit, and usually a Schottky junction diode or a Schottky junction diode capable of high-speed switching operation is used. High frequency pnp) transistors are used. However, it is very difficult to integrate these elements on the same chip together with the elements that perform all stages of A/D conversion, and there is a problem in practical implementation that this increases manufacturing costs. there were.

[Purpose of the invention]

The present invention was made in consideration of these circumstances, and its purpose is to perform high-speed, high-precision analog-to-digital signal conversion with a small number of elements without the need for a sample/hold circuit. An object of the present invention is to provide an analog-to-digital converter that can be easily integrated into an integrated circuit.

[Summary of the invention]

The present invention basically has the same principle of operation as the previously proposed A/D converter, but according to the level of the analog input signal determined by the group of comparators in the previous stage, a second level is added to that level. A high-level reference voltage close to the above level and a low-level reference voltage close to the above level are obtained, and from these selected reference voltages, a secondary reference voltage for the subsequent comparator group is obtained, and the sample is - Eliminates the need for a hold circuit. In other words, the conversion process is executed in real time by setting the secondary reference voltage for the subsequent comparator group in anticipation of the change in the analog signal level.

〔Effect of the invention〕

Therefore, according to the present invention, there is no need to simultaneously integrate sample and hold circuits that require high-speed operation with elements such as comparators that perform A/D conversion processing, and there is no need to simultaneously integrate sample and hold circuits that require high-speed operation.
Since the hold circuit itself is not required, the configuration can be greatly simplified, and practical effects such as ease of implementation into an actual circuit can be achieved.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 8 shows the conceptual configuration of the A/D converter according to the embodiment, in which a first comparator compares the levels of the analog input signal V and a plurality of reference voltages having different levels. Group 2, a secondary reference voltage circuit 22 that obtains secondary reference voltages according to the comparison results of the first comparator group 2, and compares these secondary reference voltages with the level of the analog input signal ln, respectively. It is constituted by a second comparator group 23. These first and second comparator groups 23 are constructed similarly to the comparator group shown in FIG. 4 described above. A feature of the A/D converter is that the analog input signal vin can be directly input to the first signal without going through a sample/hold circuit.
and the second comparator group 21 and 23, respectively. At the same time, the secondary reference voltage applied to the second comparator group 23 is input to the analog input signal Vin17).
It is characterized in that it is obtained from a high-level reference voltage that is second closest to l/bell and a low-level reference voltage that is second closest to the above-mentioned level.

That is, the analog input signal ■in is input to the first comparator group 2 to obtain the comparison result, and the second comparator group
Until the secondary reference voltage for the comparator 22 is set,
A finite amount of time is required. Assuming that this finite time is Δtpc, the level of the analog input signal 1n changes, albeit slightly, during that time, and the second comparator group 23 has a different level from the first comparator group 2. Analog input signal Vj
A comparison operation will be performed for n.

Therefore, this A/D converter is configured to obtain a secondary reference voltage in a reference voltage range that is greater than or equal to the maximum change level of the analog input signal that changes during the delay time Δtpc. For example, when considering an NTSC television signal, its band is 4.3 MHz. Therefore, let us assume that the level V of the analog input signal Vin is represented by v=vos ωt, and find its maximum slew rate. However, the signal amplitude V. It is assumed that IVolt is ω and the angular frequency ω is ω=2πf (f: 4.3 MHz). The maximum throughput and rate at this time are expressed as θV −=vo·ω=ω=2πf θt, and the following relationship exists regarding the delay time Δtpc.

Δtp (H=10 n5
If ec is required, the level of the analog input signal ln will change by ΔvPo=270 mv at the maximum.

Therefore, when considering such a level change, since the level change may be positive or negative, it is necessary to set the range of the secondary reference voltage given to the second comparator group 23 to be equal to or greater than ΔVPC. It turns out to be a good thing.

Therefore, in this A/D converter, as shown in FIG. 9, the comparison voltage applied to the first comparator group 2noa, 21bg21c is
Depending on the level V of the analog input signal Vin, if there is a relationship such as V3 < V < V2, for example (B), the level is one step higher than the high level v2 which is closest to the above level ■, that is, the second closest 2 to the reference voltage of high level V1 and the above level ■
The lowest level ■4 reference voltage is selected, and the difference between these reference voltages is divided by the series resistor group 24 to obtain 2.
Next, the levels of the reference voltages are respectively set. These secondary reference voltages are then applied to the second comparator group 23.
a + 23 b to 23n respectively. Incidentally, it goes without saying that the voltage "IL8B" which determines the I LSB voltage of the first comparator group 21 a r 2 l b , 21 c is set to be larger than the maximum slew rate voltage ΔVpcJ:D. Also, this voltage VILSB is the input dynamic range of the analog input signal ■in, for example 2
000 mV, the number of conversion bits m of the first comparator group 2)
In relation to the value of , it is practically desirable to define it as . In this case, it is necessary to make the voltage v1LsB higher than ΔVPC, so
If the value of m is set to 5 or less and VILSB≧62.5 mV, the above-mentioned case of Δtpc=1.0 n5ec can be sufficiently coped with. Table '2 shows this relationship.

Table 2 However, in Table 2, NP indicates the number of comparators constituting the first comparator group 2, and NF indicates the number of comparators constituting the second comparator group 23.

As shown in Table 2, the maximum slew rate voltage ΔvPc of the analog input signal is 35.8 mV, the dynamic range is 20000 mV, Δtp(is 1, On5
In the case of ec, if the first comparator group 2) is configured using 31 comparators and the second comparator group 23 is configured using 23 comparators, the total comparator Reduce the number A
/D'R converter can be constructed.

FIG. 10 shows a configuration example of the secondary reference voltage generation circuit 22 that generates the secondary reference voltage to be applied to the second comparator group 23 according to the comparison result of the first comparator group 2 described above. , which is basically constructed similarly to that shown in FIG. The differential switching transistors are given the comparison results of the first comparator group 2. Then, by the operation of these differential switching transistors, transistor groups C and D are selectively controlled to conduct, and a reference voltage is selected according to the analog input signal level and is applied across the series resistor group 240. Therefore, the second comparator group 23 receives the secondary reference voltage in the voltage range mentioned above and converts the analog input voltage vin into a digital signal.

FIG. 11 schematically shows the operation of the present A/D converter having such a configuration.

Then, in the second comparator group 23, from the existence range of the input signal level determined from the comparison result of the first comparator group,
Comparison processing is performed within a range that takes into account the level change.As a result, level comparison may be performed in areas a and c that are outside the previously detected level range, but in this case, The first comparison result (MSB side data) may be incremented by one or minus one according to the information in the area ate, and the level change may be corrected by logical processing.

Thus, according to the present invention, it is possible to digitally convert an analog input signal without using a sample-and-hold circuit.

Furthermore, digital conversion can be performed at high speed and with high precision, which has tremendous practical advantages.

Note that the present invention is not limited to the embodiments described above. Although FIG. 11 shows the effect of 4-bit A/D conversion processing, it goes without saying that it can be similarly applied to A/D conversion with a larger number of pits, such as 8-bit A/D conversion. Further, as shown in FIG. 12, if the I LSB voltage of the first comparator group 2 is set to 1/2 VILSB voltage, the reference voltage range of the second comparator group 23 is (4×VIL8
B). In this case, the third
The configuration conditions of the A/D converter can be determined as shown in the table.

As shown in Table 3 and FIG. 13, I L of the first comparator group 2
When the SB voltage is (2XviLsn), the second
The reference voltage range of the comparator group 23 is (2,5°×vIL8
B). In this case, the configuration conditions of the A/D converter are as shown in Table 4.

Table 4 In this way, depending on the value of ■1LsB, the first and second
Determine the number of each comparator in the comparator group 21.23,
Moreover, by determining the range of the secondary reference voltage, high-speed and highly accurate conversion is possible without using a sample-and-hold circuit.

In short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram showing an example of a conventional A/D converter, Figure 2 is a block diagram showing an example of a conventional A/D converter.
Figures (,) (b) are diagrams showing the configuration of a local D/A converter and its equivalent circuit, Figure 3 is a diagram showing connection errors, and Figure 4 is a diagram showing the basic A/A converter that is the basis of the present invention. A schematic configuration diagram of a D converter, FIG. 5 is a diagram showing an example of the configuration of a switch circuit of the A/D converter, FIGS. 6(a) and 6(b) are diagrams showing an example of the configuration of a level shift circuit, and FIG. The figure shows a switch circuit composed of MOS transistors, and FIG.
FIG. 9 is a conceptual block diagram of a D converter, FIG. 9 is a block diagram of main parts of an embodiment of the present invention, FIG. 10 is a block diagram of a switch circuit in the same embodiment, and FIG. 11 is a diagram showing the operation of the same embodiment. The signal level diagrams shown in FIGS. 12 and 13 are main part configuration diagrams showing other embodiments of the present invention, respectively. 71...Sample circuit, 12ar12b+12c・
...Comparator, 13...Reference voltage generator, 14ar14
b, 14c, 14d...exclusive OR circuit, 15.=
Encoder, 16a, Noro b+16c+16 d 7-
・Switch circuit, 77 (77a+77b+17C)
=-voltage divider, 18a, no8b, l8c - comparator, 19... encoder, 21 (21a +21
1], 21c)...first comparator group, 23(23a
, 23b to 23n) - second comparator group. Applicant's representative Patent attorney Takehiko Suzue Figure 6 (a) (b) Figure 7 Figure 8 Figure 9

Claims (2)

[Claims] (1) A first comparator group that compares the level of the analog input signal with a plurality of reference voltages having different levels, and a first digital signal corresponding to the analog input signal from the comparison result of the first comparator group. a high-level reference voltage closest to the analog input signal level, a higher-level reference voltage and a low-level reference voltage closest to the analog input signal level according to the comparison result of the first group of comparators; Means for independently selecting a reference voltage and a reference voltage at a lower level, and means for inputting these selected high-level and low-level reference voltages and dividing the potential difference to generate a plurality of secondary reference voltages. a second comparator group for comparing the plurality of secondary reference voltages and the level of the analog input signal, and a second comparator group for comparing the level of the analog input signal with the plurality of secondary reference voltages; and means for obtaining a digital conversion value of the analog input signal from the second digital signal value and the first digital signal value. vessel. (2) The means for obtaining the secondary reference voltage consists of a plurality of resistors connected in series to both ends of which selected high-level and low-level reference voltages are input.
Analog-to-digital converter as described in section.