JPS59115605A - Limiter - Google Patents

Abstract

PURPOSE:To offer a limiter suitable for circuit integration by obtaining a limiter output in the differential form and setting freely the limited DC level. CONSTITUTION:A collector current of a transistor (TR)Q1 is denoted as IA and the sum of collector currents of TRsQ2, Q3 is denoted as IB. Further, when an input signal voltage Vi at a terminal T1 is shown in the waveform of the figure A, since the Q2 is turned off, the Q3 is turned on, and the Q1 is turned on at a period ta of Vi<=Vr and the TRsQ1, Q3 act like a differential amplifier, the current IA is the in-phase waveform corresponding to the input voltage Vi as shown in solid lines in the figure C, and the current IB becomes the waveform in opposite phase to the IA. Further, since the Q2 is turned on, the Q3 is turned off, the Q1 is turned on, the TRsQ1, Q2 act like a differential amplifier and the base input to the Q1, Q2 is equal at a period tb of Vi>Vr, then the currents IA, IB become respectively constant values I1, I2 shown in solid lines in the figure C. The limited DC levels I1, I2 of the output currents IA, IB are set freely by the constant current sources I1, I2.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a limiter suitable for IC implementation, for example.

BACKGROUND TECHNOLOGY AND PROBLEMS FIGS. 1 to 3 each show an example of an IJ limiter. In the limiter shown in FIG. 1, the input signal voltage V7
When V7≦V with respect to the reference voltage vr, transistor Q1 is off and transistor Qb is on, vi
〉■When 1, transistor Q.

is turned on and transistor Qb is turned off, so that a portion of the input signal that is higher than the voltage vr is taken out as an output.

In addition, in the limiter of FIG. 2, transistors Q, tQb
Since the on/off relationship is opposite to that of the limiter shown in FIG. 1, the portion of the input signal below the voltage vr is extracted as the limiter output.

However, with the limiters shown in FIGS. 1 and 2, it is not possible to obtain an output in a differential format. Moreover, the limiter shown in FIG. 2 requires PNP type transistors Q, Q, Q, and is not suitable for IC implementation.

In this respect, in the limiter shown in Fig. 3, the output is obtained in a differential format, but the DC level of the output is 90 (the voltage of the input signal V
Since it is not possible to freely select the DC level at the point corresponding to , it is difficult to connect directly to the next stage, and from this point of view it is not suitable for IC implementation.

OBJECT OF THE INVENTION The present invention aims to provide a limiter that eliminates these problems.

SUMMARY OF THE INVENTION Therefore, in the invention, a limiter is configured as shown in FIG. 4 or FIG. 6.

In the embodiment, namely, in FIG. 4, input terminals T are connected to transistors Q1. Constant current sources I, II, are connected to the pace of transistor Q2, and between the emitters of transistors Q1+Q,2 and a predetermined potential point, for example, ground. Also, the transistor Q1. A resistor R is connected between the emitter of Q2, and the collector and emitter of transistor Q3 are connected in parallel between the collector and emitter of transistor Q2, and a reference voltage vr for limit level is supplied to the pace of transistor Q3. be done.

Note that the constant current (sinking current) of the constant current sources I, , I2 is set to I4. If I2, then I, = I, for example. Also, transistor Q is always on (active region)
It is said that

In such a configuration, let the collector current of the transistor Q1 be the sum of the collector currents of the IA1 transistors Q2*Q5. If the input signal voltage V (of the terminal T1) has a waveform as shown in FIG. 5A, for example, during the period t8 when Vi≦vr, as shown in FIG. 5B,
Transistor Q2 is off, transistor Q3 is on, and transistor Q is on. Therefore, during the period ta, the transistors Q1 and Q3 work as a differential amplifier, so that the current IA has a waveform of +S corresponding to the input voltage ■i, as shown by the solid line in FIG. . has a waveform with the opposite phase to the current flow □.

Further, during the period tb where Vi>vr, as shown in FIG. 5B, the transistor Q is on, the transistor Q3 is off, and the transistor Q1 is on. Therefore,
During the period tb, the transistors Q1 r Q2 function as a differential amplifier, and at this time, the transistors Q1 .
Since the pace input of Q2 is equal, the currents □, ■, are given a constant value of 11, I2, as shown by the solid line in Figure 5C.

Thus, according to the present invention, for example, with respect to the input voltage V7 as shown in FIG. 5A, the portion below the voltage Vr can be extracted as the current IAI I as a limit output as shown in FIG. 5C. At the same time, its output current I,
, IB can be obtained in differential form.

Furthermore, the DC level 1 at the cutoff point of the output current ■□I I
1*I2 can be freely set using constant current sources I and II2, making it easy to connect directly to the next stage. Furthermore, it has excellent temperature characteristics and does not require a PNP type transistor, which is also advantageous for IC implementation.

In the example shown in FIG. 6, the supply relationship between the voltages Vi and (1) is reversed from that in the example shown in FIG.

Therefore, in its operation, as shown in FIG. 7, a portion of the p1 input terminal vi that is equal to or higher than the voltage Vr can be taken out.

Effects of the Invention The limiter output can be obtained in a differential format, and the DC level of the cutting edge can be freely set. Also, IC
It is also suitable for

Figures 4 and 6 are connection diagrams of an example of the present invention.

I4. I2 is a constant voltage source.

Figure 5

Claims (1)

[Claims] the first to third transistors, the paces of the first and second transistors are connected in common, the emitter of the first transistor is connected to a first constant current source, and the second and third transistors are connected in common; The emitters of the transistors are connected to each other and to a second constant current source, and a resistor is connected between the emitter of the first transistor and the emitters of the second and third transistors. and the above second
and the collectors of the third transistor are commonly connected, and an input signal and a reference voltage are supplied to the first and second transistor paces and the third transistor pace, respectively. A limiter in which limiter outputs are taken out from the collector of the transistor and the collectors of the second and third transistors, respectively.