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JPS59114663U - Vertical synchronization circuit - Google Patents

Vertical synchronization circuit

Info

Publication number
JPS59114663U
JPS59114663U JP705283U JP705283U JPS59114663U JP S59114663 U JPS59114663 U JP S59114663U JP 705283 U JP705283 U JP 705283U JP 705283 U JP705283 U JP 705283U JP S59114663 U JPS59114663 U JP S59114663U
Authority
JP
Japan
Prior art keywords
vertical synchronization
circuit
input terminal
synchronization circuit
synchronization signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP705283U
Other languages
Japanese (ja)
Inventor
西沢 文俊
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP705283U priority Critical patent/JPS59114663U/en
Publication of JPS59114663U publication Critical patent/JPS59114663U/en
Pending legal-status Critical Current

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  • Synchronizing For Television (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図はこの考案の一実施例を示すもので、第1図はブロッ
ク図、第2図は第1図における要部特性図である。 図中、1は入力端子、2は遅延回路、3はスイッチ回路
、4は制御回路、6は出力端子である。
The figures show one embodiment of this invention, with FIG. 1 being a block diagram and FIG. 2 being a characteristic diagram of the main parts in FIG. 1. In the figure, 1 is an input terminal, 2 is a delay circuit, 3 is a switch circuit, 4 is a control circuit, and 6 is an output terminal.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)垂直同期信号が供給される入力端子と、この入力
端子に接続され、垂直同期信号を水平走査期間の1/2
の期間遅延する遅延回路と、上記入力端子および遅延回
路に接続され、いずれか一方の信号を切替えて出力する
スイッチ回路と、このスイッチ回路を1垂直期間毎に駆
動する制御回路とを備えた垂直同期回路。
(1) An input terminal to which the vertical synchronization signal is supplied, and a terminal connected to this input terminal to transmit the vertical synchronization signal to 1/2 of the horizontal scanning period.
, a switch circuit connected to the input terminal and the delay circuit to switch and output one of the signals, and a control circuit to drive the switch circuit every vertical period. synchronous circuit.
(2)制御回路を垂直同期信号によって動作させるよう
にしたことを特徴とする実用新案登録請求の範囲第1項
記載の垂直同期回路。
(2) The vertical synchronization circuit according to claim 1, wherein the control circuit is operated by a vertical synchronization signal.
JP705283U 1983-01-19 1983-01-19 Vertical synchronization circuit Pending JPS59114663U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP705283U JPS59114663U (en) 1983-01-19 1983-01-19 Vertical synchronization circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP705283U JPS59114663U (en) 1983-01-19 1983-01-19 Vertical synchronization circuit

Publications (1)

Publication Number Publication Date
JPS59114663U true JPS59114663U (en) 1984-08-02

Family

ID=30138587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP705283U Pending JPS59114663U (en) 1983-01-19 1983-01-19 Vertical synchronization circuit

Country Status (1)

Country Link
JP (1) JPS59114663U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63142775A (en) * 1986-12-04 1988-06-15 Matsushita Electric Ind Co Ltd Field discrimination circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63142775A (en) * 1986-12-04 1988-06-15 Matsushita Electric Ind Co Ltd Field discrimination circuit

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