JPS59100561A - Semiconductor device and method of producing same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to semiconductor devices and structures, and more particularly to polycrystalline silicon layers for integrated circuit devices and structures.

[Background of the invention]

It is known that semiconductor devices, particularly integrated circuit structures, include multiple polycrystalline layers. As such devices have become smaller and more complex in design, many vertical layers of various materials have been stacked one on top of the other. Such devices include multiple layers of polycrystalline silicon, all or part of which can be battened, doped with various materials, and oxidized to form an overcoat layer such as silicon dioxide. many.

As design requirements for semiconductor structures and devices become more stringent, it is necessary to reduce the thickness of each layer, make the properties uniform, and improve smoothness. 17) When a dielectric material such as silicon dioxide is sandwiched between two conductive layers, one or both of which are made of rough polycrystalline silicon, the electric field applied to the structure is The electric field may be localized and concentrated on the protrusions of the electrode, generating an even stronger electric field and damaging the adjacent dielectric layer. More importantly, current can easily flow between the two conductive layers by penetrating the conductive layer between the protrusions or protrusions on the surface of one or both of the conductive layers.
It became clear that this was the case. Such a phenomenon will cause dielectric breakdown over time. Therefore, it is essential that the polycrystalline silicon layer has as flat a Pft as possible.

In addition to this extremely strict requirement for smoothness, the polycrystalline silicon layer of complex integrated circuit devices has almost no distortion, has good crystal integrity within each grain, has a smooth surface, and has a uniform grain structure. It was determined that the material was suitable for the fine photolithography patterns required for the manufacture of integrated circuits.

The growth of silicon in an amorphous or amorphous polycrystalline state is known;
Such a thin film has a thickness of about 850 to 1. It is also known that OOO'C is normalized to convert it into a polycrystalline state. However, generally, polycrystalline silicon layers formed in the manufacture of semiconductor devices are formed in a polycrystalline state. This is because a silicon layer is formed in a much shorter time in an amorphous state than in a polycrystalline state, and some experts believe that a layer formed in an amorphous state is relatively unstable. It's for a reason. Furthermore, while the traditional requirement for such devices has been to be able to tolerate layers formed in a polycrystalline state, silicon layers formed in a polycrystalline state will require thickness and smoothness for future complex multilayer semiconductor devices. It cannot meet the conditions of degree.

In accordance with the present invention, it has been found that complex multilayer semiconductor devices can be significantly improved by forming the silicon layer in an amorphous state and normalizing it to a polycrystalline state.

[Summary of the invention]

Complex multilayer semiconductors and other electronic devices containing one or more layers of polycrystalline silicon can be grown by growing the layer in an amorphous state and normalizing it to convert it to a polycrystalline state. Improved by giving the layer special surface smoothness, crystal perfectness and microscopic homogeneity. It is surprising that this particular smoothness is preserved in the polycrystalline layer.

[Detailed explanation]

The present invention relates to semiconductor devices and other electronic devices having one or more layers of polycrystalline silicon, such devices or structures typically containing or forming part of electronic circuitry. Examples of such devices include MOS
There are gates, interconnects, load resistors, double crystal silicon capacitors and various devices found in high density integrated circuit technology. The term "device" as used herein includes structures or composites of semiconductor devices. In general, the invention is applicable to any electronic device that requires one or more polycrystalline silicon layers, such as the one shown in FIG. Although this invention improves the single layer of polycrystalline silicon on the surface of the device, it is originally expected that its effects will be realized in the internal layers of the multilayer structure.

FIG. 1 shows, for example, an interconnection arrangement between two transistors (not shown). This connection device has two gates 21 which are part of a polycrystalline silicon layer, with a gate oxide 22 and a field oxide 23? i2
It is silicon oxide. A second layer of polycrystalline silicon 24 serves as a connection between both transistors. This structure is coated with a suitable dielectric material 25.

In accordance with the present invention, a polycrystalline silicon layer is formed in an amorphous state on any conventional substrate such as sapphire, glass, silicon dioxide, etc. in electronic devices; the preferred method of depositing this silicon layer is low pressure chemical This is a vapor deposition method. For purposes of this invention, the term "amorphous" refers to a silicon layer grown by low pressure chemical vapor deposition at a temperature of about 560 DEG to 580 DEG C. This layer is calculated using the Raman method.11
When examined, it is completely amorphous, but when examined with X-rays, it is 580.
At °C, all of the particles are not amorphous but slightly crystalline, and when examined with a transmission electron microscope, they are completely amorphous with an average particle size of approximately 6.
The crystal grains of 0 to 120 people are mixed. The exact properties of this silicon layer may vary slightly even at a constant temperature depending on factors such as the position of the substrate within the reactor, the geometrical dimensions of the reactor itself, and the exact location and tolerances of the thermocouples. On the other hand, even with low-pressure chemical vapor deposition under similar conditions, the temperature is 600~
The layer deposited at 620'C was found by conventional methods to be completely crystalline with an average grain size of over 300 Å.''
1. Normalizing such a layer produces polycrystalline silicon in a highly disordered state, with some parts having good crystallinity and some parts having bad crystallinity. The area with poor crystallinity is 25% of the weight of the layer.
% and may have an extremely strained JjCf structure that can cause defects in the device, making it extremely inconvenient to use it in devices.

This polycrystalline silicon layer is preferably deposited by conventional low pressure chemical vapor deposition techniques using conventional equipment at 560-580 DEG C. from a silicon-containing vapor such as silane. For example, a doped layer is formed in a conventional location by mixing a silicon-containing vapor with a suitable dopant such as phosphine. Although low pressure chemical vapor deposition using silane as the silicon-containing vapor is preferred by this invention, known methods and materials that yield similar results may also be used.

This layer is normalized preferably at 850 DEG to 1000 DEG C. in a nitrogen atmosphere containing 0.5 vol. of oxygen.

The presence of this trace amount of oxygen is important in the phosphorous-doped layer, as it forms an extremely thin oxide layer on the doped silicon surface to prevent phosphorous back-diffusion.

This thin layer of oxide is removed from the surface of the polycrystalline silicon before subsequent steps such as battening of the silicon layer after normalization.

The present invention significantly improves semiconductor devices because the deposition of polycrystalline silicon layers in the amorphous state significantly improves grain formation upon normalization. That is,
This layer has less distortion and higher integrity than a layer grown in a polycrystalline state, and has a particularly smooth surface, which significantly improves the interface between adjacent layers, thereby lowering the electrical breakdown potential. Furthermore, since this layer has extremely good microscopic uniformity, extremely precise photoengraving is possible. Although normalization significantly increases the internal grain size, ie, the average grain size reaches about 800 grains, it is unlikely that the above advantages are preserved in the layer after conversion to the polycrystalline state.

The surface roughness of polycrystalline silicon coatings that are normalized after deposition can be characterized using optical spectroscopy or electron microscopy. The optical method reveals a silver layer with a thickness of 700 to 1000 mm.
Physical review (PhyS, 1ieV
, ) 1.9 Cunningham et al. published in Vol. B14, p.
The difference in reflectance is measured using the method of Ier).

According to the present invention, the temperature of 70°C at 560°C by low pressure chemical vapor deposition is
The square root mean square roughness, or effective roughness σ, of silicon coatings grown from orchids is less than about 20, whereas that of 11 shells grown by the same method at 620'C is typically at least 50. . Figure 2 is 900-1000
This is a chart depicting the effective roughness values of polycrystalline silicon normalized at C as a function of deposition temperature. This chart shows that according to the low-pressure chemical vapor deposition method, the σ value is only at a deposition temperature of 580'C or lower. It can be seen that it can be about 20 Å or less, typically 15 Å or less.

Thus, for example, the Journal of the Electrochemical Society
m.

Soc, ') Contrary to the article by Kamin S' published in Vol. 127, p. 686, 1980, depositing silicon in an amorphous or amorphous crystalline state is avoided in the manufacture of semiconductor devices. Instead, growing a silicon layer in a warped, amorphous state greatly improves the smoothness, distortion-freeness, and microscopic uniformity of that layer, thereby substantially improving complex multilayer semiconductor devices. It turns out that it is possible.

Although it cannot be expected that this layer will maintain its characteristics before and after normalizing because of the increase in crystal grain size due to normalizing, the inventor of the present application has found that this layer maintains its characteristics even after normalizing. It has been observed that the average particle size of the layer formed at high temperature is 200 to 400 particles. The layer of this invention surprisingly maintains its surface smoothness both before and after normalizing.

It has also been found that conventional doping, for example with phosphorus, does not significantly increase the surface roughness of the layers of the invention. This is surprising since conventional doping has been found to promote grain growth in silicon films. The inventors have found that although the crystalline volume content of the silicon layer deposited at 580°C and with conventional phosphorus doping is slightly higher than that of the corresponding undoped layer, the surface properties are the same for both. was observed. Considering that the average grain size after growth is substantially larger than that of the undoped layer, the peak-to-peak value of the surface roughness of the layer normalized by normal phosphorus doping. It is extremely surprising that there are less than 50 pp.

The invention will now be described by way of example without any intention to limit the invention to the details of this description. On each side, all parts and heads are by weight unless otherwise specified and all temperatures are in °C.

Example 1 30 mm thick thermally grown on a (100 mm) silicon substrate in a low pressure chemical vapor deposition device in a quartz tube with an internal diameter of 127 + ff71 +
A silicon coating was deposited on top of the oxide layer. The thickness of this coating was approximately 0.5μ. The deposition temperature was measured inside the reaction tube. Silicone adhesion is 2.00 af
Pressure 350 mTorr temperature 5 in silane air flow for 7 minutes
The angles were 60°, 570°, 580°, and 6000.620°. Since it was observed that the film thickness increased towards the periphery of the film as the temperature increased, the deposition of 6'OO', 62.0'
7, but this improved the radial thickness uniformity and limited the growth rate to about 100 per minute. Next, this silicon film was placed in a nitrogen atmosphere at a temperature of 900° and 95°C.
Normalized at 0° and 10,000.

This film was analyzed both after growth and after normalization by Raman method, elastic light scattering method, absorption method, ultraviolet reflectance method, X-ray diffraction method, conductivity method, scanning electron microscopy, and transmission electron microscopy. Tested.

Using the normal Raman method, the silicon film grown at 560° to 580° is completely amorphous, but at 6000° to
It was found that the crystallinity of the crystals grown at 6200 ℃ suddenly increased. However, by X-ray diffraction and transmission electron microscopy,
The coating deposited at 560' is completely amorphous;
It was confirmed that those deposited at 80° had fine crystals mixed in the amorphous base material, and those deposited at 6000° and 620° were completely crystalline. In all cases, the normalized material was completely crystalline.Differences between each coating due to the normalizing temperature were not noticeable no matter which method was used, but the line width of the Raman method and the absorption method It was found that the films deposited at low temperatures (560-580'C) were all significantly closer to single-crystal silicon, while those deposited at higher temperatures had better or worse crystallinity in some parts. Ta. This portion of poor crystallinity amounted to about 25% of the volume of the coating. Also, transmission electron microscope and
It was found by line analysis that the grain size of L-layer films formed at low temperatures increases substantially during normalization, while those grown at high temperatures increase only very slightly. The elastic light scattering method agreed with the results of the Raman scattering method.

The surface roughness of the silicon coating before normalizing was examined by electron microscopy and optical spectroscopy using the technique described in the paper by Rinningnom et al. Excitation of the surface plasma increases reflection losses, which can be directly calibrated by the interferometrically obtained σ values. 560',
For a coating deposited at 620°, the λ-3500 reflectance R from a 1000 thick silver layer is 0.83, respectively.
6 and 0.444. This clearly demonstrates the decrease in reflectance of the film grown in the polycrystalline state at 620°.

Using the calibration of Canning et al., these measurements correlate to the effective roughness σ <15 for the 560° coating and σ −51 for the 620° coating.

Transmission electron microscopy was performed on films grown at 5700° and 620°, with a platinum layer of 10 to 20 thick deposited from the 45° direction. When the peak-to-peak value σpp of the surface roughness was calculated, it was less than 50 for the 570° coating and approximately 200 to 300 for the 620' coating.

Since σpp is several times the effective roughness σ, the correlation between these values and the roughness value calculated by optical measurement is good.

When the surface of the material was observed using a scanning electron microscope to determine whether the surface coating affected the readings, the same horizontal dimensions as with the transmission electron microscope were obtained. Observations using both transmission and scanning electron microscopes revealed that, surprisingly, no increase in surface roughness due to normalization occurred in any of the coatings.

The conductivity of the coating was determined at a test voltage of 50 mV. Measurements were taken from two separate coatings at each temperature, one after growth and one after normalization. 560°, 5700 and 580
The conductivity of the film grown and normalized at 0 is ', J
10' -1,9X 10-"'(Ωam')
'Met. Samples from one group of coatings deposited and normalized at 6000° and 620° had a narrower range of conductivity than coatings grown at lower temperatures, while the range of conductivity for the other group was narrower than that of coatings grown at lower temperatures. It was extremely thick. Therefore, it appears to be extremely difficult to form a film with good reproducibility of material properties at deposition temperatures of 600' and 6200. This result was supported by the other tests mentioned above.

example · Coatings were applied as in Example 1 at the same five temperatures.

The coating was conventionally doped with phosphorus by adding phosphine to the silane deposition gas using ]% phosphine diluted with nitrogen at a PH3/5IH4 flow rate ratio of 8XIO.

To compensate for no effect on phosphine growth rate and radial uniformity, the deposition pressure was increased to 500 m TOr and the SIH4 flow rate was increased to 300 cm'/min. This film was conditioned and the characteristics were measured in the same manner as in Example 1.

Using the conventional Raman method, it was found that the doped coating had a slightly higher crystalline volume-content and a lower amorphous-to-crystalline transition region compared to the undoped coating of Example 1. . 58
The doped coatings deposited at 0° were a mixture of amorphous and crystalline, while those deposited at 600° were entirely crystalline. The same result was obtained by X-ray diffraction and transmission electron microscopy. There were approximately 2,000 to 1,000 people. Also, in contrast to the undoped coating of Example 1, the grain size of all coatings increased significantly upon normalization, regardless of the deposition temperature.

The normalized coating was subjected to Raman scattering tests for strain and lattice deformation, which are important conditions in the application of the device. In the case of deposition, it was found that the poor crystallinity observed in Example 1 was slightly improved by doping.

The results of this Raman scattering test were also confirmed by the elastic light scattering test after growth and after normalization. )・-The best structure of the coated coating can be obtained at a deposition temperature of 5700°C or less, but even at temperatures of 580' to 620°, a film of slightly inferior quality but suitable enough for some uses may be obtained; It has been found that when the angle exceeds 620°, the coating quality becomes unacceptable.

For surface roughness measurement, for example at a deposition temperature of 580' or less]
It was found that the σ value was only about 15, similar to that of the undoped film. However, unlike the coating of Example 1, the 6200
The surface roughness of the normally grown doped coating was less than 30λ, which was acceptable depending on the application.

This was in good agreement with the results of transmission electron microscopy.

What is particularly surprising is that the doped coating, which was thought to have significantly larger grain sizes than the undoped coating, had a σp of less than 50.
The p value was observed.

The conductivity of the coating was measured in the same manner as in Example 1. The transition deposition temperature is 5800, and films grown below this temperature are amorphous and have low conductivity, i.e., 1 x 1 O-2 (Ω-cm)', whereas films grown above y'i 800 are crystalline. 1×1
It has a high conductivity of 0.3 (Ω-cm)'. All normalized coatings have this high conductivity, and this value is 0.5
This corresponds to the average sheet resistance of the μ coating of 20Ω/mouth.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an interconnect device including a plurality of polycrystalline silicon layers, and FIG. 2 is a diagram illustrating the change in effective surface roughness versus deposition temperature of the polycrystalline silicon layer after normalization. 21.24... Polycrystalline silicon layer, 22.23...
Silicon dioxide layer, 25...dielectric coating. Patent Applicant: R-Sini Corporation Agent: Tetsu Shimizu and 2 others Kumayer, Switzerland, Zwe Bar 8908 Hedeingen Viratusstrasse

Claims (3)

[Claims] (1) comprising one or more polycrystalline silicon layers;
A semiconductor device characterized in that the root mean square roughness of the layer does not exceed about 20. (2) The semiconductor device according to claim 1, wherein the polycrystalline silicon layer is formed in an amorphous state and is converted into a polycrystalline state by normalizing. (3) depositing a layer of silicon on the substrate, normalizing the layer, and forming one or more additional layers of a suitable material thereon; A method of manufacturing a semiconductor device, characterized in that the layer of silicon is deposited in an amorphous state and is converted to a polycrystalline state by normalizing and has a root mean square roughness of not more than about 20.