JPS5898968A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5898968A JPS5898968A JP56197843A JP19784381A JPS5898968A JP S5898968 A JPS5898968 A JP S5898968A JP 56197843 A JP56197843 A JP 56197843A JP 19784381 A JP19784381 A JP 19784381A JP S5898968 A JPS5898968 A JP S5898968A
- Authority
- JP
- Japan
- Prior art keywords
- film
- melting point
- layer
- molybdenum
- point metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 238000002844 melting Methods 0.000 claims abstract description 20
- 230000008018 melting Effects 0.000 claims abstract description 16
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 13
- 239000011733 molybdenum Substances 0.000 abstract description 13
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 abstract description 12
- 238000010438 heat treatment Methods 0.000 abstract description 12
- 239000000758 substrate Substances 0.000 abstract description 9
- -1 Arsenic ions Chemical class 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021344 molybdenum silicide Inorganic materials 0.000 abstract description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract 2
- 239000010936 titanium Substances 0.000 abstract 2
- 229910052719 titanium Inorganic materials 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 150000002739 metals Chemical class 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 235000006732 Torreya nucifera Nutrition 0.000 description 1
- 244000111306 Torreya nucifera Species 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000002751 molybdenum Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置に係シ、特に金属とシリコンとの間
にオーミック接触を有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device having ohmic contact between metal and silicon.
最近、不純物添加多結晶シリコンのかわりに、モリブデ
ン等の高融点金属を、ゲート電極等の配線として用いる
ことによシ、抵抗會下げかつ安定な半導体装置を得よう
とする考えが注目されている。このモリブデン（ＭＯ）
の高融点金属は、比抵抗が約１０μΩ・ｃｍ となっ
ておシ、不純物添加多結晶シリコンの１ｍΩ・ｃｍに比
して、約２桁も小さく、この友め配線抵抗は十分に無視
できる程小さくなる。また結晶粒径も小さく、微細加工
径に優れておシ、高密度集積回路等の配線材料として、
多結晶シリコンにとって代るべき優れ友素材であると考
えられる。Recently, attention has been focused on the idea of using high-melting point metals such as molybdenum for interconnections such as gate electrodes instead of impurity-doped polycrystalline silicon in order to obtain stable semiconductor devices with lower resistance. . This molybdenum (MO)
The high melting point metal has a specific resistance of approximately 10 μΩ・cm, which is about two orders of magnitude smaller than that of impurity-doped polycrystalline silicon, which has a resistivity of 1 mΩ・cm, and this interconnect resistance is sufficiently negligible. becomes smaller. In addition, the crystal grain size is small and it has excellent fine processing diameter, making it suitable as a wiring material for high-density integrated circuits, etc.
It is considered to be an excellent companion material to replace polycrystalline silicon.
従来の高融点金属たとえばモリブデン全ゲート電極とし
て用い九ＭＯ８型スタテイ、り・メモリ等の°半導体装
置に於ては、メモリ・セル領域を微小にする九めに、ゲ
ート電極の一部が、ＭＯ８）ランジスタのソースまたは
ドレイン等のシリコン（以下３ｉと記す）上の拡散層（
領域）と直接オーミック接触をするいわゆるダイレクト
コンタクトと称する領域が存在する。第１図（ａｌに示
すような回路中のＭＯ８）ランジスタ１０がその例であ
る。このＭＯ８）ランジスタ１０の断面図は第１図（６
）のようになっており、高融点金属をゲート電機として
用いた場合、通常はソースとなる領域１を形成後、ゲー
ト電極２を形成して、その後イオン注入法によシ、ドレ
インとなる領域３に不純物注入【行う。その後、ドレイ
ン領域の活性化を行うために、１０００℃程度の高温熱
処理工程が必要である。この際、ソースとなる領域１と
ゲート電極２との接触が高温熱処理に対して安定で良好
なオーンツク接触が保存される必要がある。Conventional high-melting point metals, such as molybdenum, are used as the entire gate electrode in semiconductor devices such as MO8-type static and memory devices. ) Diffusion layer (hereinafter referred to as 3i) on silicon (hereinafter referred to as 3i) such as the source or drain of a transistor
There is a so-called direct contact region that makes direct ohmic contact with the contact region. An example is the transistor 10 in FIG. 1 (MO8 in a circuit as shown in al). A cross-sectional view of this MO8) transistor 10 is shown in FIG.
), and when a high melting point metal is used as the gate electrode, usually after forming the region 1 which will become the source, the gate electrode 2 is formed, and then the region which will become the drain is formed by ion implantation. 3. Impurity implantation. After that, a high temperature heat treatment step of about 1000° C. is required to activate the drain region. At this time, it is necessary that the contact between the region 1 serving as the source and the gate electrode 2 be stable against high-temperature heat treatment, and good open-circuit contact must be maintained.
同第１１Ｅ（ｂ）において、ソース領域はゲート電極て
いる。また、ゲート電極２下は、絶縁層２６を介して、
チャンネル領域となるシリコン基板２５となりている。In the same No. 11E(b), the source region is the gate electrode. Further, below the gate electrode 2, via the insulating layer 26,
This is a silicon substrate 25 that becomes a channel region.
ところで、一般に高融点金属は、Ｓｉと６００”０程度
の比較的低温の熱処理により、いわゆるシリサイド反応
と呼ばれるＳトとの化合物形成反応を生じ、高融点金属
シリサイドが形成される。ま九、１０００℃程度の高温
では、この反応は極めて激しく、配線として３０００Ａ
程度の膜厚の高融点金属管用いている場合、約２倍の６
０００λのシリサイドが形成され著しい体積変化の之め
に、コンタクト孔部分と、絶縁膜部分とで断切れが生じ
九シ、ま九大きな応力の九めに、電極が剥れたシ、シリ
コン基板に無数の欠陥を作ったシする。その結果、接触
抵抗が極めて大きくなりｆｔシ、回路がオープンになっ
たルするため、このようなダイレクトコンタクトをもつ
半導体装置に高融点金属を配線材料として用する上での
大きな障害となっている。By the way, in general, when high melting point metals are heat treated with Si at a relatively low temperature of about 600"0, a compound formation reaction with S, called a silicide reaction, occurs, and high melting point metal silicide is formed. 9, 1000 At temperatures as high as ℃, this reaction is extremely violent, and the wiring requires 3000A.
When using a high melting point metal tube with a film thickness of
000λ silicide was formed and the volume changed significantly, causing a disconnection between the contact hole and the insulating film, and due to the large stress, the electrode peeled off and the silicon substrate It created countless defects. As a result, the contact resistance becomes extremely large, resulting in an open circuit, which is a major obstacle to using high-melting point metals as wiring materials in semiconductor devices with such direct contacts. .
本発明の目的は、特に１０００″Ｏ根度の高温熱処理後
も安定で良好なＳＩとのオーミ、り接触を与える電極構
造を有する半導体装置を提供するものである。An object of the present invention is to provide a semiconductor device having an electrode structure that provides stable and good ohmic contact with an SI even after high-temperature heat treatment, particularly at a temperature of 1000''O.
本発明によれば、Ｓｉと接触する部分に特に５００λ程
２度の厚さのシリサイド層を形成し、その上に高融点金
属炭化物層を形成した２層電極構造、又は必要に応じそ
の構造上にさらに高融点金属層を形成した多層電極構造
を有する半導体装置が得られる。According to the present invention, a two-layer electrode structure is formed in which a silicide layer with a thickness of about 500 λ is formed on the part in contact with Si, and a high melting point metal carbide layer is formed on the silicide layer, or if necessary, the structure is A semiconductor device having a multilayer electrode structure in which a high melting point metal layer is further formed is obtained.
本発明は、次のような２つの知見に基づいて、従来の問
題を解決して込る。その１つは、高融点金属の炭化物が
１０００℃程度の高温熱処理によっても８ｉと反応せず
、極めて安定な物質であシ、シリサイド反応のバリヤと
なるということである。The present invention solves the conventional problems based on the following two findings. One of these is that the carbide of the high-melting point metal does not react with 8i even when subjected to high-temperature heat treatment at about 1000° C., and is an extremely stable substance that acts as a barrier to the silicide reaction.
また他の１つは、オーンツク接触部分の抵抗を小さくす
るためには、シリサイド層がＳｉと高融点金属炭化物層
の間にある方が望ましいが、このシリサイド層が厚す場
合には、高温熱処理後のストレスのために基板に欠隔を
つくったシ、あるいは剥れが生じたりするために１００
ｋから１０００λ程度の厚さが特に望ましいということ
である。Another reason is that in order to reduce the resistance of the on-sk contact area, it is desirable to have a silicide layer between the Si and the high melting point metal carbide layer, but if this silicide layer is thick, high-temperature heat treatment is required. 100% because the substrate may have gaps or peeling due to later stress.
A thickness of about 1000λ from k is particularly desirable.
以下図面によシ本発明の詳細な説明する。The present invention will be explained in detail below with reference to the drawings.
第２図（ａ）〜（Ｃ）は本発明の実施例の製造工程を示
す断面図である。まず、第２図（ａｌにおいて、Ｐ型の
Ｓｉ基板１１上に３００１の熱酸化膜１２を形成し、次
に拡散層領域となるべき部分ｔ一部分的に開孔し、その
上に４００ｋ程度の熱酸化膜１３を形成する。その後こ
の４００λ酸化膜１３を通してイオン注入法でヒ素イオ
ン（Ａｓ”）ｔ１００ｋｅマ。FIGS. 2(a) to 2(C) are cross-sectional views showing the manufacturing process of an embodiment of the present invention. First, a thermal oxide film 12 of 3001 is formed on a P-type Si substrate 11 in FIG. A thermal oxide film 13 is formed. Then, arsenic ions (As") are injected into the 400λ oxide film 13 by ion implantation.
５Ｘ１０ ｃｍ で、８１基板１１中に注入し、１
０００℃２０分の窒素中での熱処理により、イオンを活
性化し、ｎ＋拡散層１４に形成する。5X10 cm, implanted into 81 substrate 11, 1
By heat treatment in nitrogen at 000° C. for 20 minutes, the ions are activated and formed into the n+ diffusion layer 14.
その後、第２図（ｂ）［示すように、コンタクト孔１５
を開孔し、スパッタ法にょシ、第１のそリプｆｙｌ［ｔ
６ｔ−約３００λ形成し、その後アルゴンとメタンの混
合ガス中での反応性スバ、り法にょシ、炭化チタン（Ｔ
ｉＣ）膜１７ｔ−約１ｏｏｏλ形成し、さらにモリブデ
ン膜１８ｔ−１５００λ形成スル。After that, as shown in FIG. 2(b), the contact hole 15
A hole is opened, sputtering is performed, and the first rib fyl[t
Titanium carbide (T
iC) A film 17t-about 100λ was formed, and a molybdenum film 18t-1500λ was formed.
この第３層目のモリブデンｊｌ１８は、配線抵Ｋｔ−下
げるために形成したもので、ここにＴｉＣＪｌ［１−２
５００Ａ程度形成してもよい、このようにして形成され
たｎ＋拡散ｒ＃１１４上の電極は、Ｍｏ （１５００λ
）／ＴｉＣ（１０００λ）／ＭＯ（３００λ）とす＊”
ＣイルＪｉ！１層１（７）３００Ａ厚のＮ はその後の
トランジス′り製造過程によシ１０００”Ｏ程度の高温
熱処理を受は最終的［ｔｉＭＯ（１５００λ）／ＴｉＣ
（１０００λ）／Ｍｏ５ｉｚ（６００λ）となる、これ
が第２図（Ｃ）であり、ｎ 拡散層１４と接触する部分
はモリブデン、シリサイド（Ｍｏ８ｉｚ）膜１９となる
。第３図は第２図（ｂ）のような断面を持つ素子を窒素
雰囲気中で２゜分の熱処理を施した場合の固有接触抵抗
の熱処理温度依存性を示す特性図である。特性曲線２１
が本発明の本実施例に基づいた場合であシ、特性曲線２
２はモリブデンのみの電極の場合でちる。モリブデンの
みの電極の場合は、７００℃以上の熱処理では接触抵抗
が極めて大きく増加しているのに対し、本実施例の場合
は僅かしか接触抵抗の増加はみられず、すぐれたオーさ
ツク特性を示すことがわかる。This third layer of molybdenum jl18 was formed to lower the wiring resistance Kt-, and here TiCJl[1-2
The electrode on the n+ diffusion r#114 formed in this way, which may be formed at about 500A, is Mo (1500λ
)/TiC(1000λ)/MO(300λ)*”
Cil Ji! One layer 1 (7) of 300A thick N is subjected to a high temperature heat treatment of about 1000"O during the subsequent transistor manufacturing process.
(1000λ)/Mo5iz(600λ), as shown in FIG. FIG. 3 is a characteristic diagram showing the dependence of the specific contact resistance on the heat treatment temperature when a device having a cross section as shown in FIG. 2(b) is heat treated for 2° in a nitrogen atmosphere. Characteristic curve 21
is based on this embodiment of the invention, characteristic curve 2
2 is for the case of an electrode made only of molybdenum. In the case of an electrode made only of molybdenum, the contact resistance increases significantly when heat treated at 700°C or higher, whereas in the case of this example, only a slight increase in contact resistance was observed, and the electrode had excellent anti-oxidation properties. It can be seen that this shows that
Ｖ上のように、本発明によれば、特に１０００℃８度の
高温熱処理後も極めて特性の安定した良好なＳｉと金属
との間のオーｉｙり接触を有する半導体装置を作ること
ができる。As described above, according to the present invention, it is possible to produce a semiconductor device having excellent contact between Si and metal with extremely stable characteristics even after high-temperature heat treatment at 1000°C and 8°C.
本発明の実施例では、ｎ＋拡散層上のＭｏＳｉｘ層は、
熱処理によシ形成したが、これはあらかじめスバ、り法
等で直接Ｍｏ５ｉＺを形成してもよい。In an embodiment of the invention, the MoSix layer on the n+ diffusion layer is
Although Mo5iZ was formed by heat treatment, Mo5iZ may be directly formed in advance by a sputtering method or the like.
また、本発明の実施例においては、高融点金属シリサイ
ドとしてＭｏ５ｉｉｉ、高融点金属炭化物としてＴｉＣ
２、高融点金属としてＭＯｌ−用い九が、本発明はこれ
に限定されるものではなく、シリサイドや炭化物全形成
する高融点金属又は高融点金属層の高融点金属がタング
ステン（５）、タンタル（Ｔａ）等の高融点金属である
場合にも有効である。In the embodiments of the present invention, Mo5iii is used as the high melting point metal silicide, and TiC is used as the high melting point metal carbide.
2. MOI is used as the high melting point metal, but the present invention is not limited thereto. It is also effective when using high melting point metals such as Ta).
第１図（ａ）はダイレクトコンタクトラ有するメモリ・
セル中の回路図、第１図（ｂ）ｆｌ第１図（ａ）のダイ
レクトコンタクトラ有するＮＯ８）ランジスタの断面図
、第２図（ａ）乃至第２図（Ｃ）は本発明の実施例のオ
ーミック接触ｔ−説明するための断面図、第３図は第２
図の構成の素子から求めた固有接触抵抗の熱処理温度依
存性を示す特性図である。
尚図中、
１・・・・・・ソースとなる領域、２・・・・・・ゲー
ト電極、３・・・・・・ドレインとなる領域、１０・・
・・・・ＮＯ８）ランジスタ、１１・・・・・・Ｐ型Ｓ
ｉ基板、１２．１３・・・・・・熱酸化膜“、１４・・
・・・・ｎ＋拡散層、１６．１８・・・・・・モリブデ
ン膜％１７・・・・・・炭化チタン膜、１９・・・・・
・モリブデン・シリサイド膜、２１・・・・・・炭化チ
タン等を設けた場合の特性曲線、２２・・・・・・電極
をモリブデンのみで形成した場合の特性曲線、２３・・
・・・・絶縁膜、２４・・・・・・電極、２６・・・・
・・絶縁層、２５・・・・・シリコン基板。
第 ｌ 図（α）
２４
！！−２図（（１）
竿２図＜ｂ）
８
″ 茅２図（Ｃ）Figure 1(a) shows a memory with a direct contact layer.
A circuit diagram in a cell, FIG. 1(b), a cross-sectional view of a NO8) transistor with a direct contact layer in FIG. 1(a), and FIGS. 2(a) to 2(C) are examples of the present invention. Ohmic contact t-A cross-sectional view for explaining the
FIG. 3 is a characteristic diagram showing the heat treatment temperature dependence of the specific contact resistance obtained from the element having the configuration shown in the figure. In the figure, 1...A region that becomes a source, 2...A region that becomes a gate electrode, 3...A region that becomes a drain, 10...
...NO8) transistor, 11...P type S
i-substrate, 12.13... thermal oxide film", 14...
......n+ diffusion layer, 16.18...Molybdenum film %17...Titanium carbide film, 19...
・Molybdenum silicide film, 21...Characteristic curve when titanium carbide etc. is provided, 22...Characteristic curve when the electrode is formed only of molybdenum, 23...
... Insulating film, 24 ... Electrode, 26 ...
...Insulating layer, 25...Silicon substrate. Figure l (α) 24! ! -2 figure ((1) Rod 2 figure <b) 8 ″ Kaya 2 figure (C)
Claims (1)
装置に於て、前記シリコンとオーギ、り接触をすべ１！
部分に高融点金属シリサイド層を有し、さらにその高融
点金属シリサイド層上に高融点金属炭化物層を有するこ
とを特徴とする半導体装置。In a semiconductor device that has ohmic contact between metal and silicon, there is no need to make ohmic contact with the silicon!
1. A semiconductor device comprising a high melting point metal silicide layer in a portion thereof and further comprising a high melting point metal carbide layer on the high melting point metal silicide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56197843A JPS5898968A (en) | 1981-12-09 | 1981-12-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56197843A JPS5898968A (en) | 1981-12-09 | 1981-12-09 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5898968A true JPS5898968A (en) | 1983-06-13 |
| JPH0363225B2 JPH0363225B2 (en) | 1991-09-30 |
Family
ID=16381257
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56197843A Granted JPS5898968A (en) | 1981-12-09 | 1981-12-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5898968A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5125007A (en) * | 1988-11-25 | 1992-06-23 | Mitsubishi Denki Kabushiki Kaisha | Thin-film soi-mosfet with a body region |
| US5414301A (en) * | 1985-03-15 | 1995-05-09 | National Semiconductor Corporation | High temperature interconnect system for an integrated circuit |
| US5436505A (en) * | 1993-02-09 | 1995-07-25 | Kabushiki Kaisha Kobe Seiko Sho | Heat-resisting ohmic contact on semiconductor diamond layer |
-
1981
- 1981-12-09 JP JP56197843A patent/JPS5898968A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5414301A (en) * | 1985-03-15 | 1995-05-09 | National Semiconductor Corporation | High temperature interconnect system for an integrated circuit |
| US5125007A (en) * | 1988-11-25 | 1992-06-23 | Mitsubishi Denki Kabushiki Kaisha | Thin-film soi-mosfet with a body region |
| US5436505A (en) * | 1993-02-09 | 1995-07-25 | Kabushiki Kaisha Kobe Seiko Sho | Heat-resisting ohmic contact on semiconductor diamond layer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0363225B2 (en) | 1991-09-30 |
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