JPS5895465A - Inclination processing circuit for data in memory - Google Patents

Abstract

PURPOSE:To prevent exclusive occupation of an operation controlling part in the inclination processing, by updating the line address for every several bits when picture data, which is read out from a picture memory while updating the line address for every several bits, is written in the picture memory. CONSTITUTION:Picture data outputted from a photoelectric converting part is stored in a picture memory 2. An operation controlling part 1 calculates the inclination of an original on a basis of this data. When an inputted original 9 is inclined slightly from a reference line 10, a line address LA is updated in 20-byte units in accordance with the inclination to read out data. The operation controlling part determines the right shift or the left shift of one-line data of the picture memory 2 on a basis of the calculated inclination and calculates the number of bits to be shifted for the purpose of preventing the distortion. A line address output circuit 3 updates the line address each time a required number of bits of data in the picture memory 2 is read out.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention In this invention, originals, forms, etc. are skinned and input into an image data processing device such as a facsimile machine or an OC le, and the skinny 11-m image data is stored in an image memory. When the image data is stored, it can be applied to a rounding circuit that corrects the image data to a form close to the original image. This invention relates to a tilt processing circuit for data in memory, which can be applied to cases where the data is tilted and edited according to the round shape.

In recent years, K[n,
For example, facsimile machines and OCR have come to be combined. A facsimile machine is a device that transmits a document as an electrical signal, and an OCR is a device that recognizes characters on a form. Therefore, by combining these, the image data sent by the facsimile machine is converted into 0CRK
f! One possible application is to perform cognitive processing. However,
As is well known, OCR is a device that detects character lines and cuts out one character based on this for recognition, so if a form is input in a skewed manner, recognition accuracy will decrease.
In extreme cases, it becomes completely unrecognizable.

In addition, some 7mm 7mm devices have been introduced that have an editing function, but as part of this editing process, the data in the image memory (which can be used by tilting the image 1# appropriately) has been introduced. This is advantageous because it allows for diversity in one editing process.

Technical Background of the Invention Therefore, conventionally, image data stored in an image memory is loaded into a register in an arithmetic control unit in predetermined bit units (for example, byte or word units), bit-shifted, and then the image data is stored in the image memory again. By repeating the process of storing in memory nine times, the above process! ! However, according to such a method, since the processing is performed by the arithmetic control unit, it takes a lot of processing time.

Furthermore, while this process is being performed, the arithmetic control unit cannot perform other processes.

Purpose of the Invention The present invention has been made in view of the above-mentioned drawbacks of the conventional art, and its purpose is to shorten the processing time performed by the arithmetic control s,
Accordingly, it is an object of the present invention to provide a slope processing circuit for data in a memory that can increase the time that an arithmetic control section can contribute to another process 1111. Part 1 and
In addition to the image memory 2, there is also a line address output circuit 3 that continuously updates and outputs the line address of the image memory 2 for each required number of bits based on the slope determined in advance by the arithmetic control unit l, and an image memory. By providing a line data shift circuit 4 that reads image data from 2, shifts this data by the required number of bits based on the nine slopes determined by the arithmetic control unit 1, and writes it again to the image memory 2, the above-mentioned purpose can be achieved. achieved.

That is, in skinny correction and editing processing as described above, it is necessary to tilt the image in the image memory without causing distortion. In order to achieve this, the first
To do this, read the data of one column (l line) in the image memory, shift it by the number of bits necessary to avoid distortion of the image, and then shift it by several bits (by taking the slope into consideration).
The second method is to update the line address every few bits (or bytes) when reading data from the image memory depending on the slope. A conceivable method is to update the data, read out the data, perform a shift to prevent distortion from occurring in the data, and then store the data in the image memory again using the same 1-line address.

The line address output circuit of the present invention plays the role of updating and outputting the line address in the above two methods, and the line data shift circuit does not cause distortion to the image data in the above two methods. It plays the role of making a shift for the sake of the future.

In the example described below, the case using the second method is a
As will be explained, it goes without saying that the tenth method can also be adopted in Oka's circuit. It is also possible to combine the methods of #11 and #2. That is, even when writing the image data obtained by updating the line address from the image memory every few bits (or several bytes) to the image memory, the line address is updated every few bits (or several bytes). It is. In this way, for example, it is possible to make the right-inclined nine data baro-inclined.

Embodiments of the Invention Hereinafter, embodiments of the present invention will be described with reference to the drawings in the case of the second method described above. Further, in the following example, a case will be described in which the circuit is used as a skinny correction circuit.

As shown in FIG. 1, an arithmetic control section 1, an image memory 2
, line address output circuit 3, and line data shift circuit 4 are connected by an address node 5 and a data bus 6. The address bus 5 is, for example, 24 bits, of which the upper 16 bits are used as a line address, the remaining lower 8 bits are used as a byte address, and the data bus 6 is, for example, 8 bits. .

The arithmetic control unit 1 has a processor function, and uses read/write commands (not shown) to read, for example, images output from or transmitted from a photoelectric conversion unit in an image data processing device to which it belongs. Store the data in image memory 2. Then, based on the stored image data, the arithmetic control section 1 calculates the inclination of the document or document. That is, the arithmetic control unit 1 determines how much the image data is to be tilted based on this. For example, as shown in Figure 2, the original 7
Assuming that marks for calculating the inclination are printed on both upper ends 8A and 8B of , the arithmetic control unit 1 calculates the inclination from the addresses in the image memory 2 where the two markmas are stored.

Based on the calculated slope, the arithmetic control unit 1 calculates how many bits the line address should be updated for the data in the image memory 2. For example, when the input document 9 is tilted slightly from the reference line 10 by ii degrees as shown in Figure 3, the line address LA is set in units of 20 bytes according to the tilt as shown in Figure IIa and B. It is decided to update and read the data. In addition, when the document 9 is extremely tilted with respect to the reference line 10 as shown in FIG. It is decided to update and read the data. Furthermore, when calculating the above-mentioned inclination, it is also calculated whether the document 9 is tilted upward to the right as shown in Figure 3 or upward to the left as shown in Figure 4. Then, in the case of the upper right corner, it is decided that the line address is to be updated continuously up, for example, and in the case of the upper left corner, it is decided that the line address is to be updated down, for example, continuously.

Furthermore, the calculation control s1 is based on the calculated slope.

It is determined whether to shift one line of data in the image memory 2 to the right or left, rounding is performed to avoid distortion, and how many bits to shift are calculated.

For example, when the document 9 is tilted upward to the right as in the case of the person shown in FIG. 3, the data that would be stored in the memory area having the lower line address is shifted to the left by a large amount. 9. When the original 9 is tilted at 9 with the upper left corner as shown in Figure 4, the data that would be stored in the memory area having the upper line address is shifted to the left by a large amount.

The method of continuously updating the line address and the method of shifting each 2-in data in the above description are just examples.

In other words, depending on which position is used as a reference to correct the skew, the up/down of the line address, the direction of data shift, and the number of shifts are variable. For example, if correction is to be performed based on the center of the document 9, If the tilt is like that of a person in Figure 3, the further upward you go (from the center), the more you shift to the right, and the further you go below the center, the more you shift to the left.

In any case, the arithmetic control unit 1 generates data indicating how many bytes (bits) the line address should be changed for each 12-in data read from the image memory 2, and how many bits to shift each 12-in in which direction. It is necessary to have data on whether or not to do so.

Next, the line address output circuit 3 will be explained. The line address output circuit 3 is supplied with a latch signal LATCH, a load signal LOAD11, a load signal LOAD1%, and an up/down signal UP/DOWN from the arithmetic control section 1. In addition, the line address output circuit 3 is supplied with a clock signal BY'I'ECLOCK generated for each required number of bits and a line address output signal OUT from the line data shift circuit 4.

Specifically, as shown in FIG. 5, the line address output circuit 3 includes a latch circuit 11, a byte number counter 12, a line address counter 13, a delay circuit 14, a gate 15, an O
It is composed of an R gate 16.

The latch circuit 11 stores data indicating how many bytes (hereinafter, this embodiment will be explained in units of bytes) to continuously update the line address as calculated by the arithmetic control unit 1. is input via the data bus 6. At this time, the arithmetic control unit 1 outputs the latch signal LATCH.
By activating , data is latched into the latch circuit 11 . Next, the data latched by the latch circuit 11 is loaded into the byte number counter 12 when the arithmetic control section 1 activates the load signal LOADl. This byte number counter 12 receives a clock signal B output from the line data shift circuit 4 every time one byte of image data is input to the line data shift circuit 4.
It is counted down by YTE CLOCK.

Then, when the number of bytes loaded into the byte number counter 12 is counted down and reaches zero, the byte number counter 12 outputs the line address advancement clock LADCK to the line address counter 13 and the delay circuit 14.

This line address advancement clock LADCK is delayed for a predetermined time by the delay circuit 14, and then reaches the byte number counter 12 via the OR gate 16, where it receives the load signal LOA.
It works equivalent to Dl. That is, it has the function of loading the data input to the latch circuit 11 into the byte number counter 12 again.

On the other hand, the line address counter 13 includes an arithmetic control section 1
However, before the first line address advancement clock LADCK is output from the byte number counter 12, the line address (this line address is, for example, the starting address of the area where image data is stored) is input via the data bus 6. The line address is loaded by making the load signal LOAD@ active. Further, the arithmetic control unit 1 sends an up/down signal UP to the line address counter 13.
/DOWN to instruct whether to count up or down. The line address counter 13 is counted up or down by the line address advance lock LADCK output by the byte number counter 12. During the countdown t+, the counted up line address is output from the line address counter 13 and reaches the gate 15. When the line address output value -jJ()UT indicating the timing at which the line address should be output is made active and applied to the gate 15 from the line data shift circuit 4,
The output of line address counter 13 will be sent to address bus 5.

To explain with a specific example, when the arithmetic control unit 1 decides to update the line address down every 2 bytes and read the data, and starts this process from address ◆0 of the image memory 2, , 2 (byte) is stored in the latch circuit 11, 2 (byte) is stored in the byte number counter 12, and ◆0 (address) is stored in the line address counter 13. Then, when the clock BYTECLOCK is given, the content of the byte number counter decreases to "1", "0", and "
0", a signal equivalent to the load signal LOAD I is input to the byte number counter 12 via the OR gate 16, and "2" (byte) is loaded again.

As mentioned above, when the byte number counter 12 becomes "0", the line address advancement clock LADCK is output, and the contents of the line address counter 13 change from 0 to ≠1.
will be updated to. Furthermore, the line address output value QUT is activated and output to the gate 15 at a predetermined timing, and as a result, φ1 (address) is sent onto the address bus 5.

Next, the line data shift circuit 4 will be explained. The line data shift circuit 4 receives a transfer lock signal BITCLOCK, a load signal LOADl, a
It is configured to receive a reset signal RESET, a mode signal MODE, a clear signal CLEAR, and a transfer start signal 5TART.

Specifically, the line data shift circuit 4 is a DMA (direct memory access controller) as shown in FIG.
17 and P/S (parallel-serial) f[device 1g,
8/P (serial-parallel) converter 19, line memory addition, pit address counter 21, selector 2
2.7 lip-flop (hereinafter referred to as F/F) 23.

When the line data shift circuit 4 operates, the arithmetic control section 1 first outputs the line data store head address to the pit address counter 21 via the data bus 6, and makes the load signal LOAD active.

As a result, the leading address of the 2-in data is loaded into the pit address counter 21. Next, the arithmetic control unit 1 activates the clear signal CLEAR, sets the mode signal MODE as an input mode, and inputs ljj to the DMA 17.
Data is transferred from the image memory 2. That is, the arithmetic control unit 1 sets the data start address, data length, etc. in the DMA 17, and makes the transfer start signal 5TART active.

Then, the DMA 17 activates the line address output signal OUT and inputs 1-byte data from the image memory 2 based on the address output from the line address output circuit 3. Thereafter, the DMA 17 outputs the clock signal BYTECLOCK to the byte number counter 12 of the line address output circuit 3, and outputs the input 1-byte data to the P/8 converter 18. P
The /8 converter 18 converts 1 byte of data into the arithmetic control unit 1.
Each bit is sent to the line memory in synchronization with the transfer lock BITCLOCK output from BITCLOCK. and,
When the sending of one byte is completed, the P/S converter 18
A data request signal REQ is output as active to M A 17. As a result, the DMA 17 sends the next 1-byte data to the P/8 converter 18.

On the other hand, the bit address counter 21
The bit data output from the P/8 converter 18 is sequentially stored in the line memory while incrementing the address for the line memory in synchronization with the transfer lock BITCLOCK sent from the P/8 converter 18. In this way, when data for one line (one line of image memory 2) is stored in the line memory, the calculation control unit l
When the MA 17 notifies the end of input, the operation to transfer the data in the line memory Kasai to the image memory 2 is started.

That is, as already explained, the arithmetic control unit 1 loads the transfer destination address in the image memory 2 into the line address counter 13 of the line address output circuit 3. and,
Bit address of line data shift circuit 4
To do this, the number of bits to be shifted calculated from the inclination of the original is output onto the data bus 6 and the load signal LOAD is output.
Load by activating I. Furthermore, the arithmetic control unit l sends a clear signal CLE to the DMA17.
AR is sent as active, mode signal MODE is set to output mode, and transfer start signal 5TART is set active. The pit address counter 21 transfers one bit at a time from a preset address to lock B.
Send bit data to selector n in synchronization with ITCLOCK.

Here, the selector n is controlled by the output of the F/FZ3, and for example, before the F/F23 starts data transfer,
It is assumed that the reset signal RESET outputted by the arithmetic control section 1 has been reset. Then, selector n is
Passes the output of the line memory addition. The data that has passed through the selector ρ reaches the 8/P converter 19 and is summarized into 1 byte of data. When 1 byte of data is formed, the s7p converter 19 outputs a data output request signal -150UTREQ to the DMA 17. This results in
One byte data is input from the DMA 17 Hiro 8/P converter 19, and this data is transferred to the address output by the line address output circuit 3 of the image memory 2.

After repeating such operations and outputting the final bit of the line memory counter, the pit address counter 21 outputs a line end signal END to the F/F 23. As a result, 9, F/FZ3 is set and its output reaches selector n. As a result, the selector n selects the "0" input, and the C8/P converter 19 receives "0". Then, this "0" is output by the number of bits to be shifted, and as a result, rOJ is stored in the last few bits of one line of the image memory 2.

Of course, the control of the selector ρ by the F/F 23 is not limited to the example above, but also depends on whether the document is tilted at the top right or top left, or which part of the document is centered to correct skinny. It's different. That is, in the case of left shift, set KFi and current view F/F23, input "0" to selector 4, and when the required number of bits "0" is input, the arithmetic control unit 1 sends the reset signal RE8E.
It is also possible to output T to reset the F/F 23 and pass the output from the selector n to the line memory.

In this way, the data in the image memory 2 is updated by increasing or decreasing the line address for each required number of bits, and the data for one line is read out.Furthermore, this data is transferred to the line data shift circuit. Number of bits recommended by 4 is 7
Skinny correction is performed by shifting the image.

That is, suppose that the image of the document 9 as shown in FIG. 7(a) is tilted due to the skinny and becomes an image as shown in FIG. 7(b) in the image memory 2. Since the diagonal 1 m 201 part is not in the original image, it is unclear how it will look when it enters the image memory 2. Also, the part marked by diagonal @ 202 is a part that is present in the original image, but was removed at the stage of inputting it to the image memory 2.

When an image as shown in FIG. 7(b) is input to the skinny correction circuit of this embodiment, the image as shown in FIG. 7(c) is corrected to an image close to 118 pixels. If the image in FIG. 7(b) is corrected only by the line data shift circuit 4, it will become a table image as shown in FIG. 7(d), and if it is corrected only by the line address output circuit 3, The image will look like figure (e).

In this way, in order to correct one line of data, the processing involving the arithmetic control unit 1 includes the start processing when inputting one line of data from the image memory 2 to the line memory adder;
Only the output start process is required when outputting one line of data from the line memory to the image memory 2, and the processing time can be reduced. (9) The line memory has a capacity to store 1247 worth of data and can read from any bit for shifting, so it is easy to shift the required number of bits.

In the above explanation, when reading from the image memory 2, the line address is updated and read every ta byte, and this is shifted and stored in the image memory as l line data. According to the 20-year method,
When reading data from the image memory, the line address may be updated every several bytes and the data may be stored when one line data is read out, shifted, and stored in the nine bales one image memory. Even if this is done, the power of the arithmetic control unit does not change, the capacity of the image memory is increased by an amount corresponding to the assumed maximum slope, and other hardware remains unchanged.

As described in detail, according to the present invention, the arithmetic control unit is not exclusively used for tilt processing of data in the image memory, and
The time involved by the arithmetic control section can be dramatically reduced. Therefore, the arithmetic control section can effectively use the time spent in the slope processing of the data in the memory for other processing. Furthermore, in a system having a plurality of arithmetic control units, it can be expected that the number of arithmetic control units can be reduced.

[Brief explanation of drawings]

The first WA is a block diagram of an embodiment of the main part of the present invention, FIGS. 2 to 4 are conceptual diagrams of the slope processing process according to the present invention, and FIG. 5 is a block diagram of an embodiment of a line address output circuit.
FIG. 6 is a block diagram of an embodiment of the line data shift circuit, and FIG. 7 is a conceptual diagram of rounding explaining an example of skinny correction according to the present invention. l...Arithmetic control unit 2...Image memory 3...
Line address output circuit 4...Line data shift circuit

Claims (1)

[Claims] An image memory into which certain bit data is input/output by one access;
In an image data processing device having an arithmetic control unit that determines whether to tilt i degrees, the line address of the image memory is continuously updated for each required number of bits based on the inclination determined by the arithmetic control unit. and a memory controller, and under the control of the memory controller, shifts the data read from the image memory by a required number of bits based on the slope determined by the arithmetic control section. , further comprising a line data shift circuit for transferring data to the image memory again, and using the line address output by the line address output circuit when transferring data between the image memory and the line data shift circuit. A slope processing circuit for data in memory.