JP2737932B2 - Image data reduction device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data reduction device used for an image processing device such as an optical file system and a personal computer.

2. Description of the Related Art Generally, when reducing image data to n / N (n and N are integers and n <N), this type of image data reduction device thins out N-bit data in the main scanning direction to n bits. Thus, the main scanning direction is reduced, and the N lines in the sub-scanning direction are reduced to n lines, thereby reducing the sub-scanning direction.

In this case, since the reduced image quality is deteriorated simply by thinning out, when the main scanning direction is reduced, data obtained by performing a logical sum operation on the thinned bit and the next bit represents one bit. When the sub-scanning direction is reduced, each bit of a line to be decimated and each bit of the next line are logically ORed, so that the data is representative of each bit of one line. .

Conventionally, as this type of image data reduction device, a device that performs an operation of reducing original image data or an address operation by a processor dedicated to image processing is known.
As another device, there is known an apparatus which reduces original image data by processing the image data line by line by software.

Problems to be Solved by the Invention However, in the conventional image data reduction device,
Since the image data is reduced by software, there is a problem that the image data cannot be reduced at high speed.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above-described conventional problems, and has as its object to provide an image data reduction device capable of reducing image data at high speed.

Means for Solving the Problems In order to achieve the above object, the present invention provides an OR circuit for sequentially shifting image data and outputting a logical sum signal of a bit decimated in the main scanning direction and a next bit. , A second shift register for sequentially shifting the image data from the first shift register, and n (n, N
Is an integer, corresponds to a reduction ratio setting circuit for setting reduction ratio data composed of n <N) bits “1” and (N−n) bits “0”, and corresponds to bit “0” of the reduction ratio data A clock control circuit for outputting a signal for activating the OR circuit of the first shift register and stopping a clock signal of the second shift register, and a line memory for storing at least two lines of image data. A buffer that outputs a logical sum signal of each bit of a line thinned out in the sub-scanning direction by a wired OR and a bit of the next line, and a control circuit that controls the line memory and the buffer. is there.

According to the present invention, when the clock signal is stopped, the capture of the image data into the second shift register is stopped to reduce the image data in the main scanning direction, and the image data corresponding to the bit “0” of the reduction ratio data is provided. The control circuit can reduce the number of lines and output a logical sum signal to reduce image data in the sub-scanning direction.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic block diagram showing an embodiment of an image data reduction device according to the present invention, FIG. 2 is a main part circuit diagram showing a main scanning OR circuit of FIG. 1, and FIG. Line memory shown
FIG. 4 is a main part circuit diagram showing a sub-scanning OR circuit, and FIG. 4 is an explanatory diagram of the operation of the image data reducing device of FIG.

In FIG. 1, 1 is a data bus having N bits, 2
As shown in FIG. 4 (a), image data (x x N bits) in which x words consisting of N bits are consecutive in the main scanning direction and y dots in the sub scanning direction ×
The main scanning direction of (N × y dots) is changed to xxn dots (n
<N) is a main scanning OR circuit.

Reference numeral 3 denotes an image data (x × n × 3) having a line memory and reduced in the main scanning direction by the main scanning OR circuit 2.
The image data (x × n × y × (n / N) dots as shown in FIG. 4 (b), where n / n is obtained by performing a logical sum operation (OR) on the sub-scanning direction of (y dots) as described later. N is an integer) line memory / sub-scan OR to output to data bus 4
Circuit.

In FIG. 2, reference numeral 21 denotes a buffer for temporarily storing image data (N bits) on the data bus 1; and 22, a clock I which is N times the data transfer speed of the data bus 1 for transferring the image data from the buffer 21. A shift register of (N + 1) -stage which is transferred in the following manner. Between the last stage of the shift register 22 and the preceding stage, a bit to be thinned out in the main scanning direction by an OR control signal from a clock control circuit 27 described later. AND gate and OR to output the logical sum signal of the next bit
The gate is connected.

23 takes in the image data from the shift register 22 by a clock II described later and reduces its main scanning direction,
The output shift register, 24 is a shift register
This is a buffer for temporarily storing the image data from 23.

After the reduction, one line is composed of x × n bits, and 25 is the number of words after the reduction in the main scanning direction when one word is N bits (an integer value rounded up when xxn / N is not an integer). ) Is set in advance to the main scan word number register, 26
Is a reduction ratio register in which the total bit number of one word is N and the reduction ratio data of n bits “1” is set in advance in accordance with the reduction ratio n / N. In the case of, for example, data of (1110110110110101) is set in advance.

27, when the reduction ratio data set in the reduction ratio register 26 corresponds to bit "0", outputs an active OR control signal and stops the clock II. A clock control circuit for transferring the data stored in the shift register 23 to the buffer 24 when the number of words set to 25 has been reached. In FIG. 3, reference numeral 31 denotes a thinned-out pixel in the sub-scanning direction by a wired OR. A sub-scanning OR buffer that outputs a logical sum signal of each bit of the line to be cut and each bit of the next line, 32 is for storing data of the line to be thinned in the sub-scanning direction and the data of the next line. There are at least N line memories.

33 controls the sub-scanning OR buffer 31 for the number of words set in the main-scanning word number register 25 described above, and uses the reduction ratio data from the reduction ratio register 26 to reduce the reduction set in the sub-scanning OR circuit 31. Bit "0" of ratio data
And a sub-scanning OR control / memory address generation circuit for outputting write and read address signals for the line memory 32 corresponding to the next bit.

 Next, the operation of the above embodiment will be described.

In FIG. 2, image data (N bits) read from the data bus 1 to the buffer 21 is
Is set to In this case, the next image data is sequentially read into the buffer 21 and set in the shift register 22.

The shift register 22 controls the data bus 1 by the clock I.
The image data is sequentially shifted to the next stage at N times the data transfer speed of the first stage, and the bit of the last stage and the bit of the preceding stage are logically connected by an OR circuit connected between the last stage and the preceding stage. The sum operation and the logical sum operation data are output from the final stage.

In this case, in the last stage of the shift register 22, the OR control signal from the clock control circuit 27 activates the OR.
The circuit performs a logical OR operation on the data bits decimated in the main scanning direction of the final stage and the bits of the preceding stage, and outputs the logically ORed data from the final stage.

Then, since the clock II from the clock control circuit 27 stops when it corresponds to the bit “0” of the reduction ratio data, the image data corresponding to the bit “0” of the reduction ratio data is not taken into the shift register 23, Therefore, the N-bit image data in the main scanning direction is reduced to n bits.

When the reduced image data (xxn) for one line is stored in the shift register 23, the main scanning word number register
Buffer 24 according to the number of main scan words preset to 25
, And similarly, image data (1
X × n bits per line) are stored in the buffer 24. Therefore, x × N × y bits of image data are reduced to x × n × y bits in the main scanning direction.

Next, a description will be given of an operation in the case of reducing the x × n × y bits of image data in the sub-scanning direction.

In FIG. 3, under the control of the sub-scanning OR control / memory address generating circuit 33, of the image data stored in the buffer 24, the data of the line to be thinned and the data of the next line are transmitted via the sub-scanning OR buffer 31. Line memory 32
To the sub-scanning OR buffer 31
The logical sum signal of each bit of one line is output to the data bus 4. Note that data other than the above-mentioned lines are directly output to the data bus 4.

Accordingly, the image data of x × n × y dots is reduced to n / N in the sub-scanning direction, and as shown in FIG. 4, the main scanning direction and the sub-scanning direction are each reduced to n / N.

When the image data is reduced to 11/16, a line memory 32 for 10 lines is required. The above-described reduction in the sub-scanning direction can be performed by a DMAC (Direct Memory Access Controller).

Effect of the Invention As described above, according to the present invention, since image data is reduced by a hardware configuration, image data can be reduced at high speed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram showing an embodiment of an image data reduction device according to the present invention, FIG. 2 is a main part circuit diagram showing a main scanning OR circuit of FIG. 1, FIG. 3 is a main part circuit diagram showing the line memory / sub-scanning OR circuit of FIG. 1, and FIG. 4 is an operation explanatory diagram of the image data reduction device of FIG. 1, 4 data bus, 2 main scan OR circuit, 3 line memory / sub scan OR circuit, 22, 23 shift register, 2
5: Main scanning word number register, 26: Reduction ratio register, 31: Sub scanning OR buffer, 32: Line memory, 33
... Sub-scan OR control / memory address generation circuit.

Claims (3)

(57) [Claims] A first shift register including an OR circuit for sequentially shifting image data and outputting a logical sum signal of a bit to be decimated in a main scanning direction and a next bit; A second shift register for sequentially shifting image data from the shift register, and n (n, N is an integer, n <N) bits “1” and (N−N) where the total number of bits in one word is N a reduction ratio setting circuit for setting reduction ratio data composed of n) bits “0”, and an OR circuit of the first shift register being activated when the reduction ratio data corresponds to bit “0” of the reduction ratio data A clock control circuit for outputting a signal and stopping a clock signal of the second shift register, wherein the stop of the clock signal causes the clock signal to be transmitted to the second shift register. Stop receiving the image data image data reduction device for reducing the image data in the main scanning direction. 2. A line memory for storing image data of at least two lines, and a logical OR signal of each bit of a line to be thinned in the sub-scanning direction and each bit of a next line by a wired OR. Buffer and 1
The total number of bits of a word is N and n (n, where N is an integer, n
<N) bits “1” and (N−n) bits “0”
A reduction ratio setting circuit for setting reduction ratio data consisting of
An image data reducing device having a control circuit for controlling the line memory and the buffer, wherein the control circuit thins out a line when the bit corresponds to bit “0” of the reduction ratio data, and outputs the logical sum signal. An image data reduction device that outputs and reduces image data in the sub-scanning direction. 3. A first shift register including an OR circuit for sequentially shifting image data and outputting a logical sum signal of a bit decimated in the main scanning direction and a next bit, and A second shift register for sequentially shifting image data from the shift register, and n (n, N is an integer, n <N) bits “1” and (N−N) where the total number of bits in one word is N a reduction ratio setting circuit for setting reduction ratio data composed of n) bits “0”, and an OR circuit of the first shift register being activated when the reduction ratio data corresponds to bit “0” of the reduction ratio data A signal that outputs a signal, a clock control circuit that stops the clock signal of the second shift register, a line memory that stores at least two lines of image data, and a wired OR, An image data reduction device comprising: a buffer that outputs a logical sum signal of each bit of a line to be drawn and each bit of a next line; and a control circuit that controls the line memory and the buffer. When the signal is stopped, the image data is not taken into the second shift register, the image data is reduced in the main scanning direction, and the line is thinned out by the control circuit when the data corresponds to bit “0” of the reduction ratio data. And an image data reduction device for outputting the logical sum signal to reduce image data in the sub-scanning direction.