JPS5894035A - Data processing system - Google Patents

Abstract

PURPOSE:To always perform an operation with suited internal constitution and to increase the processing speed, by varying the connection among one or plural registers, an arithmetic unit and a data bus based on a program instruction. CONSTITUTION:The signal of a signal line 10 which indicates the connection at a connection controlling part is decoded by a decoder 41 by an instruction of a program. The value of output signals 301-436 are set at 0 or 1. This output signal line controls the intersections 101-236 among the input signals lines 8- 31 and the output signal lines 8-24 of a data bus, an arithmetic unit and a register. In such constitution, the combination among the register, arithmetic unit and data bus can be varied in various ways for each desired operation.

Description

DETAILED DESCRIPTION OF THE INVENTION α) Description of the field to which the invention pertains The present invention relates to a data processing system, and particularly to a data processing system in which the internal configuration of a data processing device can be changed by instructions from a program.

■ Explanation of the conventional technology In conventional microcontrollers, the connections between the register (sub), the arithmetic unit (AIIT), and the unit bus (BU8) are fixed and are configured in such a way that they cannot be changed. Therefore, there are cases where processing speed can be improved by executing many ALUs in parallel, such as vector operations, and cases where processing speed can be improved by arranging ALUs in series and executing continuous operations. For example, when the calculation contents instructed by the program change significantly,
There was a drawback that processing power was reduced in either one of the calculations.

(3) Purpose of the Invention In order to eliminate these drawbacks, the present invention makes it possible to change the connection between one or more BEGs, ALUs, and BUSs by instructions from a program, and to change the connection between one or more BEGs, ALUs, and BUSs according to the contents of calculations instructed to be executed by the program. The purpose is to improve processing speed by always executing calculations with an adapted internal configuration, and the drawings will be described in detail below.

(4) Explanation of the structure and operation of the invention Figure 1 shows an embodiment of the invention, in which there are 4 BUSs, 2 ALUs, and 6 REGs.
This is the case when there are more than one. Codes 1 to 4 in the figure are BU
S1 to BUS4.5 to 8 are signal lines that connect OOG and paths, and 9 is a connection control unit (OOG) that interconnects the input/output signal lines of BUS, RBG, and ALU according to program instructions. , IO changes the connection between BUS, ALU, and REG according to program instructions.
Signal line for indicating K, 11.12.15゜16 is A
Input signal line to LU, 13.17 is ALU l.

2, 14.18 is ALU1, 2 output signal line, 1
9-24 are output signal lines of REGI-RgG6, 31-3
6 is an input signal line to REG1 to REG6, and 25 to 30 are REGI 5 to BEG6. BLIS, RBG are connected to the OOG by a signal line 10 which indicates the connection to the OOG according to the instructions of the program.

Each input/output signal line of the ALU is connected inside the COG.

An example of the configuration of 00G is shown in FIGS. 2 and 3. In FIG. 2, a signal (signal line 10) instructing the connection of COG according to a program command is decoded by a decoder (DIXJ), and the values of DEO output signals 301 to 436 are set to 0 or 1. This output signal line is BUS, ALU
, output signal lines 8 to 24 from RgG, BUS, ALU,
Input signal I to REG! Intersection points 101-23 with 8-31
6 connections respectively. FIG. 3 shows an example of the configuration of the intersection 101. When the value of the signal line 301 that controls the intersection 101 is 1, the AND circuit 501 and the OR circuit 502 connect the signal lines 18 and 31. Signal line 301
When the value of is O, the signal line 50 is
The value of 3 becomes 0, and the connection between the signal lines 18 and 31 is disconnected. Other intersection points 102 to 236 in FIG. 2 have the same configuration as in FIG. 3. The OOG does not need to be centrally located at one location, and can be distributed in a distributed manner within the data processing device. Because of this structure, when configuring ALUs 1 and 2 to operate in parallel using the signal line 10 according to program commands, the signal line 24 is connected inside the OOG.
and 15.23 and 16.18 and 33.21 and 11.20 and 12.36 and 14.8 and 31 and 22.7 and 32.6 and 3
The configuration shown in FIG. 4 is realized by connecting BUS 4, 19.5, and 35, respectively.

Each of the ALUs 2 can operate in parallel, and high-speed operations on mutual array data such as vector operations become possible.

Also, by the signal line 10 according to the command of the program, AL
When configuring Ul,2 to operate in series, 00G
Internally signal lines 24, 15.23, 16.18 and 33°2
2 and 11.21 and 12.14 and 35.6 and 31 and 20.
5, 32.degree., 7, and 34, the configuration shown in FIG. 5 can be realized, and it is possible to perform continuous performance of a plurality of data at high speed. In FIGS. 4 and 5, for convenience of explanation, the COG and its control signal line 10, the unconnected REG and its input/output signal line, etc. are omitted. This example is REG.

Although the number of ALUs is small, such as 6 and 2, by adopting a similar configuration using a large number of BEGs and ALIJs, R[G, input LUs are used for each operation to be executed.

The combination of BUS can be changed in various ways, and the internal configuration of the data processing device can take the optimal form for each to execute calculations, making it possible to significantly shorten the program execution time.

6) Description of Effects As explained above, according to the present invention, the internal configuration of the data processing device can be changed by program commands, so that various programs with different arithmetic execution control forms, such as programs suitable for a Neumann type computer, can be used. This has the advantage that programs suitable for non-Neumann type computers can be executed on the same data processing system without loss of efficiency. Furthermore, when a data processing device is implemented as an LSI, it is almost impossible to change the internal configuration, but by implementing the configuration of the present invention, it becomes possible to change the internal configuration even if the data processing device is implemented as an LSI. There are also advantages.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an internal configuration diagram of an embodiment of the OOG shown in FIG. 1, FIG. 3 is a configuration diagram of an embodiment of the connection circuit inside the OOG, and FIG. 4 is an explanatory diagram illustrating a state in which two arithmetic units are connected to operate in parallel based on the OOG connection conditions, and FIG. 5 is an explanatory diagram illustrating a state in which two arithmetic units are similarly connected to operate in series. In the figure, 1 to 4 are data paths (HUS), 5 to 8 are signal lines between the data path and 000, and 9 is connection control unit (OOG).
), IO is a connection control signal line, 13.17 is an arithmetic unit (ALU), and 25 to 30 are registers (RJX)). 41 represents a decoder. Patent applicant Hiroshi Mori, patent attorney representing Nippon Telegraph and Telephone Public Corporation

Claims (1)

[Scope of Claims] A plurality of storage units storing operand data including program addresses or operation results during processing, one or more arithmetic units, and a portion of the storage unit and the arithmetic unit. In a data processing system having at least one or more data transfer means capable of connecting all of A connection control section is provided in which the signal lines are collected and the connections between the input and output signal lines can be changed according to instructions from a program. A data processing system characterized in that a connection mode between the storage section, the arithmetic unit, and the data transfer means is controlled by instructions of a program.