JPH04177527A - Arithmetic processing circuit - Google Patents

Abstract

PURPOSE:To execute the data transfer at high speed by providing a transfer path for transferring data inputted to an arithmetic part in parallel to the arithmetic part, and an output selecting part which can output alternatively an output signal of the arithmetic part and a transfer signal of the transfer path in response to a control signal. CONSTITUTION:By providing a transfer path 100 for transferring data inputted to an arithmetic part which can execute an arithmetic processing of input data, in parallel to the arithmetic part, and also, an output selecting part 101 which can output alternatively an output signal of the arithmetic part and a transfer signal of the transfer path in response to a control signal, an arithmetic circuit is constituted. That is, by the transfer path 100, transfer data is transferred in parallel to the arithmetic part, and by the output selecting part 101, a transfer signal of this transfer path 100 is selected. In such a way, the data transfer can be executed without passing through the arithmetic part, and the data transfer can be executed at a high speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an arithmetic processing circuit and a technology for increasing the speed of data transfer therein, and relates to a technology that is effective when applied to, for example, a processor controlled by a microprogram. .

[Prior art]

The execution unit of a data processing device such as a processor includes an arithmetic logic unit (ALU), various registers called source registers, and destination registers, and conventionally these registers share one or more internal paths. combined. When such an execution unit performs a required operation, the data in the source register is given to the arithmetic unit via the internal bus, and the result of the operation is stored in the destination register. In such a calculation cycle, the data to be calculated is always given to the required calculation unit from the internal bus,
Furthermore, the result of the operation is returned to the required register via the internal bus.

FIG. 4 shows a conventional example of the above execution section.

Buses BUSI and BUS2 have registers (REG) 44.
. The ALU 47 performs arithmetic processing on the input data, and outputs the processing result to the bus BUS3. At this time, the attributes of the output data (negative, zero nine carry, parity, etc.) are determined, and the result is set in the flag register 48.

The bus BUS3 includes the output terminal of the ALU 47, the input terminals of the registers 44 to 46, and the tristate buffer 49.
The input terminals of the ALU 47 are coupled to each other so that the output data of the ALU 47 can be transmitted to the registers 44 to 46, and the output data of the ALU 47 can be transmitted to the external path EXTB via the tri-state buffer 49.
It is possible to send to the US.

The data held in registers 44 to 46 is transferred to external bus EXTB.
It may also be sent to the US. In the case of such data transfer, basically no arithmetic processing is required in the ALU 47, but since it is necessary to set the attribute of the data related to the transfer in the flag register 48, the ALU 47 does not add zero to the data. It will be done. For example, when the data held in the register 44 is sent to the external bus EXTBUS, when the data is transmitted to one input terminal of the ALU 47, the input data from the other terminal of the ALU 47 is set to zero, thereby Zero addition to the data is possible.

Based on the result of such zero addition, the attribute of the data is determined. The result of the zero addition is substantially equal to the output data of the register 44, and is sent to the external bus EXTBUS via the tri-state buffer 49.

An example of a document describing the processing of the execution unit in a data processing device is "Bit Slice Microprocessor" published by Maruzen Co., Ltd. on November 30, 1972.

[Problem to be solved by the invention]

According to the above conventional technology, even in the case of data transfer from the register to the external bus, it is necessary to perform zero addition processing in the ALU in order to determine the attribute of the data related to the transfer, and the data after the addition processing is will be sent to the external bus.

In other words, even in data transfer according to a transfer command, AL
It will pass through the calculation path of U. The present inventors believe that passing through the ALU calculation path in data transfer causes a data transmission delay, and this is considered to be the main factor inhibiting the speeding up of data transfer in the calculation processing circuit. It was revealed by.

An object of the present invention is to provide an arithmetic processing circuit that can speed up data transfer.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a transmission path is provided for transmitting data to be input to a calculation unit that enables calculation processing of input data in parallel with the calculation unit, and furthermore, a transmission path is provided to transmit data to be input to the calculation unit that enables calculation processing of input data, and an output signal of the calculation unit is further transmitted in response to a control signal. An arithmetic processing circuit is constructed by providing an output selection section that can selectively output the transmission signal of the transmission path. In a more specific aspect, a first tri-state buffer provided in the transmission path and a second tri-state buffer coupled to the output terminal of the arithmetic unit and operated complementary to the first tri-state buffer are provided. The output selection section can include a tri-state buffer. Further, in order to enable attribute determination of the transfer data, even when the output selection section selects the transmission signal of the transmission path, the calculation section executes arithmetic processing for determining the attribute of the transmission path transmission signal. It can be configured to

[For production]

According to the above means, the transfer data is transmitted in parallel to the arithmetic unit by the transmission path, and the transmission signal of this transmission bus is selected by the output selection unit without going through the arithmetic unit. It is assumed that data transfer is possible at the same time, and this works to enable high-speed data transfer.

〔Example〕

FIG. 2 shows a processor which is an embodiment of the arithmetic processing circuit according to the present invention. Processor 21 shown in the figure
is formed on a single semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique, although this is not particularly limited.

This processor 21 has a control form in which a macro instruction is fetched from an external program memory (not shown) connected via an input/output circuit 22, and the instruction is executed by an execution unit 23 based on microprogram control.

A microprogram describing various arithmetic processing procedures performed by the execution unit 23 is stored in a micro ROM (read-only memory) 24.

This micro ROM 24 is accessed by the output of an instruction decoder 26 that decodes the instruction code of the macro instruction fetched by the instruction fetch unit 25 and the output of the sequence controller 27, so that the micro instructions constituting the micro program are sequentially read and read. be done.

The instruction fetch unit 25 fetches a macro instruction provided from a memory (not shown) via the input/output circuit 22 and the instruction fetch bus 28. The instruction decoder 26 accesses the micro ROM 24 based on address information obtained by decoding the instruction code included in the macro instruction. As a result, the first microinstruction of a series of microinstructions for performing the arithmetic processing specified by the macroinstruction is read out. The second of a series of microinstructions for performing the arithmetic processing specified by the above macroinstructions.
The subsequent microinstructions are designated by supplying the next address field information of the microinstruction read immediately before to the sequence controller 27. The microinstructions read from the microROM 24 in this manner are supplied to the microinstruction decoder 29. This microinstruction decoder 29 decodes the applied microinstruction and generates a control signal 20 for the execution unit 23 and the like.

The execution unit 23 performs data and address calculations based on the control signal 20 output from the microinstruction decoder 29, and is coupled to the input/output circuit 22 via the internal data/address bus 21. The selection of which of the internal data/address bus 21 and the instruction fetch bus 28 to interface with the outside is controlled based on instructions from the sequence controller 27, so that the instruction fetch bus 28 is selected in the instruction fetch cycle. It has become.

FIG. 1 shows an example of a data calculation system included in the execution section 23.

Buses BUSI and BUS2 have registers (REG) 11
, 12.13 and the input terminal of ALUI5 are coupled, thereby allowing the output data of the registers 11 to 13 to be transmitted to ALUI5. ALUI 5
Then, arithmetic processing is performed on the input data. At this time, the attributes of the output data (negative, zero 2 carry, parity, etc.) are determined, and the result is set in the flag register 17.

The bus Bus3 includes input terminals of registers 11 to 13,
The input terminals of the output selection section 101 and the tri-state buffer 19 are coupled, and the output data of the ALUI5 can be sent to the bus BUS3 via the output selection section 101. The data sent to the bus BUS3 can be transmitted to the external bus EXTBUS via the registers 11 to 13 and the tri-state buffer 19.

The output selection unit 101 includes a tri-state buffer 14 provided between the buses Bus 1 and BUS 3, a tri-state buffer 16 provided between the output terminal of the ALU 15 and the bus BUS 3, and a tri-state buffer 16 provided between the output terminal of the ALU 15 and the bus BUS 3. and an inverter 18 coupled to a control terminal of tri-state buffer 16 to turn on state buffers 14 and 16 in a complementary manner. tri-state buffer 14,
16 and 19 are buses BUSI and BUS2. BUS
A plurality of bits are arranged corresponding to the configuration bits of 3.

A path from bus BUSI to bus BUS3 via the tri-state buffer 14 is a transmission bus 100,
This transmission path 100 allows data to be input to the ALU 15 to be transmitted to the bus BUS3 in parallel.

The control signal C0NI is the tri-state buffer 14.
．． 16, and the control signal C
ON2 is a signal for controlling the operation of the tri-state buffer 19. This control signal C0NI, CON
2 is the decoded output of the microinstruction decoder 29.

In the above configuration, normal data operations are performed as follows.

In response to the output of the microinstruction decoder 29, for example, registers 11.13 are selected, and their held data is transmitted to ALUI5 via bus BUSI,2. The transmitted data is used as an addend and an augend, respectively. ALU
At step 15, arithmetic addition/subtraction and logical product/sum operations are performed based on the output of the microinstruction decoder 29, and the results of the operations are output. At this time, the attribute of the data of the calculation result is determined, and the result is set in the flag register 17. The control signal C0NI is a signal related to the operation command code, and is set to a high level in the case of normal data operation.

As a result, in the case of normal data calculation, the tri-state buffer 16 is turned on, so the ALU 15
The calculation output is transmitted to the bus BUS3 via the tristate buffer 16. At this time, the tristate buffer 14 is turned off, so the addend on the bus Busl is not transmitted to the bus BUS3 via the transmission path 100. The data on the bus Busa is stored in the register designated by the output of the microinstruction decoder 29, thereby completing the operation cycle.

When the data transfer instruction is decoded by the microinstruction decoder 29, the data transfer is performed as follows.

In the case of data transfer, the transfer data held in any of the registers 11 to 13 is output to the bus BUS1. At this time, the control signal CNTl is set to a low level because no calculation is performed. Thereby the tri-state buffer 14
is turned on, and data on bus BUS1 is transmitted to bus BUS3 via transmission path 100. When external transfer is instructed, the data on this bus BUSs is transmitted to the external bus EXTBUS via the tri-state buffer 719, which is turned on by setting the control signal CON2 to a low level. At this time, the output of the inverter 18 is set to high level, so the tri-state buffer 16 is turned off, and the output of the ALU 15 is connected to the bus BUS.
3 will not be sent. In this case, the attribute determination of the transferred data is performed in the ALU 15. That is, the state of the bus BtJs2 is all set to zero, so that the ALU 15 stores the data (addend) on the bus BUSI.
Zero addition is performed on the , and attribute determination is performed based on the addition result.

FIG. 3 shows an example of an attribute discrimination circuit.

The discrimination circuit 31 shown in the figure is not particularly limited, but the zero addition result (30-1 to 3O-N) in the ALU 15
The ALU 15 is a Nant gate having a number of input terminals corresponding to the number of bits, and is arranged inside or outside the ALU 15. The most significant bit 30-1 is reflected in the flag register 17 (flag pin)-N (negative), and data bit 3
If 0-1 to 30-N are all zero, flag register 1
The contents of parity bit 30-N+1 are reflected in bit P (parity). Since the flag set in this way is used after the next instruction execution cycle, there is no particular problem even if the flag is set at the same timing as the calculation cycle in the ALU 15.

Note that the data transmitted to the bus BUS3 via the transmission path 100 may be taken into the registers 11 to 13 (excluding the transfer source).

According to this embodiment, there are the following effects.

(1) A transmission path 100 is provided for transmitting data to be input to the ALU 15 in parallel with the ALU 15 that enables arithmetic processing of input data, and the output signal of the ALU 15 is further provided in response to the control signal C0NI. Since an output selection unit 101 is provided that can selectively output the transmission signal of the calyx and the transmission path 100, the transmission signal can be output from the registers 11 to 13 to the outside through the transmission path 100 without going through the ALU 15. data transfer can be performed, thereby increasing the speed of the data transfer.

(2) Data transfer that does not involve direct arithmetic processing in the ALU 15 occurs relatively often in the execution unit 29, and therefore, according to the effect of (1) above, the entire execution unit 23 and the entire processor 21 Operation speed can be improved.

(3) Advances in semiconductor process technology have made it possible to reduce the processing section of conventional large-scale computers to a single chip, making it essential to have multiple pipelines in the arithmetic processing section, parity/FCC code processing, etc. In such a case A
Since it is inevitable that the internal signal delay in the arithmetic unit such as LtJ15 is further increased, the effects of (1) and (2) above are particularly noticeable in such a system.

(4) The output selection unit 101 includes a tri-state buffer 14 provided in the transmission path 100 and a tri-state buffer 16 that is coupled to the output terminal of the ALU 15 and operates complementary to the tri-state buffer 14. This configuration is effective in simplifying the configuration of the output selection section 101.

(5) Even when the output selection unit 101 selects the transmission signal of the transmission path 100, the ALU 15 executes arithmetic processing for determining the attribute of the transmission signal of the transmission path. Discrimination is possible.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto, and various changes can be made without departing from the gist thereof.

For example, instead of the tri-state buffers 14 and 16 that constitute the output selection section 101, a transfer gate or other element or circuit having the same function can be applied.

In the above explanation, the invention made by the present inventor was mainly applied to a microprogram control type processor, which is the field of application that formed the background of the invention, but the present invention is not limited thereto, The present invention can be widely applied to peripheral controllers having the following functions, as well as various central processing units for office computers, engineering workstations, etc. The present invention can be applied to devices that are equipped with at least an arithmetic unit and perform data processing.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, the transfer data is transmitted in parallel to the calculation section through the transmission path, and the output selection section selects the transmission signal of this transmission path, thereby performing data transfer without going through the calculation section. This makes it possible to speed up data transfer.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of a processor according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the overall structure of the processor. FIG. 3 is an explanatory diagram of a data attribute discrimination circuit included in this embodiment, and FIG. 4 is a block diagram of a conventional example. 11 to 13... register, 14, 16.19...
Tri-state buffer, 15...ALU, 17...
Flag register, 18... Inverter, 100...
Transfer path, 101... Output selection unit, 21... Processor, 31... Nantes gate. Figure 2 Figure 2I / Figure 3

Claims (1)

[Claims] 1. In an arithmetic processing circuit including an arithmetic unit that enables arithmetic processing of input data, a transmission path for transmitting data to be input to the arithmetic unit in parallel with the arithmetic unit; . An arithmetic processing circuit comprising: an output selection section capable of selectively outputting an output signal of the arithmetic section and a transmission signal of the transmission path in response to a control signal. 2. The output selection section is configured to select a first
2. The arithmetic processing circuit according to claim 1, comprising: a tri-state buffer; and a second tri-state buffer coupled to an output terminal of said arithmetic unit and operated complementary to said first tri-state buffer. . 3. Even when the transmission signal of the transmission path is selected by the output selection section, the calculation section executes calculation processing for determining the attribute of the transmission signal of the transmission path.
Or the arithmetic processing circuit according to 2.