JPS588365A - Status career storage system - Google Patents

Abstract

PURPOSE:To prevent the registration of redundant information, by controlling the storage to a status career storage circuit when the internal status information at present and just preceding are coincident with each other, and storing the number of coincident times of the internal status information to the status career storage circuit. CONSTITUTION:A microinstruction readout address circuit 11 instructs the address to read out the microinstruction of the address in a microinstruction word memory 12 and sequentially stores the output address to an address comparison register 32'. The address output of the circuit and the address stored in the register 32' are compared at an address comparison circuit 40, the content of the circuit 11 is sequentially stored in a status career storage circuit 20. Every time when the storage is executed, the address counter 31 revises the content of an address register 30. When the result of comparison is coincident in the circuit 40, the number of times of coincidence is counted at a coincidence counter 41 and the revision of the status career storage data of the internal state can not be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION This state history storage method stores the history of internal states for tracing the operation of information management equipment.

Conventionally, this type of state history storage scheme is
c As shown in FIG. (abbreviated as register)
, counter i1 and butts, various timing 4
I-wheel For example, command execution control every 7 arm wear steps.
The circuit 10 also outputs the contents stored in the internal state information register s2 to the state history storage □ circuit 20. State history memory at the time of Jin - The storage address for Roku is an address register! IO, state history storage path 20
&: 411 to store the contents of internal state information register s2
The contents of the C% address register bO are set so that the counter s1 indicates the next address stored in the update register, and the internal state can be stored from the low address of the state history memory 1i112G. ing. By storing the internal state information, the internal state information can be outputted and used for dealing with disabled books.

But 1! However, the state history memory circuit 20 has a limited storage capacity, and when the internal state II disaster report is recorded at the highest address x11 of the state history memory al120, the state history memory circuit 20 is again under the control of the address register sO. When the lowest address of &: is stored, the address register sO counter s1 points to the next address, and the status history memory 1 is changed.
1j12oh - Stored internal state information is old Il
Book C was missing. For this purpose, each step of the firmware instruction internally executes the next state! In the operation trace stored in the memory circuit 20, redundant information is stored when the same step is performed many times due to asynchronous meeting with a bribe, etc., and these redundant quasi-memories are useful when a failure occurs. First, there was the drawback of missing more useful information.

Honmari #I#211! In order to eliminate the above-mentioned shortcomings of the past, the present invention 0IlvJ#2, the present invention, sequentially registers the internal state information of the device to the state history memory W path, p&:, the current and ■ key. When the internal state information of the internal state information of
A new value that prevents redundant information from being stored in the p% state history memory circuit by storing it in illI, makes it possible to use sea lanes more effectively, and also makes it possible to understand the relationship with real time. 11k state history storage method.

That is, according to Wli Motoya, in an information contemplation device that has a memory history state history storage circuit for storing IIklII history inside the device, there is a holding gui that holds the internal state of the device, and then an internal state and a spear that retain the internal state of the device. A comparison circuit that compares the internal state held and stored in the record/hold four paths, and a control operation that stores the state history in the state history record path based on the comparison results. C1kl+ to suppress memory using the state history storage control circuit and the test state history storage control aii*
The state history storage system, which is composed of 6 types such as kakunta, which records the number of controlled operations, is looked down upon.

Next, the present invention will be explained in detail with reference to the II page with reference to a preferred embodiment of the present invention.One aspect of the present invention is the history storage of firmware addresses of an information contemplation device controlled by firmware. The method will be explained.

@21f is a plotter structure showing an example of this invention. 11, the same reference number as in Figure 1 is l111!
Same element as I 1 showing 0 1 of the present invention 1 I! Examples are:
A microinstruction memory 12 which is provided in the information contemplation device 1' and which stores the microinstruction II, and a microinstruction memory 12 for reading the microinstruction at the address in the experimental microinstruction memory 12 is provided. Microinstruction that specifies the address
A read address branch (hereinafter abbreviated as a micro address circuit) 11, an address register (hereinafter abbreviated as a register) 32' for sequentially storing the output addresses of the micro address branch 11, and a key distribution register 32'. An address ratio Il! for comparing the address indicated by the microaddress circuit 11 and the address stored in the register s2'. −Route (
40 (hereinafter abbreviated as comparison jump), the address indicated by the four microaddress paths 11, and the value of the coincidence counter (described later) are sequentially stored in the -<state history storage path (hereinafter referred to as history storage path). (abbreviated) 20 and %*M An address register 30 indicating an address to be stored in the history memory garden path, and the history storage system 20 is provided with the mytalo address circuit 11 or 6e.
an address counter (hereinafter abbreviated as counter) that updates the contents of the address register 50 every time the contents are stored;
31, and a match counter 41 that counts and records the a# that matched at step 40.

Figure 11!3 is an operational tie construction diagram of the actual example shown in 1112WJ. The micro-instruction Akebono read from 12 is compared, S-ink shows the w function of 11114G, the output of 84-system Sisk s2', and the output of S-Jinsha counter 41. %C%'Circuit that operates asynchronously with the microcommand (0 is not shown in Figure 2)
B, I) is the address of the Mytaro command word that makes a synchronous wait from the microphone command and gives an operation instruction at 1kvh, and operates by waiting nu with the enclosure which is operating asynchronously with the microphone master command. Each indicates a microinstruction 110 address that provides an instruction.

FIG. 4 shows the storage status of the address of the Mitaro instruction word in the history storage circuit 20 and the value of the coincidence counter 41 in the tie construction shown in the building sW.

Below, we will explain the detailed operation of Motonakamei based on the block diagram of &: Kame 21m and the tie 5 ring of Juku S map. The microinstruction 11m in the miter address circuit 12 is read out from the microphone-instruction address AC indicated by the microinstruction address circuit 11. This address 1 company register 52
The comparison circuit 40 calculates the ratio I2 with the address stored in '. Now, it is assumed that address l matches the contents of register B2p and is e%A.

History memory path 20 is accessed by address register sO.
- The count value of the address tzrJ' match counter 41 indicated by the micro address circuit 11 is stored in the indicated address. Address register 30 is counter s1
The address is updated via , and the match counter 41 is set O&: because the result of the comparison path 40 is a mismatch. Maitada Instruction II & Company, Micro Life 4Fm
In order to avoid waiting time from circuits that are not synchronized with the miter command, the miter command X [ll111 is used to write the next mi/11 command address 1 indicated by the miter command Akebono a to the miter command. ■Memory 12 &: Shown.

In the next step, the miter command danme 4 so 12 or b miter command -1 is issued.

Address II is compared with '&' in the comparison circuit 40 in the same way as the address register, and since there is a mismatch, the history memory circuit 20 goes to the address indicated by the address register 3o in the same way as the address 1. Address 1 and the count value of the -interval counter 41 are stored. Further, the address of the address register 30 is updated via the counter 31, and the -interval counter 41 is also O&:
Reset damn. Since this miter command ◆l1fb is synchronized with the microinstruction word and waits from -Ik%/%1III, the tie-building of 11IsIl is now waiting for the asynchronous path. In this case, non-1ll
Il! □ Address B even though my Ia address circuit 11 is not receiving the signal from 1.
The microinstruction 4912 shows the address B again, so read out the microinstruction 11.
Since there is an error with the contents of the register ', updating of the address in the address register 30 is inhibited, and the value of the -interval counter 41 is incremented by 1. However, even on this platform, the contents of the history memory 1120 and the register J$2' are filled with the content of the catfish.

Signal from Thai construction gs''e
Ruto! In the Italian dress 111111, the address C is specified to the 12 in the ``My Instruction I'' in the tie (Nugu 5). In the miter instruction word memo 12, the company address C&:corresponding microinstruction word - is read out, and it is the same as before. The addresses are compared as follows. ζThe company comparison link 40 makes a negative Ikk judgment and instructs to update the address register sum.
The value of the negative counter 41 is set to 0&:. At this time, the history storage circuit 20. The respective contents can also be written into the nine stars 12'. History distribution! The value 1 of the match counter 41 is stored again along with the address C in the address that was written once in the OC mining process &:'1
Niru. Also, since the first miter command is not an instruction that waits for an asynchronous path, the master 418 address IQ 1111 indicates the next address D indicated by the miter command I memory 12 &: 1111. . On the other hand, the address register 30 is also updated, and the corresponding contents are also stored in the history storage path 2o register 12'. Jin's Maita ■Life◆
■-I have a waiting meeting for the 8th order, Tai 5 Ngukaku 1
During this time, the address register SOW and comparison 40 are frozen as a match, so no update is performed, but the key record match counter 41 is updated by 1+1.
Finally, the control count value #s2& is calculated.

In the 20th generation, the history of the S step in the address register is stored in the memory of the address register, even though the command word of the step was deleted in the 20th generation. take.

Among the address history memories of 11411, the address C was stored in the memory area, and once the address jfIX was stored, it was re-memorized and the address CJ:t was returned.
, the storage area of address I. Similarly, address l) is written twice I
It is a turtle that has been re-memorized.

As explained above, by checking the internal state of the IIE and the direct key, and controlling whether or not the state information can be stored based on the result, redundancy can be eliminated. In addition, by memorizing matches where the internal states match, the relationship with the included time can be calculated.
p! : There is.

[Brief explanation of the drawing]

1WJ is a plotter structure showing the conventional technique of ■, 111I2■ is a block configuration showing an example of this invention, and 1IsWJ is a plotter configuration shown in 112. , No. 41 is a column indicating the memory record of the address layer in the history storage circuit. 1.1'...Information processing device, 10.Crow-instruction execution control 11111 11.0 microinstruction - read address ll*1III, 12...Microinstruction dawn message, 2
0...Status history memory S*, Persimmon...Address register, 31...Counter, 32...Internal status information, 9 stars, s2'...Address comparison, ν star, 40...・Hisunkanro, 41... Match terminal, '%'%1-... Asynchronous link 7' waiting meeting '1, 1 Maitaro command address, 1, D・^・Asynchronous- My Its instruction l address that has a rendezvous with the road, ``%'k1%-1d1-・*e
Miter Instruction Patent Applicant at the above address of Miter Instruction Akebono 4g Patent Attorney Yutabe Kumagai Figure 1 Figure 2

Claims (1)

[Claims] A holding enclosure for storing the internal state of the device; -Comparing the internal state of the device that develops with the %/% retained in the III retention path and the result of comparison with the Mongolian comparison am-1 It is equipped with a state history memory control circuit that controls whether or not to store the state history in the preliminary state history memory am, and a counter that counts the number of instances where memory has been suppressed in the experimental state history memory control circuit. A state history storage method with a unique feature.