JPS5858627B2 - Isousa Sokutei Souchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention multiplies the phase difference between a plurality of signals to be measured having a fundamental frequency f in a high frequency relationship, for example, 6f and 5f, to a least common multiple relationship, and in the case of 5f and 6f, effectively The present invention relates to a device for measuring a phase difference at a frequency of 30f, and will be described below with reference to the drawings.

In Fig. 1, the signal of 6f is multiplied by 3
It is converted into an Off signal.

The 5f signal is converted to a 30f signal by a 6-multiplier circuit 02, the phase difference between the two 30f signals is detected by a phase difference detection circuit 03, and the phase difference can be read by a phase difference meter 04.

The circuit shown in FIG. 1 is a conventional analog multiplier type measuring device, and because it uses two multiplier circuits, it has the disadvantage of having errors due to fluctuations in ambient conditions such as temperature.

FIG. 2 shows a circuit in which a conventional analog system is implemented using a digital phase lock system, in which a 6f signal is converted to 30f by a 5-multiplying circuit 6 and introduced into an error detection circuit 5.

If you want to measure the 30f signal in units of Vloo,
The reference oscillator 1 generates a signal of 300Of, and the frequency dividing circuit 2 divides the signal to 1/100.

The output of the frequency dividing circuit 2 is introduced into a coincidence detection circuit 3 to create a coincidence signal with the phase difference value register 4.

The coincidence signal is introduced into the error detection circuit 5, and as shown at 41 in FIG.
An addition or subtraction signal is sent out depending on whether OI+ or OI+ is used, and the match signals 42, 43, and 44 eventually arrive at the rising or falling points of the signal 3Of in FIG. 441.

Further, the 5f signal is converted to 3Of by the 6 multiplier circuit 11 and introduced into the error detection circuit 10.

The 300Of signal generated by the reference oscillator 1 is divided by 1/100 by the frequency dividing circuit 7, and the output of the matching circuit 3 is output at the reference point (rising or rising edge) of 30f, which is multiplied by 6f. In order to reset the frequency divider circuit 7, the starting point of the frequency divider circuit 7 is exactly 3 created by 6f.
This means that the phase is synchronized to 0f.

Here, the coincidence detection circuit 8 detects coincidence between the signals of the phase difference register 9 and the frequency dividing circuit γ, and sends the coincidence output to the error detection circuit 10 to perform the same operation as the phase lock of 30f by 6f. The numerical value placed at 9 is the phase difference value itself between 30f due to 6f and 30f due to 5f.

Even in this method, since the multiplier circuits 6 and 11 are used, there are errors due to temperature and the like.

The present invention completely eliminates the error caused by such a multiplier circuit, simplifies the circuit configuration, and effectively provides the same effect as measuring the phase difference using a 30f signal.

An embodiment of the present invention will be described with reference to FIG.

The phase difference between the signals of 6f and 5f is 1/100 for 3Of.
Suppose that it is measured in units of .

A reference signal of 300Of is generated by the reference oscillator 21.

The signal of 3000f is frequency-divided by the l/100 frequency divider circuit 22.

A match detection circuit 23 detects whether the output of the frequency dividing circuit 22 matches the register 24 .

The frequency of the output of the coincidence detection circuit 23 has a period of 30f.

This coincidence output is 115 by the frequency dividing circuit 25, and the coincidence output has a cycle of 6f.

The output of the frequency divider circuit 25 is introduced into the error detection circuit 26 together with the 6f signal, and the output of the error detection circuit causes the register 24 to be output so that a coincidence output is output at the rising or falling point of the <6f signal as shown in FIG. Add or subtract numbers.

Further, the output of the frequency dividing circuit 25 which has divided the frequency of the coincidence detection signal is divided by 1f6 by the frequency dividing circuit 27 to convert the coincidence signal into a period of f.

The 3000f signal generated by the reference oscillator 1 is sent to the frequency divider circuit 2.
The frequency is divided by 1/100 by 8, but the frequency dividing circuit 28 is divided by 6.
Since it is reset by dividing the reference point of the signal f into the period f, the starting point of the frequency dividing circuit 28 is precisely phase-locked to the signal 6f.

The output of the frequency divider circuit 28 is introduced into the coincidence detection circuit 29 together with the output of the register 30.

Since the output of the frequency output circuit 29 has a period of 30f, the frequency is divided by 1f6 by the frequency dividing circuit 31 to convert it to a period of 5f, and the output is introduced into the error detection circuit 32 together with the 5f signal.

Depending on the output of the error detection circuit 32, the register 30 is set so that the coincidence output is at the rising or falling point of the 5f signal.
By adding or subtracting , the digital phase lock system from circuits 22 to 27 is phase-locked to the signal of 6f,
The 5f digital phase lock system is synchronized with the 6f digital phase lock system by a frequency dividing circuit 28 that is synchronized by resetting the phase-locked 6f by f divided by the frequency dividing circuit 27. Since the phase lock system, that is, the circuits 28 to 32 are phase-locked to the 5f signal, the final result is 30f due to 6f.
The phase difference between 30f and 5f is stored in the register 30 of one of these digital phase lock systems.

As described above, the present invention uses signals of a plurality of frequencies 5f and 6f that are in a high frequency relationship with the fundamental frequency f as signals to be measured, and calculates the phase difference between the signals to be measured. A phase difference measuring device that measures at a frequency 30f that is the least common multiple of frequencies 5f and 6f, and includes one reference oscillator 21 that generates a reference signal 3000f of a frequency that provides a unit sum of 0 required for this measurement, a first frequency dividing circuit 22 that divides the reference signal 3000f to the same frequency as the least common multiple frequency 3Of and outputs the same frequency; a register 24 that detects a match between the output of the first frequency dividing circuit 22 and the output of the register 24 and outputs a match output;
a second frequency divider circuit 25 that divides the output of the second frequency divider circuit 25 to the same frequency as one frequency 6f of the plurality of frequencies 5f and 6f, and outputs the output of the second frequency divider circuit 25; An error detection circuit 26 detects and outputs an error with the signal under test at one frequency 6f, and an output of the error detection circuit 26 causes the output of the minus number output circuit 23 to be adjusted to the one frequency 6f.
A digital phase lock system 22-- which is a means for adding or subtracting the number set in the register 24 so that the rising or falling point of the signal under test f, that is, the measurement point is reached.
Digital phase lock system 28-3 having the same configuration as 26
2 are also provided for the signals under test 5f of other frequencies among the plurality of frequencies 5f and 6f, that is, the same number as the signals under test are provided, and one third frequency dividing circuit 27 that divides the output of one second frequency dividing circuit 25 to the fundamental frequency f and outputs the resultant signal;
and means for synchronizing the frequency division of this frequency dividing circuit 28 by resetting the second frequency dividing circuit 28 of the other digital phase lock system with the output of the third frequency dividing circuit 27. , is a phase difference measuring device characterized in that the phase difference is measured by the number set in one of the registers 24 and 30, and according to the present invention, since an analog multiplier circuit is not used, the temperature It is not affected by the surrounding conditions such as, and it is possible to easily measure multiple signals that have a harmonic relationship with each other in a least common multiple relationship using a digital circuit with a simple circuit configuration, and the effect is remarkable. It is.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing a conventional device using an analog system. 01...5 multiplier circuit, 02...6 multiplier circuit, 03...phase detection circuit, 04...
・Phase difference meter. FIG. 2 is a configuration diagram showing a conventional device using a digital phase lock method. 1... Reference oscillator, 2... Frequency divider circuit,
3... Coincidence detection circuit, 4... Register, 5... Error detection circuit, 6... 5 multiplier circuit, γ... Minute cycle circuit, 8...match detection circuit, 9...register, 10...error detection circuit, 11...6 multiplier circuit. FIG. 3 is a configuration diagram showing an embodiment of the present invention. 21... Reference oscillator, 22... Frequency dividing circuit, 23... Coincidence detection circuit, 24...
Register, 25... Frequency divider circuit, 26...
・Error detection circuit, 27... Frequency division circuit, 28...
...Frequency divider circuit, 29...Coincidence detection circuit, 3
0...Register, 31...Divide circuit,
32...Error detection circuit. FIG. 4 is a waveform diagram showing the error detection operation. 41...30f signal, 42,43.44...
... Match signal.

Claims (1)

[Claims] 1. A signal of each frequency of a plurality of frequencies having a high frequency relationship with the fundamental frequency is taken as a signal to be measured, and the phase difference between each of the signals to be measured is calculated as the frequency of the least common multiple of the plurality of frequencies. A phase difference measuring device for measuring a phase difference, comprising one reference oscillator that generates a reference signal of a frequency from which the unit required for the measurement is obtained, and that divides the reference signal into frequencies that are the same as the frequency of the least common multiple. A first frequency dividing circuit that rotates and outputs a frequency, and a value serving as the phase difference is set,
a register that outputs the output according to this set number; a coincidence detection circuit that detects a coincidence between the output of the first frequency dividing circuit and the output of the register and outputs a coincidence output; and an output of the coincidence detection circuit a second frequency dividing circuit that divides and outputs the same frequency as one of the plurality of frequencies; and an output of the second frequency dividing circuit and the signal under test having the one frequency. an error detection circuit that detects and outputs an error; and an error detection circuit that adds the numbers set in the registers so that the output of the coincidence detection circuit comes to the measurement point of the signal under test of the one frequency based on the output of the error detection circuit. or a means for subtracting, and the same number of digital phase lock systems as the number of signals under test are provided, and the output of the second frequency dividing circuit of one of the digital phase lock systems is divided into the fundamental frequency. one third frequency divider circuit that rotates and outputs the frequency, and means for synchronizing the frequency division of the first frequency divider circuit of another digital phase lock system with the output of the third frequency divider circuit; A phase difference measuring device, characterized in that the phase difference is measured by the number set in one of the registers.