JPH11326404A - Minute error detecting device for frequency - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily measure with high accuracy a difference frequency with a simple circuit by comparing and outputting each counter value at the time of a stop action of a counter based on a specific procedure. SOLUTION: For example, an oscillation frequency f on a specification of generators 1, 2 is defined as 10 MHz, a nominal accuracy S is defined as 1×10<-7> and each actual frequency at this time is defined as f1 =10<7> Hz, f2 =9999999.6 Hz. An interval of a start signal and a stop signal is prepared by frequency- dividing the generator by 1×10<8> by a frequency divider circuit 5 and the interval of both start and stop signals is defined as T=1×10<8> /f1 and T=10 second. So, a counter A3 counts f1 ×T=10<8> times. Similarly, a counter B4 counts f2 ×T=99999996 times. The counter A3, B4 are sufficient cyclic counters of approximately 8 bit and the difference C is outputted as +4 by a comparator 6. The fact indicates that the frequency of f1 is higher by 0.4 Hz than that of f2 .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency error detector for receiving signals from two or more oscillation sources having very similar frequencies and calculating a frequency deviation between the signals.

[0002]

2. Description of the Related Art Conventionally, when there are two or more oscillation sources having the same oscillation specification, which are very similar, a phase detector or a frequency comparator is used as a frequency minute error detector for obtaining a difference frequency between them. There is one that calculates a difference frequency.

[0003]

However, the conventional frequency minute error detector uses a phase detector and a frequency comparator to detect the difference frequency, which results in a complicated circuit configuration. There was a point.

[0004]

According to the present invention, there is provided a frequency small error detector according to the present invention, which outputs an output signal of one of two or more oscillators that generate a very similar frequency by a predetermined number of divisions. A dividing circuit for dividing and outputting, and a start and stop operation based on an output signal of the dividing circuit,
A counter that counts the output signals of two or more oscillators, and a comparator that compares each counter value of the counter when the counter stops, and outputs the difference as a small frequency error signal. .

[0005]

FIG. 1 is a block diagram showing a configuration of a small frequency error detector according to one embodiment of the present invention. In the figure, 1 is an oscillator that originally has an oscillation frequency specification of fHz and is actually f1 Hz, and 2 is an oscillator that originally has an oscillation frequency specification of fHz and is actually f2 Hz.
Reference numeral 3 denotes a counter A for counting the output of the oscillator 1. When a start signal is input, the counter is reset to start counting, and continues counting with a clock of frequency f1 until a stop signal is input. 4
Is a counter B for counting the output of the oscillator 2. When a start signal is input, the counter is reset, and continues counting cyclically with a clock of frequency f2 until a stop signal is input.

A frequency dividing circuit 5 divides the frequency of the clock output from the oscillator 1 and generates a start signal and a stop signal to the counters A3 and B4. Here, the interval between the start signal and the stop signal is T seconds. The start signal and the stop signal in the frequency divider 5 may be generated, for example, by generating a start signal at the rising edge of the divided clock and generating a stop signal at the next rising edge of the divided clock. Output to counter.

Reference numeral 6 denotes a comparator which takes the difference between the value A indicated by the counter A3 and the value B indicated by the counter B4 when the counters A3 and B4 stop counting and outputs the result as a value C.

Next, the operation of this embodiment will be described. First, as a specific example 1, an outline of the operation will be described. In the configuration of FIG. 1, the oscillation frequency f of the oscillator 1 and the oscillator 2 in the specification is 10 MHz. This nominal accuracy S is 1
× 10 ^-7 . At this time, f1 = 10000000.0Hz, f2 =
Set to 999999.6Hz.

An interval between the start signal and the stop signal is created in the frequency divider circuit 5 by dividing the oscillator 1 by 1 × 10 ⁸ , and the interval between the start signal and the stop signal T = 1 × 10 8
⁸ / f1 and T = 10 sec. Then, the counter A3 counts f1 × T = 1000000000 times.

Similarly, the counter B4 is given by f2 × T = 999999.
You will be slammed six times. As the counters A3 and B4, a cyclic counter of at most about 8 bits is sufficient, and the difference C is output as +4 by the comparator 6. This is because in this case f1 is greater than f2
This means that the 0.4 Hz frequency is high.

From the above results, the operation of detecting a small frequency error is generalized as follows. First, the effective digits are known from the accuracy of the oscillator 1 and the oscillator 2, and the frequency division number N in the frequency dividing circuit is determined. Here, the accuracy S is ^{defined as} S = a × 10 ^−b (1
≦ a <10, b is a natural number), and the number of frequency divisions N = 1 × 10
^{b + n} (n is a natural number). At this time, when the interval T between the start signal and the stop signal is T = N / f1, the obtained frequency difference Δf is Δf = f (nominal frequency) × 10
^{-(b + n)} × C (comparator output) Hz. Here, n
Is larger, counter A3, counter B4
Becomes large (that is, the value of C becomes large)
However, usually n = 1 is sufficient.

Next, a specific example 2 based on the above generalization operation will be described. First, f = 20kHz, S =
4 × 10 ^-6 , f1 = 20000.03 Hz, f2 = 19999.97 Hz. Here, based on the above generalization operation, the frequency division number N is set to n = 1, 1 × 10 ⁷ , and the start signal / stop signal interval T is set to T = 1 × 10 ⁷ /f1=499.9992.
sec.

At this time, the counter A3 counts f1 × T = 100000
The 00 count and the counter B4 count f2 × T = 99999970, and thus C = 30. At this time, f1 and f
2 is Δf = f × 10 ^{− (b + 1)} × C = 20 × 10
³ × 1 × 10 ⁻⁷ × 30 = + 0.06 Hz, and it can be detected that f1 is 0.06 Hz higher than f2.

Although the scale (maximum count value) of the counters A3 and B4 in this embodiment is required to be at least twice as large as the finally obtained maximum C, the actual scale is About 8 bit counter is enough.

The comparator 6 calculates the difference between the counter A3 and the counter B4.
If the counter B4 is an 8-bit cyclic counter of 0 to 255, and if AB is simply the output C of the comparator 6, a large numerical value near 255 may be output. When the difference between the counter B4 and the counter B4 takes a value equal to or more than a certain value K, C = − (256−
(A-B)) and the output C of the comparator 6 solves the problem.

Here, the value of K is assumed to be 256- (maximum C + 1) or less. Incidentally, the expected maximum C can be easily calculated from the precision S in the above-described generalization formula by taking into account the maximum deviation. Also, this K
Assuming that the numerical value of 256 is the maximum count value of the counters A3 and B4 + 1, not only the 8-bit counter but also arbitrary counters A3 and B
4 is possible.

The detection error in this embodiment is as follows. In this embodiment, the phase difference between the oscillator 1 and the oscillator 2 is completely arbitrary.
The error is a maximum of ± 1 count, and high-precision detection can be performed.

In this embodiment, the output clocks of the two oscillators are counted by the respective counters, and each counter is started and stopped based on a signal obtained by dividing the output of one of the oscillators. , And outputs the difference to detect the minute error of the frequency of each oscillator. Therefore, the difference between the respective oscillation frequencies can be measured with a very simple circuit in a short time and with high accuracy. It becomes possible. Further, the frequency difference is obtained as a plus / minus result, and it is possible to determine which frequency is higher or lower. Also, if one oscillator is a known standard oscillation source, it can be used as a calibration device, and application in all fields can be expected.

Further, in this embodiment, the description has been made with the example of two oscillators. Similarly, the output clocks of a plurality of oscillators are counted by a plurality of counters, and the start and stop of each counter are determined by the plurality of oscillators. By performing the output of one of the oscillators based on the frequency-divided signal and comparing the count values of the respective counters, it is possible to detect the minute frequency error of each oscillator.

In this embodiment, the oscillators 1, 2
Has been described using the example of an output oscillator as a digital clock. In the case of an analog oscillator, the output signal of each oscillator is converted into a digital signal by an analog-to-digital converter, etc. It is possible to detect a small error.

[0021]

As described above, according to the present invention, the output signal of one of the two or more oscillators that generate a very similar frequency is divided by the frequency dividing circuit according to the present invention. The counter performs a start and stop operation based on the output signal of the divider circuit,
The output signals of two or more oscillators are counted, and when the counters stop by the comparator, each counter value of the counter is compared, and the difference is output as a small frequency error signal. The difference between the oscillation frequencies of the
Moreover, there is an effect that measurement can be performed with high accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a small frequency error detector according to one embodiment of the present invention.

[Explanation of symbols]

 1, 2 oscillators 3 Counter A 4 Counter B 5 Divider circuit 6 Comparator

Claims (3)

[Claims] 1. A frequency dividing circuit that frequency-divides an output signal of a certain one of two or more oscillators that generate a very similar frequency by a preset number of frequency divisions and outputs the frequency-divided signal. A counter that starts and stops based on the output signal and counts the output signals of the two or more oscillators, respectively. When the counter performs a stop operation, each counter value of the counter is compared, and the difference is used as the frequency. A frequency error detector comprising: a comparator that outputs the error signal as an error signal. 2. An output signal of a certain one of two or more oscillators generating a very similar frequency is divided by a predetermined number of frequency divisions, and based on a period of the divided frequency, A frequency divider circuit that generates and outputs a start signal and a stop signal; and a start operation when a start signal is output from the frequency divider circuit, and a stop operation when a stop signal is output from the frequency divider circuit; A counter that counts the output signals of the two or more oscillators, and a counter value of the counter when the stop signal output from the frequency divider circuit is output, and outputs the difference as a frequency minute error signal. A small error detector comprising: 3. The nominal frequency of the oscillator is f, the precision S is S = a × 10 ^−b (1 ≦ a <10, b is a natural number), the frequency division number N of the frequency dividing circuit is N = 1 × 10 ^{b + n} (n is a natural number), and the frequency deviation Δf of each of the two or more oscillators is
3. The method according to claim 1, wherein Δf = f × 10− ^{(b + n)} × C using a frequency minute error signal C corresponding to each oscillator of the comparator. vessel.