JPS5858601U - Sequence control device - Google Patents
Sequence control deviceInfo
- Publication number
- JPS5858601U JPS5858601U JP15345981U JP15345981U JPS5858601U JP S5858601 U JPS5858601 U JP S5858601U JP 15345981 U JP15345981 U JP 15345981U JP 15345981 U JP15345981 U JP 15345981U JP S5858601 U JPS5858601 U JP S5858601U
- Authority
- JP
- Japan
- Prior art keywords
- registers
- output
- pair
- storage device
- control device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Feedback Control In General (AREA)
- Programmable Controllers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図は本考案の一実施例の要部を示すブロック図である。
１・・・・・・記憶装置、２・・・・・・アドレスカウ
ンタ、５゜６．７および８・・・・・・レジスタ、９お
よび１０・・・・・・マルチプレクサ、１１・・・・・
・比較器。The figure is a block diagram showing the main parts of an embodiment of the present invention. 1...Storage device, 2...Address counter, 5°6.7 and 8...Register, 9 and 10...Multiplexer, 11...・・・
・Comparator.
Claims (1)
次読出して、読出した情報に従って順次対象を制御する
シーケンス制御装置はおいて、出力が順次＋１または−
１されて前記記憶装置にアドレスを指定するアドレス指
定手段と、前記記憶装置のアドレス範囲を複数区分に区
分する複数対のレジスタと、前記複数対のレジスタ中か
ら１対のレジスタを選択する選択手段と、前記選択手段
により選択された１対のレジスタの置数と前記アドレス
指定手段の出力とを比較し前記１対のレ−）ｘ夕の何れ
か一方の置数に前記アドレス指定手段の出力が一致した
とき前記アドレス指定手段の出力 □を変化させるこ
とを少なくとも禁止する禁止手段とを備えてなること栃
特徴とするシーケンス制御装置。A sequence control device that sequentially reads information stored in a storage device over a predetermined range and sequentially controls a target according to the read information has an output that sequentially changes to +1 or -.
1, addressing means for specifying an address to the storage device; a plurality of pairs of registers for dividing the address range of the storage device into a plurality of sections; and selection means for selecting one pair of registers from the plurality of pairs of registers. and compares the number set in the pair of registers selected by the selection means with the output of the addressing means, and sets the number set in one of the pair of registers to the output of the addressing means. and prohibiting means for at least prohibiting a change in the output □ of the addressing means when they match.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15345981U JPS5858601U (en) | 1981-10-17 | 1981-10-17 | Sequence control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15345981U JPS5858601U (en) | 1981-10-17 | 1981-10-17 | Sequence control device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5858601U true JPS5858601U (en) | 1983-04-20 |
| JPS622643Y2 JPS622643Y2 (en) | 1987-01-22 |
Family
ID=29946074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15345981U Granted JPS5858601U (en) | 1981-10-17 | 1981-10-17 | Sequence control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5858601U (en) |
-
1981
- 1981-10-17 JP JP15345981U patent/JPS5858601U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS622643Y2 (en) | 1987-01-22 |
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