JPS585130U - programmable logic controller - Google Patents
programmable logic controllerInfo
- Publication number
- JPS585130U JPS585130U JP9827981U JP9827981U JPS585130U JP S585130 U JPS585130 U JP S585130U JP 9827981 U JP9827981 U JP 9827981U JP 9827981 U JP9827981 U JP 9827981U JP S585130 U JPS585130 U JP S585130U
- Authority
- JP
- Japan
- Prior art keywords
- display means
- display
- programmable logic
- turned
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はこの考案の一実施例の概略ブロック図である。
第２図は第１図の各部の波形図である。
第３図はこの考案の一実施例の具体的な動作を説明する
ためのフロー図である。 −
図において、５は入力制御部、８は出力制御部、９は発
振回路、１０は監視タイマ、１１はｃｐｕ。
１２は異常検出回路、１３は保護バッテリ、１４はメモ
リ、１５は初期リセット発生回路、１６はラッチタイミ
ング発生回路、１８，２０．２’２はフリップフロップ
、２６，２８．３１は表示器を示す。FIG. 1 is a schematic block diagram of an embodiment of this invention. FIG. 2 is a waveform diagram of each part of FIG. 1. FIG. 3 is a flow diagram for explaining the specific operation of one embodiment of this invention. - In the figure, 5 is an input control section, 8 is an output control section, 9 is an oscillation circuit, 10 is a monitoring timer, and 11 is a CPU. 12 is an abnormality detection circuit, 13 is a protection battery, 14 is a memory, 15 is an initial reset generation circuit, 16 is a latch timing generation circuit, 18, 20.2'2 is a flip-flop, and 26, 28.31 is a display device. .
Claims (1)
タを処理して外部機器を制御するとともに、異常を判別
する制御手段と、 異常状態を表示する表示手段と、 前記制御手段の異常判別出力信号に基、づいて前記表示
手段に異常状態を表示する表示駆動手段と′ を備え
たプログラマブルシーケンスコントローラにおいて、さ
らに 電源投入時に前記表示手段を強制的に点灯させる手段、
および 電源投入後に所定の時間を計時し、その計時出力信号に
基づいて前記表示手段を消灯させる手段を備えたことを
特徴とする、プログラマブルロジツクコントローラ。[Scope of Claim for Utility Model Registration] Control means for controlling external equipment by processing input data based on a pre-stored program and determining abnormality; display means for displaying abnormal conditions; A programmable sequence controller comprising display driving means for displaying an abnormal state on the display means based on an abnormality determination output signal of the control means; and means for forcibly lighting the display means when the power is turned on;
and means for counting a predetermined time after power is turned on and turning off the display means based on the clock output signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9827981U JPS585130U (en) | 1981-06-29 | 1981-06-29 | programmable logic controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9827981U JPS585130U (en) | 1981-06-29 | 1981-06-29 | programmable logic controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS585130U true JPS585130U (en) | 1983-01-13 |
Family
ID=29893043
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9827981U Pending JPS585130U (en) | 1981-06-29 | 1981-06-29 | programmable logic controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS585130U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6082724U (en) * | 1983-11-15 | 1985-06-07 | 岩崎通信機株式会社 | Processor stop state detection and display device in magnetic printing device |
-
1981
- 1981-06-29 JP JP9827981U patent/JPS585130U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6082724U (en) * | 1983-11-15 | 1985-06-07 | 岩崎通信機株式会社 | Processor stop state detection and display device in magnetic printing device |
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