JPS58138148U

JPS58138148U - Microcomputer system monitoring device

Info

Publication number: JPS58138148U
Application number: JP3150782U
Authority: JP
Inventors: 森田　俊二
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1982-03-05
Filing date: 1982-03-05
Publication date: 1983-09-17
Also published as: JPS6343561Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来のマイクロコンピュータシステムの監視装
置を示すブロック図、第２図は本考案の一実施例による
監視装置を示すブロック図である。１・・・ＣＰＵ、　２・・・クロック発生回路、３・・
・メモリ、４・・・監視タイマ、５・・・表示制御回路
、６ａ〜６ｅ・・・表示ランプ、７ａ〜７ｄ・・・入出
力インターフェイス、８・・・クロック異常検出回路、
９・・・割込コントローラ、１０・・・ノーリプライ検
出回路、１１・・・バス異常検出回路。なお、図中、同
一符号は同一、又は相当部分を示す。FIG. 1 is a block diagram showing a conventional monitoring device for a microcomputer system, and FIG. 2 is a block diagram showing a monitoring device according to an embodiment of the present invention. 1...CPU, 2...Clock generation circuit, 3...
・Memory, 4... Monitoring timer, 5... Display control circuit, 6a to 6e... Display lamp, 7a to 7d... Input/output interface, 8... Clock abnormality detection circuit,
9... Interrupt controller, 10... No reply detection circuit, 11... Bus abnormality detection circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims

[Scope of utility model registration request]

(1) A CPU that inputs and outputs data information via various input/output interfaces based on clock pulses sent out from a clock generation circuit, and processes data while writing and reading data information to and from memory; The CP
The count is reset by a reset signal periodically sent from the CPU, the clock pulses from the clock generation circuit are counted, and when the count exceeds a predetermined value, a detection signal is sent out, and the CPU
a monitoring timer that sends a system reset control signal to the
a display control circuit that lights a run lamp for a period of continuous input of a normal operation signal from the CPU during normal operation of the CPU, and keeps the trouble lamp turned on when receiving the input of the trouble detection signal;
In a computer system monitoring device, a clock abnormality detection circuit detects an abnormality in a clock pulse of the clock generation circuit and sends a pulse abnormality signal to the display control circuit, and also sends a system reset control signal to the CPU; and a parity bit. a bus abnormality detection circuit that detects a system bus abnormality and sends a parity error signal using a bus abnormality detection circuit; and a bus abnormality detection circuit that detects a system bus abnormality using When receiving the parity error signal of the CP, it outputs an interrupt control signal and operates the interrupt controller.
A no-reply detection circuit is provided that causes the U to execute an interrupt processing program to generate a no-reply abnormal signal and sends the parity error signal to the display control circuit. The no-reply lamp is lit based on the no-reply error signal, the parity error lamp is lit based on the parity error signal, and the trouble lamp is also lit based on the clock error signal to identify each error cause. A monitoring device for a microcomputer system, characterized in that the system is configured to detect an abnormality externally every time the system resets, and does not reset the system except for the abnormality factor that generates the system reset control signal.

(2) The above-mentioned various input/output interfaces include a digital interface, an analog output interface, an analog input interface, and a peripheral device interface. Device.

(3) An analog/digital conversion abnormal lamp is provided as a lamp whose lighting is controlled by the display control circuit, and the lamp is turned on when an abnormality occurs in the analog/digital converter in the analog input interface. 2. A monitoring device for a microcomputer system according to item 2.