JPS5848926A - Insulated type semiconductor device - Google Patents
Insulated type semiconductor deviceInfo
- Publication number
- JPS5848926A JPS5848926A JP14615881A JP14615881A JPS5848926A JP S5848926 A JPS5848926 A JP S5848926A JP 14615881 A JP14615881 A JP 14615881A JP 14615881 A JP14615881 A JP 14615881A JP S5848926 A JPS5848926 A JP S5848926A
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- plate
- metal
- semiconductor device
- bonded
- solder
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は絶縁型半導体装置、特に#!−導俸基捧と、半
導体基体を載置する金属支持体との間が・電気的に絶縁
され、熱的に接続された半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated semiconductor device, particularly #! - A semiconductor device in which a conductive base and a metal support on which a semiconductor substrate is placed are electrically insulated and thermally connected.
半導体装置の一例である高出力トランジスタを複数個搭
載した混成集積回路装置では、数アンペア以上のフレフ
タ電流が流れるが、この際半導体素子としてのトランジ
スタペレットは通常発熱する。この発熱に起因する特性
の不安定性や寿命の加速的劣化を避けるためトランジス
タベレットが許容制限温度を越えて昇温するのを防止し
なければならない。又、混成集積回路装置に搭載される
回路素子、中でも半導体素子としてのトランジスタベレ
ットは他の回路素子と電気的に絶縁されなければならな
い場合が多い。さらに、高度な機能の要求される混成集
積回路装置では搭載された回路素子が外部からの影響、
特に電磁波妨害を受けないようにするための方策や、安
全上の見地から混成集積回路装置の搭載回路素子はその
収納容器から電気的にしゃ断されていなければならない
。In a hybrid integrated circuit device equipped with a plurality of high-output transistors, which is an example of a semiconductor device, a flefter current of several amperes or more flows, and at this time, the transistor pellet as a semiconductor element usually generates heat. In order to avoid instability of characteristics and accelerated deterioration of life due to this heat generation, it is necessary to prevent the temperature of the transistor bellet from rising beyond the allowable limit temperature. Further, in many cases, circuit elements mounted on a hybrid integrated circuit device, especially transistor pellets as semiconductor elements, must be electrically insulated from other circuit elements. Furthermore, in hybrid integrated circuit devices that require advanced functionality, the mounted circuit elements are subject to external influences.
In particular, from the standpoint of safety and prevention of electromagnetic interference, the mounted circuit elements of a hybrid integrated circuit device must be electrically isolated from its storage container.
このような要求を満すためには熱伝導性や電気絶縁性は
優れ、限られたスペースに所定の電気回路を構成する回
路素子を搭載できる絶縁板が必要になる。このような絶
縁板の一例として、第1図に示す断面図のように、ヒー
トシンクとしての役割を併せて担う銅の如き金属支持板
1上に鉛−錫系半田等からなる第1の金属ろう2を介し
て絶縁板3を接着し、この絶縁板3の他方の面上に鉛−
錫系半田等からなる第2の金属ろう4を介して銅板の如
き電極板5を接着した構造のものが知られており、混成
集積回路装置はさらに電極板5上に鉛−錫系半田等から
なる第3の金属ろうを介して半導体基体等の回路素子を
一体化し、所定の電気配線や封止処理を施して得ら扛る
。かかる構造の混成集積回路装置において、絶縁板3は
電気絶縁性に優れ併せて高い熱伝導性を兼ね備えている
ことが望ましく、この観点から無機質絶縁物、例えばア
ルミナ、ベリリヤが多用されている。しかしながら、ア
ルミナやベリリヤを除く無機質絶縁物、例えば窒化アル
ミニウム、窒化シリコンは体積抵抗率1014Ω・m以
上(室温)と極めて優れた電気絶縁性を有するとともに
、それぞれ熱伝導率0.2’1m/ぼ・C・s、o、o
3*/鍜・C・S(室温)と良好な熱伝導性を兼ね備え
ており、前述した半導体装置用絶縁板として好ましい性
質を持っている。にもかかわらず、これらの無機質絶縁
物が半導体装置に実用されることは殆んどなかった。こ
の理由は、アルミナやベリリヤに比べて低コスト、均質
かつ量産的に製造するための方法が十分て確立されてい
なかったことの他に、これらの無機質絶縁物と金属との
接着を信頼性高く実現すること、つまりこれら無機質絶
縁物表面に信頼性の高い金属化処理を施すことが極めて
困難であったことにもよる。In order to meet these requirements, an insulating board is required that has excellent thermal conductivity and electrical insulation, and can mount circuit elements constituting a predetermined electric circuit in a limited space. As an example of such an insulating plate, as shown in the cross-sectional view shown in FIG. An insulating plate 3 is bonded through the insulating plate 2, and a lead layer is placed on the other side of the insulating plate 3.
A structure in which an electrode plate 5 such as a copper plate is bonded via a second metal solder 4 made of tin-based solder or the like is known, and the hybrid integrated circuit device further has a structure in which an electrode plate 5 such as a copper plate is bonded via a second metal solder 4 made of tin-based solder or the like. A circuit element such as a semiconductor substrate is integrated through a third metal solder made of a metal solder, and then predetermined electrical wiring and sealing treatments are performed. In a hybrid integrated circuit device having such a structure, it is desirable that the insulating plate 3 has excellent electrical insulation and high thermal conductivity, and from this point of view, inorganic insulating materials such as alumina and beryllia are often used. However, inorganic insulators other than alumina and beryllia, such as aluminum nitride and silicon nitride, have extremely excellent electrical insulation properties with a volume resistivity of 1014 Ω·m or more (at room temperature), and thermal conductivity of 0.2'1 m/m or more, respectively.・C・s, o, o
It has good thermal conductivity of 3*/C/S (at room temperature), and has desirable properties as an insulating board for semiconductor devices as described above. Nevertheless, these inorganic insulators have rarely been put to practical use in semiconductor devices. The reason for this is that, compared to alumina and beryllia, there is a lack of well-established methods for producing homogeneous and mass-produced products at a lower cost than in comparison to alumina and beryllia. This is partly due to the fact that it has been extremely difficult to realize this, that is, to perform highly reliable metallization on the surfaces of these inorganic insulators.
本発明の目的は、前述した無機質絶縁物を用いて熱伝導
性に優れた絶縁型半導体装置を提供することにある。An object of the present invention is to provide an insulated semiconductor device with excellent thermal conductivity using the above-mentioned inorganic insulator.
この目的を達成する本発明の絶縁型半導体装置は、支持
部材により支持され、支持部材と反対の側で少なくとも
1つの主平面を有する無機質絶縁部材と、絶縁部材の主
平面上に金属ろうによシ接着された金属板と、金属板の
絶縁部材側と反対側の表面に導電的に接着された少なく
とも1つの半導体基体とを含む半導体装置であり、上記
絶縁部材が窒化アルミニウム、窒化硼素、窒化シリコン
の群から選択された1つを主成分とする物質であり、こ
の絶縁部材の少なくとも金・萬ろうにより金属板を接着
する領域の表面に、モリブデン及びタングステンを含む
粉末金属を還元性雰囲気下で焼結された金属層を含む金
属化領域を有することを特徴とする。An insulated semiconductor device of the present invention that achieves this object includes an inorganic insulating member that is supported by a supporting member and has at least one main plane on the side opposite to the supporting member, and a metal solder on the main plane of the insulating member. A semiconductor device comprising a metal plate bonded to a metal plate, and at least one semiconductor substrate conductively bonded to a surface of the metal plate opposite to an insulating member side, wherein the insulating member is made of aluminum nitride, boron nitride, nitride. It is a substance whose main component is one selected from the group of silicones, and a powdered metal containing molybdenum and tungsten is applied to the surface of the insulating member at least in the area where the metal plate is bonded using gold wax in a reducing atmosphere. characterized in that it has a metallized region comprising a metal layer sintered with.
本発明をさらに詳細に説明すると、前述した金属化領域
は、(1)無機質絶縁部材としての窒化アルミニウムや
窒化シリコンとの反応性に富み強固な接着性を有するモ
リブデン及びタングステン混合粉末を印刷法により塗布
し、この際混合粉末の塗布は揮発性有機溶媒といっしょ
に混練してペースト状になされた混合粉末ペーストを厚
さ約60μmに印刷して行なわれ、(2)混合粉末ペー
ストを塗布した無機質絶縁部材を還元性フォーミングガ
ス雰囲気(水素1:窒素10.容量比)中で1320C
(保持時間:20分間)に加熱して前述の混合粉末ペー
スト中の有機質を揮散させるとともに粉末金属どうしの
焼結と粉末金属と無機質絶縁物との反応を促進せしめ、
(3)無機質絶縁物に一体化された焼結金属上に無電解
ニッケルめっきを施して厚さ3〜5μmのニッケルめっ
き層を形成し、そしてニッケルめっき層を形成した無機
質絶縁物を水素の如き還元性雰囲気中で81CI’((
保持時間3〜5分間)して形成される。このようにして
金属化された無機質絶縁物の両面には、鉛−錫系半田の
一般的なるの付は法により銅板等の金属板と一体化され
る。一体化された金属板は一方が支持板としての役割を
担い、他方が半導体基体を搭載する導体板やヒートシン
ク板としての役割を担う。To explain the present invention in more detail, the above-mentioned metallized region is formed by (1) printing a molybdenum and tungsten mixed powder that is highly reactive and has strong adhesive properties with aluminum nitride and silicon nitride as inorganic insulating members; At this time, the mixed powder was applied by printing the mixed powder paste, which was made into a paste by kneading it together with a volatile organic solvent, to a thickness of about 60 μm. The insulating member was heated at 1320C in a reducing forming gas atmosphere (hydrogen 1:nitrogen 10.capacity ratio).
(Holding time: 20 minutes) to volatilize the organic matter in the above-mentioned mixed powder paste and promote sintering of the powdered metals and reaction between the powdered metals and the inorganic insulator,
(3) Electroless nickel plating is applied to the sintered metal integrated with the inorganic insulator to form a nickel plating layer with a thickness of 3 to 5 μm, and the inorganic insulator with the nickel plating layer is then 81CI'((
(holding time: 3 to 5 minutes). Both surfaces of the inorganic insulator metallized in this manner are integrated with a metal plate such as a copper plate by a general method of applying lead-tin solder. One of the integrated metal plates serves as a support plate, and the other serves as a conductor plate on which a semiconductor substrate is mounted and a heat sink plate.
以下、本発明を実施例によシさらに詳細に説明する。Hereinafter, the present invention will be explained in more detail using examples.
実施例1 本実施例では、絶縁型トランジスタについて説明する。Example 1 In this embodiment, an insulated transistor will be explained.
第2図は本J 彪夕11で得た絶縁型トランジスタの断
面図である。このトランジスタは無機質絶縁部材として
の窒化アルミニウム板11の両面に焼結して一体化した
モリブデン及びタングステンを含む金属層と同金属層上
にめっき形成したニッケル層とからなる積層金属層12
を配し、この窒化アルミニウム板11の一方の主面側に
導体板としての銅板13と半導体基体としてのシリコン
トランジスタペレット14を順次積層して鉛−錫系半田
15により導電的に接着し、他方の主面側に支持板とし
ての鋼板16を鉛−錫系半田17によシ接着した構造に
なっている。この際、トランジスタベレット14のエミ
ッタ及びベース領域をそれぞれ所定の金属端子にアルミ
ニウム細線を介して導電的に接続し、銅板を所定の金属
端子(コレクタ)に導電的に接続し、そしてトランジス
タベレット14、銅板13、窒化アルミニウム板11等
が完全に封止されるようにエポキシ樹脂でモールドして
いる。FIG. 2 is a cross-sectional view of the insulated transistor obtained in Book J Biaoyu 11. This transistor consists of a laminated metal layer 12 consisting of a metal layer containing molybdenum and tungsten sintered and integrated on both sides of an aluminum nitride plate 11 as an inorganic insulating member, and a nickel layer plated on the metal layer.
A copper plate 13 as a conductor plate and a silicon transistor pellet 14 as a semiconductor substrate are sequentially laminated on one main surface side of this aluminum nitride plate 11 and conductively bonded with lead-tin solder 15, and the other side is It has a structure in which a steel plate 16 serving as a support plate is bonded to the main surface side using lead-tin solder 17. At this time, the emitter and base regions of the transistor bellet 14 are conductively connected to predetermined metal terminals via thin aluminum wires, the copper plate is conductively connected to a predetermined metal terminal (collector), and the transistor bellet 14, The copper plate 13, aluminum nitride plate 11, etc. are molded with epoxy resin so that they are completely sealed.
以上の構成で得られた絶縁型トランジスタのベレット1
4から銅支持板16に至る間の熱抵抗は0.851T/
Wと良好な放熱性を示し、そして銅板13と銅支持板1
6間に交流実効値電圧2000V[50Hz)を連続し
て10時間印加したが絶縁破壊は生じなかった。又、得
られた絶縁型トランジスタに一55r(25分間)−室
温(5分間)−+150C(25分間)−室温(5分間
)の温度サイクルを2000回与えたが熱抵抗の変動は
認められなかった。このように、放熱性や絶縁性に優れ
そして耐温度サイクル性に優れた絶縁型トランジスタが
得られたのは、窒化アルミニウムに接着強度に優れる積
層金属層で金属化処理ができ、金属板との一体化が可能
になったことによる。Bellet 1 of the isolated transistor obtained with the above configuration
The thermal resistance from 4 to the copper support plate 16 is 0.851T/
W and exhibits good heat dissipation, and the copper plate 13 and the copper support plate 1
Although an AC effective value voltage of 2000 V [50 Hz] was continuously applied for 10 hours during 6 hours, no dielectric breakdown occurred. Furthermore, the obtained insulated transistor was subjected to a temperature cycle of 155R (25 minutes) - room temperature (5 minutes) - +150C (25 minutes) - room temperature (5 minutes) 2000 times, but no change in thermal resistance was observed. Ta. In this way, an isolated transistor with excellent heat dissipation, insulation properties, and temperature cycle resistance was obtained because aluminum nitride can be metallized with a laminated metal layer with excellent adhesive strength, and it can be bonded to a metal plate. This is due to the fact that integration has become possible.
実施例2
本実施例では、実施例1において無機質絶縁部材として
窒化シリコン板を用い、これら無機質絶縁部材に実施例
1と同様の積層金属層を設けて金属化し、実施例1と同
様の構造の絶縁型トランジスタを得た。Example 2 In this example, silicon nitride plates were used as the inorganic insulating members in Example 1, and these inorganic insulating members were metallized with a laminated metal layer similar to that in Example 1. An isolated transistor was obtained.
以上の構成で得られた絶縁型トランジスタの熱抵抗は1
.25r/Wと良好な放熱性を有しており、そして絶縁
性や耐温度サイクル性は実施例1とほぼ同等であった。The thermal resistance of the isolated transistor obtained with the above configuration is 1
.. It had good heat dissipation of 25 r/W, and its insulation properties and temperature cycle resistance were almost the same as in Example 1.
このように、放熱性や絶縁性に優れそして耐温度サイク
ル性に優れた絶縁型トランジスタが得られたのは、窒化
シリコンに接着強度に優れる積層金属、′―で金属化処
理できたため、金属板との一体化が可能になったことに
よる。In this way, an isolated transistor with excellent heat dissipation, insulation properties, and temperature cycle resistance was obtained because silicon nitride could be metallized with a laminated metal, which has excellent adhesive strength. This is because it has become possible to integrate with
実施例3
本実施例では10A級インバータの電流制御パワーモジ
ュールを例に採って説明する。Embodiment 3 In this embodiment, a current control power module for a 10A class inverter will be taken as an example.
このパワーモジュールは、第3図に示すように、底面に
ニッケルめっきを施した7 0mmX 140mmX3
.2mmのアルミニウム支持板21と、実施例1と同様
の積層金属層からなる金属化領域を両面に設けた25m
mX25聴X0.6mの窒化アルミニウム板221〜2
26、同じ(15mmX 15mmX016關の窒化ア
ルミニウム板227,228及び同じ< 16mmX
15mmX O,6rranの窒化アルミニウム板22
9と、そして表面にニッケルめっきを施した2 3mm
X 23mmX O,25rrr!nのアルミニウム載
置板231〜236、同じ(13wnx 13聰×0.
25咽のアルミニウム載置板’237,238及び同じ
(14mmX 13間X0.25mのアルミニウム載置
板239を順次鉛−錫系半田(図示せず)を介して一体
化し、アルミニウム載置板上に鉛−錫系半田(図示せず
)を介してトランジスタ、ダイオード、抵抗、双方向性
サイリスタを搭載して、第4図に示すような混成集積回
路を構成し、エポキシ樹脂からなる封止用ケース(図示
せず)で封止し、さらにケース内を絶縁性樹脂で充填し
てモジュールを得た。このモジュールは第4図に示す電
気回路を構成しているが、一点鎖線で表わした範囲の回
路素子はそれぞれ対応するアルミニウム載置板上に搭載
されている。As shown in Figure 3, this power module is 70 mm x 140 mm x 3 with nickel plating on the bottom.
.. A 25 m aluminum support plate 21 with a thickness of 2 mm and metallized regions made of laminated metal layers similar to those in Example 1 were provided on both sides.
m x 25 m x 0.6 m aluminum nitride plate 221-2
26, the same (15mmX 15mmX016 aluminum nitride plate 227, 228 and the same
15mm x O, 6rran aluminum nitride plate 22
9 and 2 3mm with nickel plating on the surface
X 23mmX O, 25rrr! n aluminum mounting plates 231 to 236, same (13wnx 13ts x 0.
Aluminum mounting plates 237 and 238 of 25mm diameter and the same (14mm x 13mm x 0.25m aluminum mounting plate 239) were successively integrated via lead-tin solder (not shown) and placed on the aluminum mounting plate. A hybrid integrated circuit as shown in Figure 4 is constructed by mounting transistors, diodes, resistors, and bidirectional thyristors via lead-tin solder (not shown), and a sealing case made of epoxy resin. (not shown) and further filled the inside of the case with insulating resin to obtain a module.This module constitutes the electric circuit shown in Fig. 4, and the area indicated by the dashed line Each circuit element is mounted on a corresponding aluminum mounting plate.
以上の構成で得たモジュールのトランジスタ。Transistor of the module obtained with the above configuration.
ダイオード、双方向性サイリスタの各ペレットとアルミ
ニウム支持板との間の熱抵抗0.6′C/W以下であり
、実用上支障のない優れた放熱性を有していることが確
認された。又、同モジュールに実施例1と同様の温度サ
イクルを50回与えたが、熱抵抗の変動は認められなか
った。さらにアルミニウム載置板とアルミニウム支持板
間に実施例1と同様の交流岨圧を10時間印加したが、
絶縁破壊は認められなかった。以上のように放熱性が良
いため発熱の著しいパワー素子を多数収納でき、この結
果パワー回路を小型化することが可能になった。It was confirmed that the thermal resistance between each pellet of the diode and bidirectional thyristor and the aluminum support plate was 0.6'C/W or less, and that it had excellent heat dissipation properties that would not cause any practical problems. Further, the same module was subjected to 50 temperature cycles similar to those in Example 1, but no change in thermal resistance was observed. Furthermore, the same AC pressure as in Example 1 was applied between the aluminum mounting plate and the aluminum support plate for 10 hours.
No dielectric breakdown was observed. As described above, since the heat dissipation is good, a large number of power elements that generate significant heat can be accommodated, and as a result, it has become possible to downsize the power circuit.
以上説明したように、本発明によれば窒化アルミニウム
、窒化シリコンからなる無機質絶縁板を用いて熱伝導性
に優れた絶縁型半導体装置を得ることができる。これは
、従来極めて困難であった窒化アルミニウムや窒化シリ
コンに金属化できたこと、即ち接着強度に優れ、半田等
の金属ろうによる接着が可能な焼結モリブデン及びタン
グステンを含む積層金属;・謔で無機質絶縁板を金属化
できたため、金属板等との一体化が可能になったことに
よる。又、本発明によれば、無機質絶縁板の金属化処理
には一般的な印刷、焼付けによる金属化の手法を用いる
ことが可能であり、金属化した無機質絶縁板は通常の金
属ろうによるリフロー処理で金属板と一体化することが
できるため、半導体装置の製作が容易である。As explained above, according to the present invention, an insulated semiconductor device with excellent thermal conductivity can be obtained using an inorganic insulating plate made of aluminum nitride or silicon nitride. This is because it has been possible to metallize aluminum nitride and silicon nitride, which has been extremely difficult in the past.In other words, it is a laminated metal containing sintered molybdenum and tungsten that has excellent adhesive strength and can be bonded with metal solder such as solder. This is because the inorganic insulating plate can be made into a metal, making it possible to integrate it with a metal plate, etc. Further, according to the present invention, it is possible to use general printing and baking metallization methods for metallizing the inorganic insulating plate, and the metallized inorganic insulating plate can be subjected to reflow treatment using ordinary metal soldering. Since it can be integrated with a metal plate, it is easy to manufacture semiconductor devices.
なお、本発明において半導体基体を載置する金属板は半
導体装置の主要な導電路を担うものであって、金属ろう
のみで導電路を確保できる場合は金属板を除いても本発
明の目的を達成できる。In addition, in the present invention, the metal plate on which the semiconductor substrate is placed plays a main conductive path of the semiconductor device, and if the conductive path can be secured only with metal solder, the purpose of the present invention can be achieved even if the metal plate is omitted. It can be achieved.
第1図は従来の絶縁型半導体装置の断面図、第2図は本
発明を適用した絶縁型トランジスタの断面図、第3図は
本発明を適用したパワーモジュールの斜視図、第4図は
第3図のパワーモジュールの電気回路である。
11・・・窒化アルミニウム板、12・・・積智金属層
、13・・・銅板、14・・・シリコントランジスタベ
レン第 1 図
第 3 図
第 4 V
236 23η 232FIG. 1 is a sectional view of a conventional insulated semiconductor device, FIG. 2 is a sectional view of an insulated transistor to which the present invention is applied, FIG. 3 is a perspective view of a power module to which the present invention is applied, and FIG. 4 is a sectional view of a conventional insulated semiconductor device. This is an electrical circuit of the power module shown in Figure 3. DESCRIPTION OF SYMBOLS 11... Aluminum nitride plate, 12... Sekichi metal layer, 13... Copper plate, 14... Silicon transistor Belen Figure 1 Figure 3 Figure 4 V 236 23η 232
Claims (1)
で少なくとも1つの主平面を有する無機質絶縁部材と、
この絶縁部材の上記主平面上に金属ろうにより接着され
た金属板と、この金属板の上記絶縁部材側と反対側の表
面に導電的に接着された少なくとも1つの半導体基体と
を具備し、上記絶縁部材が窒化アルミニウム、窒化シリ
コンの群から選択された1つを主成分とする物質であり
、この絶縁部材の少なくとも金属ろうにより金属板を接
着する領域の表面に、モリブデン及o:pンyステンを
含む粉末金属を還元性雰囲気下で焼結された金属層を含
む金属化領域を有することを特徴とする絶縁型半導体装
置。 2、特許請求の範囲第1項において、半導体基体が金属
ろうを介して前記金属化領域に導電的に接着されたこと
を特徴とする絶縁型半導体装置。[Claims] 1. An inorganic insulating member supported by a support member and having at least one main plane on the opposite side of the support member side 2;
A metal plate bonded to the main plane of the insulating member by a metal solder, and at least one semiconductor substrate conductively bonded to a surface of the metal plate opposite to the insulating member side, The insulating member is made of a substance whose main component is one selected from the group of aluminum nitride and silicon nitride, and molybdenum and O:PNY are applied to at least the surface of the insulating member in the area where the metal plate is bonded by metal solder. An insulated semiconductor device comprising a metallized region including a metal layer formed by sintering powdered metal containing stainless steel in a reducing atmosphere. 2. An insulated semiconductor device according to claim 1, wherein the semiconductor substrate is electrically conductively bonded to the metallized region via a metal solder.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14615881A JPS5848926A (en) | 1981-09-18 | 1981-09-18 | Insulated type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14615881A JPS5848926A (en) | 1981-09-18 | 1981-09-18 | Insulated type semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5848926A true JPS5848926A (en) | 1983-03-23 |
JPS6326542B2 JPS6326542B2 (en) | 1988-05-30 |
Family
ID=15401437
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14615881A Granted JPS5848926A (en) | 1981-09-18 | 1981-09-18 | Insulated type semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5848926A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6032343A (en) * | 1983-08-02 | 1985-02-19 | Toshiba Corp | Power semiconductor module substrate |
EP0235682A2 (en) * | 1986-02-20 | 1987-09-09 | Kabushiki Kaisha Toshiba | Aluminium nitride sintered body having conductive metallized layer |
JPS62219546A (en) * | 1986-03-19 | 1987-09-26 | Toshiba Corp | Semiconductor device |
JPH01185928A (en) * | 1988-01-21 | 1989-07-25 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
US4965659A (en) * | 1987-06-30 | 1990-10-23 | Sumitomo Electric Industries, Ltd. | Member for a semiconductor structure |
US5138439A (en) * | 1989-04-04 | 1992-08-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
JP2000086368A (en) * | 1998-09-16 | 2000-03-28 | Fuji Electric Co Ltd | Nitride ceramic substrate |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53102310A (en) * | 1977-02-18 | 1978-09-06 | Tokyo Shibaura Electric Co | Heat conducting base plates |
JPS5551774A (en) * | 1978-10-06 | 1980-04-15 | Kyoto Ceramic | Composition and method for metallizing nonnoxide ceramic body |
-
1981
- 1981-09-18 JP JP14615881A patent/JPS5848926A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53102310A (en) * | 1977-02-18 | 1978-09-06 | Tokyo Shibaura Electric Co | Heat conducting base plates |
JPS5551774A (en) * | 1978-10-06 | 1980-04-15 | Kyoto Ceramic | Composition and method for metallizing nonnoxide ceramic body |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6032343A (en) * | 1983-08-02 | 1985-02-19 | Toshiba Corp | Power semiconductor module substrate |
JPH0586662B2 (en) * | 1983-08-02 | 1993-12-13 | Tokyo Shibaura Electric Co | |
EP0235682A2 (en) * | 1986-02-20 | 1987-09-09 | Kabushiki Kaisha Toshiba | Aluminium nitride sintered body having conductive metallized layer |
JPS62219546A (en) * | 1986-03-19 | 1987-09-26 | Toshiba Corp | Semiconductor device |
US4965659A (en) * | 1987-06-30 | 1990-10-23 | Sumitomo Electric Industries, Ltd. | Member for a semiconductor structure |
JPH01185928A (en) * | 1988-01-21 | 1989-07-25 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
US5138439A (en) * | 1989-04-04 | 1992-08-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
JP2000086368A (en) * | 1998-09-16 | 2000-03-28 | Fuji Electric Co Ltd | Nitride ceramic substrate |
Also Published As
Publication number | Publication date |
---|---|
JPS6326542B2 (en) | 1988-05-30 |
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