JPS5846850B2 - Size selection method - Google Patents
Size selection methodInfo
- Publication number
- JPS5846850B2 JPS5846850B2 JP4289577A JP4289577A JPS5846850B2 JP S5846850 B2 JPS5846850 B2 JP S5846850B2 JP 4289577 A JP4289577 A JP 4289577A JP 4289577 A JP4289577 A JP 4289577A JP S5846850 B2 JPS5846850 B2 JP S5846850B2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- main pattern
- monitor
- workpiece
- metal electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010187 selection method Methods 0.000 title claims description 3
- 239000002184 metal Substances 0.000 description 15
- 230000004888 barrier function Effects 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 12
- 239000013078 crystal Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Landscapes
- Length Measuring Devices By Optical Means (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Weting (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
【発明の詳細な説明】
この発明は寸法選別方法に係り、特に写真製版技術によ
って形成されたパターンの仕上り寸法の選別方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a size selection method, and more particularly to a method for selecting finished dimensions of a pattern formed by photolithography.
以下、半導体装置、殊に接合形素子であるショットキー
・バリヤ・ダイオードの製造を例にとって説明する。The following will explain the manufacture of a semiconductor device, particularly a Schottky barrier diode, which is a junction type device, as an example.
ショットキー・バリヤ・ダイオードは半導体結晶と金属
電極とが接触した構造を有しており、第1図はその一例
を示す断面図である。A Schottky barrier diode has a structure in which a semiconductor crystal and a metal electrode are in contact with each other, and FIG. 1 is a cross-sectional view showing an example thereof.
図において、1は半導体結晶、2ばその一生面上に形成
された直径りの円形金属電極、3は絶縁性表面保護膜、
4は半導体結晶の他の主面へのオーミックコンタクト、
5は半導体結晶1と金属電極2との界面であり、この界
面5にショットキー・・・バリヤが形成される。In the figure, 1 is a semiconductor crystal, 2 is a circular metal electrode with a diameter formed on the entire surface of the crystal, 3 is an insulating surface protection film,
4 is an ohmic contact to the other main surface of the semiconductor crystal;
5 is an interface between the semiconductor crystal 1 and the metal electrode 2, and a Schottky barrier is formed at this interface 5.
ショットキー・・・バリヤの最も重要た電気特性は零バ
イアス時のバリヤ容量(Cjo)であり、その値は次式
で与えられる。Schottky... The most important electrical property of the barrier is the barrier capacitance (Cjo) at zero bias, and its value is given by the following equation.
とkで、qは電子の電荷量、ε8は半導体結晶1の誘電
率、凡は半導体結晶1のキャリア濃度、vbiはビルト
イン電圧、kはボルツマン定数、Tは絶対温度、Dは金
属電極2の直径である。and k, q is the electron charge, ε8 is the permittivity of the semiconductor crystal 1, approximately is the carrier concentration of the semiconductor crystal 1, vbi is the built-in voltage, k is Boltzmann's constant, T is the absolute temperature, and D is the metal electrode 2. It is the diameter.
近年、半導体結晶成長技術の向上にともない、このよう
た素子を数多く形成する半導体基板内におけるキャリア
濃度N。In recent years, with the improvement of semiconductor crystal growth technology, the carrier concentration N in the semiconductor substrate on which many such elements are formed has increased.
の不均一は極めて小さくなっているので、バリヤ容量C
joの不均一性は金属電極2の直径りの不均一性に専ら
依存するといえる。Since the non-uniformity of is extremely small, the barrier capacitance C
It can be said that the non-uniformity of jo depends exclusively on the non-uniformity of the diameter of the metal electrode 2.
一例として、キャリア濃度N。As an example, carrier concentration N.
”−2X1.OonのGaAs結晶基板を用いた場合、
D=10μのとき Cjo=0.11 pF’D=12
μのとき C,=0.16pF
O
であり、直径りが2μ異たるだけでバリヤ容量Cjoは
約45係も変化する。When using a GaAs crystal substrate of ”-2×1.Oon, when D=10μ, Cjo=0.11 pF'D=12
When μ, C,=0.16 pF O , and a difference in diameter of only 2 μ changes the barrier capacitance Cjo by a factor of about 45.
バリヤ容量Cj。O値は通常10〜20%の偏差内にな
げればならないので、金属電極2の直径りは1μ以下の
精度におさえねばならない。Barrier capacity Cj. Since the O value must normally be within a deviation of 10 to 20%, the diameter of the metal electrode 2 must be kept within an accuracy of 1 μm or less.
ところが、半導体基板上にこのような精度で金属電極2
を基板全面にわたつて形成することは、写真製版工程、
エツチング工程などにおける不均一性を考慮すると極め
て困難である。However, the metal electrode 2 cannot be placed on the semiconductor substrate with such precision.
Forming it over the entire surface of the substrate is a photolithography process,
This is extremely difficult considering the non-uniformity in the etching process.
従って、所定範囲のバリヤ容量Cjoの素子を選別しよ
うと思えば、全素子についてバリヤ容量Cjoを測定す
るか、もしくは金属電極2の径を測定せねばならなかっ
た。Therefore, in order to select devices with barrier capacitance Cjo within a predetermined range, it is necessary to measure the barrier capacitance Cjo of all the devices or measure the diameter of the metal electrode 2.
これは非常に手数のかかる作業であった。This was a very time-consuming task.
この発明は上記従来の方法の欠点に鑑みてなされたもの
で、各素子毎にモニターパターンを金属電極2と同時に
形成するようにして、出来上った素子について、このモ
ニターパターンの形成具合の目視によって金属電極2の
直径りを類推し分類し得る方法を提供せんとするもので
ある。This invention has been made in view of the above-mentioned drawbacks of the conventional method, and involves forming a monitor pattern on each element at the same time as the metal electrode 2, and visual inspection of the formation of the monitor pattern on the completed element. The present invention aims to provide a method for classifying the diameter of the metal electrode 2 by analogy.
第2図はこの発明の一実施例を示すパターン図で、6は
金属電極形成用の主パターン、7はモニタパターンであ
る。FIG. 2 is a pattern diagram showing an embodiment of the present invention, in which 6 is a main pattern for forming metal electrodes, and 7 is a monitor pattern.
ショットキー・バリヤ・ダイオードの製造のための写真
製版工程では、通常耐薬品性、密着力などを考慮して、
米国
Phi l ip A−Hunt Chemica1社
製WAYCOATICRESIST東京応化工業社製O
MRなどのネガ形のフォトレジスト材が田いられる。In the photolithography process for manufacturing Schottky barrier diodes, chemical resistance, adhesion, etc. are usually taken into consideration.
WAYCOATIC RESIST made by Phil ip A-Hunt Chemica 1 in the U.S. O made by Tokyo Ohka Kogyo Co., Ltd.
Negative photoresist materials such as MR are used.
これらのレジスト材を用いて膜厚が0.5〜1.0μの
絶縁性表面保護膜3を微細加工する場合は、1.5〜2
μのパターンが限度であることは周知の実験的経験であ
る。When microfabricating the insulating surface protection film 3 with a film thickness of 0.5 to 1.0μ using these resist materials,
It is well known experimental experience that the pattern of μ is the limit.
そこで、各ショットキー・バリヤ・ダイオードを形成す
るチップ毎に第2図に示すように、直形が2μ、3μ、
4μ・・・・・・・・・のドツトパターン列からなるモ
ニターパターン7を、例えば直径12μの金属電極2用
の主パターン6と同時に形成させるようにしておく。Therefore, as shown in Figure 2, for each chip forming each Schottky barrier diode, the straight shape is 2μ, 3μ,
A monitor pattern 7 consisting of a dot pattern row of 4 μm, etc. is formed at the same time as the main pattern 6 for the metal electrode 2, for example, having a diameter of 12 μm.
このようにして出来上ったモニターパターン7を目視し
て、伺μのドツトパターンまでが形成されているかを見
るだけで、主パターン6の出来上り寸法を1μ以内の精
度で推定することができる。The finished dimensions of the main pattern 6 can be estimated with an accuracy of within 1 .mu. by simply visually observing the thus-formed monitor pattern 7 and seeing whether a dot pattern up to .mu. is formed.
これは1チツプの大きさが250〜1000μ角であり
、この範囲ではパターンの加工精度は均一と考えられる
からである。This is because the size of one chip is 250 to 1000 μm square, and the processing accuracy of the pattern is considered to be uniform within this range.
このような方法で8μ以上の径の主パターンについて上
述の1μの精度での出来上り寸法の推定が可能である。With this method, it is possible to estimate the finished size of a main pattern having a diameter of 8μ or more with an accuracy of 1μ as described above.
すなわち、例えば、モニターパターン704種類のドツ
トパターンがいずれも形成されていれば主パターン6は
所望通り直径12μに仕上っており、モニターパターン
7の内の2μのドツトが消滅しておれば主パターン6の
仕上り寸法は例えば10μであるというように予め、モ
ニターパターン7の形成状況と主パターンの仕上り寸法
との対応を測定しておけば、それから後はモニターパタ
ーン7の形成状況の目視だけで主パターン6の寸法選別
ができる。That is, for example, if all of the four types of dot patterns in the monitor pattern 70 are formed, the main pattern 6 has a diameter of 12 μm as desired, and if 2 μm of dots in the monitor pattern 7 have disappeared, the main pattern 6 If you measure in advance the correspondence between the formation status of the monitor pattern 7 and the finished size of the main pattern, for example, the finished size of the monitor pattern 7 is 10μ, then the main pattern can be determined simply by visually observing the formation status of the monitor pattern 7. 6 size selections are possible.
第2図のように1つのテップに主パターン6が1個のみ
の場合には、上述のようにモニターパターン7によって
選別はできるが、所望仕上り寸法の主パターン6を有す
るチップを数多く要求される場合には、更に数多くのテ
ップを製作してその中から選び出さねばならず、製品歩
留りの点ヤ用題がある。When there is only one main pattern 6 in one step as shown in FIG. 2, it is possible to sort by the monitor pattern 7 as described above, but a large number of chips having the main pattern 6 with the desired finished dimensions are required. In some cases, a larger number of steps must be manufactured and selected from among them, which poses problems in terms of product yield.
第3図はこの点を考慮して開発された先行技術のものに
この発明を適用した他の実施例を示すパターン図で、主
パターン6が直径12μを中心にして直径が15μ、1
4μ、13μ、12μ。FIG. 3 is a pattern diagram showing another embodiment in which the present invention is applied to the prior art developed with this point in mind.
4μ, 13μ, 12μ.
10μ、9μ、8μの8種類設けられており、この内の
いずれか一つが所望の仕上′り寸法12μになることが
期待される。Eight types are provided, 10μ, 9μ, and 8μ, and it is expected that any one of these will have the desired finished size of 12μ.
そこで、第2図の実症例の場合ト同様のモニターパター
ン7を各チップ毎に設け、このモニターパターン7の形
成状況を目視し、これによって上述の8種類の主パター
ン6の内のどれが所望寸法に最も近いかを判定して、そ
れを実際に使用するようにできることは容易に理解でき
よう。Therefore, a monitor pattern 7 similar to that shown in the case of the actual case shown in FIG. 2 is provided for each chip, and the formation status of this monitor pattern 7 is visually observed. It is easy to see that it is possible to determine which dimension is closest and use it in practice.
なお、モニターパターンの形状、寸法、更にはドツト状
の残しパターンとするか、穴あき状のヌキパターンにす
るかなどは絶縁性表面保護膜の種類、膜厚、写真製版条
件、パターン形成後のエツチング条件などによって適宜
決定すべきであるが、最小のパターンは被加工物の微細
加工限界値程度にすることが必要である。The shape and dimensions of the monitor pattern, as well as whether it will be a dot-like pattern or a hole-like open pattern, will depend on the type and thickness of the insulating surface protective film, the photolithography conditions, and the post-pattern formation process. Although it should be determined appropriately depending on the etching conditions, etc., the minimum pattern needs to be approximately the microfabrication limit value of the workpiece.
以上、ショットキー・バリヤ・ダイオードの金属電極形
成のための絶縁性表面保護膜の加工を例にとって説明し
たが、その他の半導体装置の製造工程もしくは金属膜な
どの加工工程における加工精度のチェックに適用できる
ものである。The above explanation took the example of processing an insulating surface protection film for forming a metal electrode of a Schottky barrier diode, but it can also be applied to checking processing accuracy in the manufacturing process of other semiconductor devices or the processing process of metal films, etc. It is possible.
以上詳述したように、この発明では被加工物に所定寸法
精度の主パターンを加工形成するに際して、上記被加工
物の加工糖、度限界値に相当する寸法を最小寸法とし順
次所定寸法差を有する複数個のモニターパターンを上記
被加工物の主パターン形成部位に近接して同時に加工形
成するので、このモニターパターンの形成状態を目視す
るだけで、十分精度よ〈主パターンの仕上り寸法を判定
選別でき、数多くの寸法測定などの繁雑な手順を省くこ
とができる。As described in detail above, in this invention, when processing and forming a main pattern with predetermined dimensional accuracy on a workpiece, the minimum dimension is the dimension corresponding to the degree limit value of the processed sugar of the workpiece, and the predetermined dimensional difference is sequentially adjusted. Since a plurality of monitor patterns are simultaneously processed and formed in close proximity to the main pattern forming area of the workpiece, just visually observing the formation status of these monitor patterns is enough to ensure sufficient accuracy. This eliminates complicated procedures such as numerous dimensional measurements.
第1図はこの発明の説明に用いたショットキー・バリヤ
・ダイオードの構造を示す断面図、第2図はこの発明の
一実施例を示すパターン図、第3図はこの発明の他の実
施例を示すパターン図である。
図において、1は半導体結晶、2は金属電極、3は絶縁
性表面保護膜、6は主パターン、7はモニターパターン
である。
なお、図中同一符号は同一もしくは相当部分を示す。FIG. 1 is a cross-sectional view showing the structure of a Schottky barrier diode used to explain this invention, FIG. 2 is a pattern diagram showing one embodiment of this invention, and FIG. 3 is another embodiment of this invention. FIG. In the figure, 1 is a semiconductor crystal, 2 is a metal electrode, 3 is an insulating surface protective film, 6 is a main pattern, and 7 is a monitor pattern. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
るに際して、上記被加工物の加工精度限界値に相当する
寸法を最小寸法とし順次所定寸法差を有する複数個のモ
ニターパターンを上記被加工物の主パターン形成都立に
近接して同時に加工形成し、上記モニターパターンの形
成状態を目視して上記主パターンの形成寸法を判定選別
することを特徴とする寸法選別方法。1. When processing and forming a main pattern with a predetermined dimensional accuracy on a workpiece, a plurality of monitor patterns having a predetermined dimensional difference are sequentially formed on the workpiece, with the minimum dimension corresponding to the processing accuracy limit value of the workpiece. A size selection method characterized in that the main pattern is processed and formed at the same time in close proximity to the main pattern forming station, and the formed size of the main pattern is determined and selected by visually observing the formed state of the monitor pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4289577A JPS5846850B2 (en) | 1977-04-13 | 1977-04-13 | Size selection method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4289577A JPS5846850B2 (en) | 1977-04-13 | 1977-04-13 | Size selection method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS53127268A JPS53127268A (en) | 1978-11-07 |
JPS5846850B2 true JPS5846850B2 (en) | 1983-10-19 |
Family
ID=12648758
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4289577A Expired JPS5846850B2 (en) | 1977-04-13 | 1977-04-13 | Size selection method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5846850B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5646534A (en) * | 1979-09-25 | 1981-04-27 | Nec Home Electronics Ltd | Manufacture of semiconductor device |
JPS56165320A (en) * | 1980-05-23 | 1981-12-18 | Sanyo Electric Co Ltd | Formation of multilayer electrodes of semiconductor device |
-
1977
- 1977-04-13 JP JP4289577A patent/JPS5846850B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS53127268A (en) | 1978-11-07 |
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