JPS5844221B2 - Test method for field effect semiconductor devices - Google Patents

Description

[Detailed description of the invention] The non-invention is a field effect semiconductor device (hereinafter referred to as FET)
This invention relates to a method suitable for testing the lifespan and characteristics of a material by passing a direct current through it.

In general, FETs are designed to be used in a so-called source grounded state where the source terminal is a common terminal, as shown in FIG.

Therefore, even in a test that only applies a DC bias, such as a DC current life test, the source terminal of the n-channel type is at a negative potential and the drain terminal is at a positive potential, and the source terminal of the n-channel type is at a negative potential. A DC voltage is applied between the source terminal and the drain terminal so that the potential is positive and the drain terminal is negative, and a bias is applied using a so-called source common circuit that applies DC voltage between the gate terminal and the source terminal. .

By the way, in recent years, M using gallium arsenide (GaAs) has been developed.
ES (metal semiconductor) FET is F for high frequency.
Although it is attracting attention as an ET, this type of FET has a significantly high high frequency gain, so it is not suitable for low frequency FETs.
Compared to this, the unstable region regarding input/output impedance is expanded, and therefore, in the above-mentioned tests, oscillations often occur just by applying a DC bias.

In order to prevent such oscillations, it is necessary to adjust the input/output impedance so that it does not fall into an unstable region over a wide frequency range from low frequencies to high frequencies.

However, it is extremely difficult to adjust the input/output impedance in the above-mentioned test.

That is, in that case, since an impedance adjustment circuit is required for each element, the impedance adjustment circuit becomes enormous in the above-mentioned test in which a large number of elements are usually handled at once.

Further, if one element oscillates, there is a high possibility that other elements using the same power source will also oscillate.

The present invention is based on GaAs MES with large high frequency gain.
- Even with FETs, oscillation is suppressed without requiring an input/output impedance adjustment circuit, and the above-mentioned DC current test can be performed in an extremely stable state.This will be explained in detail below. .

The present invention is based on the knowledge that the operating principle remains the same whether the FET is connected to a so-called source grounded FET, in which the source terminal is a common terminal, or to a so-called drain grounded FET, in which the drain terminal is a common terminal. There is.

Now, the GaAs-MES-FET can be expressed as an equal circuit as shown in FIG.

In Figure 2, S is the source terminal, D is the drain terminal,
G is a gate terminal, C1 to C5 are capacitors, and L.

~L3 indicates the inductance of the internal lead, respectively.

Note that C3 to G5 are capacitances between terminals of the package.

Such FETs are designed in a conventional manner in order to improve the high frequency gain in the common source circuit.

. That is, the input and output capacitances C2 and C5 and the inductance L1 leading to the ground terminal S are made as small as possible.

In the present invention, when conducting a DC current test, as shown in FIG.
Ground the drain terminal of the FET as a common terminal, and
The gain is reduced and oscillation is prevented without changing the operating principle of the ET.

That is, in the circuit shown in Figure 2, the drain terminal is grounded as a common terminal, and in the n-channel type, the source terminal S is grounded.
Apply a DC voltage between the source terminal S and the drain terminal so that the terminal S is at a positive potential, the drain terminal is at a negative potential, and in the case of a p-channel type, the source terminal S is at a negative potential and the drain terminal is at a positive potential. At the same time, a test is performed by applying a DC voltage between the gate terminal G and the drain terminal.

In this case, the capacitance C3 and C
1 will be entered, and its value is 10 in the case of a common source.
reach more than double.

Furthermore, since the inductance at the grounded terminal is L2, it is larger than in the case of the source being grounded.

As a result of these, the high frequency gain is significantly reduced, the unstable region in the input/output impedance is narrowed, and oscillation is prevented.

As can be seen from the above explanation, according to the present invention, when testing an FET, by simply changing the method of applying DC bias, the high frequency gain can be reduced without any effect on the operating principle of the FET. , it is possible to prevent oscillation, so it is possible to use a large number of FETs at once without applying it to a circuit that is precisely controlled like an actual circuit, or without adding an input/output impedance adjustment circuit. tests can be conducted.

[Brief explanation of the drawing]

Figure 1 shows a conventional bias circuit for an n-channel FET with its source grounded, Figure 2 shows other circuit diagrams of the FET, and Figure 3 shows a bias circuit for an n-channel FET according to the present invention with its drain connected to ground. respectively represent the bias circuits. In the figure, S represents a source terminal, D represents a drain terminal, G represents a gate terminal, C1 to C3 represent capacitance, and L1 to L3 represent inductance.

Claims (1)

[Claims] 1 The drain terminal of a field-effect semiconductor device is a common terminal, and for an n-channel type, the source terminal is at a positive potential and the drain terminal is at a negative potential; for an n-channel type, the source terminal is at a negative potential and the drain terminal is at a positive potential. Apply direct current between the source and drain terminals so that the voltage is
A method for testing a field-effect semiconductor device□, characterized by applying a DC voltage between a gate terminal and a drain terminal to test the DC current life, characteristics, etc.