CN114006610A - Stabilizing circuit of frequency compensation circuit with self-adaptive load change - Google Patents
Stabilizing circuit of frequency compensation circuit with self-adaptive load change Download PDFInfo
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Abstract
The invention discloses a stabilizing circuit of a frequency compensation circuit with self-adaptive load change, which comprises a first-stage amplification circuit, a second-stage amplification circuit, a frequency compensation circuit with self-adaptive load change and an output-stage circuit, wherein the frequency compensation circuit consists of a compensation capacitor C1, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8 and a ninth MOS transistor M9; the output of the first-stage amplifying circuit is connected with the input of the second-stage circuit, the output of the second-stage circuit is connected with the output-stage circuit, and the frequency compensation circuit adaptive to load change is connected between the input and the output of the second stage. The advantages are that: compared with the fixed resistor as pole zero compensation, the MOS tube is used as an adjustable resistor, and a proper adjustment relation is established between the MOS tube and the load current, so that the pole zero frequency can be automatically adjusted when the load current changes; the system can stably work under different load current conditions, and the precondition of higher current capacity is also provided.
Description
Technical Field
The invention relates to the technical field of chip design, in particular to a stabilizing circuit with a frequency compensation circuit adaptive to load change for a floating-point multiply-add device.
Background
Negative feedback is widely used in analog signal processing because the nature of the feedback enables the system to operate accurately by suppressing variations in open loop performance. A negative feedback system is shown in figure 1.
A feedback system is provided that: (1) at the frequency III, the phase shift around the loop can be so large that negative feedback becomes positive feedback; (2) the loop gain is sufficient for the signal to settle (i.e., the loop gain ≧ 1), and both of these conditions will cause oscillation at frequency III. Therefore, to avoid instability, the total phase shift must be minimized so that the angle β H is still more positive than-180 ° when the loop gain magnitude = 1. As shown in fig. 2 and 3, bode plots for the stable system versus the unstable system.
A system open loop transfer function in the S domain is unstable if there is a pole in the right half-plane. If only the left half-plane poles and zeros are present, then the stability needs to be further analyzed in the bode plot.
In the Bott diagram, the gain curve will drop according to the slope of-20 dB/10 octave through a polar point; going through a zero point will rise with a slope of +20dB/10 octave. The phase curve begins to decrease at a frequency of 0.1, III p, completing a-90 phase change at a frequency of 10 III p. When passing through one zero point, if the zero point is the left half-plane zero point, then the rising starts at 0.1, and the +90 ° phase change is completed at the frequency of 10, z. When passing through a right half plane zero point, the phase curve of the phase change device descends according to a minus 45-degree slope, and finally the minus 90-degree phase change is completed.
For the feedback system in the linear voltage regulating circuit structure of fig. 4, the conventional frequency compensation method is to perform stability compensation on the feedback system by connecting a resistor-capacitor structure (C1, R1) as pole zero compensation in series between the output of the first-stage operational amplifier and the ground.
Without pole zero compensation, a simple analysis shows that the pole P1 of the output stage is set as the dominant pole, i.e., the pole with the lowest frequency, due to the large load capacitance. The first stage amplifier circuit has a large gain, i.e., a large transconductance, and therefore the pole P2 of the first stage amplifier circuit is set to be the second lowest frequency pole. The rest poles are very high in frequency and have no influence on the stability of the system, and are neglected here. The dominant and the secondary poles will always together cause a phase shift of-180. And since the two poles are low in frequency and close in frequency, this results in a phase shift of-180 ° within a narrow frequency range, which results in system instability. The gain curve at this time is shown in fig. 5.
When C1 and R1 are used for pole zero compensation, a new pole P and a new zero Z of the left half-plane are introduced by C1 and R1 and are between P1 and P2. The gain curve at this time is as shown in fig. 6. Analysis shows that the gain can be reduced to 0dB more quickly, and although the bandwidth is reduced, the system stability is better.
The above techniques can compensate for circuit pole zeros, but the system can become unstable when the load changes. As the load current increases, the transconductance of the power tube increases due to the increase of the load current according to the pole frequency of P1, and P1 moves to a higher frequency direction; however, the compensation pole zero does not move when the load current changes. This results in the pole zero compensation pair not being able to compensate effectively. The gain can only be reduced to 0dB at higher frequencies, eventually showing that the circuit becomes unstable as the load current varies.
Disclosure of Invention
The invention mainly solves the problems that the pole moves due to the change of load current, but the compensation pole zero can not move along with the change of the load current, so that the pole zero pair can not be effectively compensated, the stability of the system is reduced, the load carrying capacity of the system is limited, and the like.
The invention provides a stabilizing circuit with a frequency compensation circuit adaptive to load change, which adopts the technical scheme that:
a stabilizing circuit with a frequency compensation circuit adaptive to load change comprises a first-stage amplification circuit, a second-stage amplification circuit, a frequency compensation circuit adaptive to load change and an output-stage circuit, wherein the frequency compensation circuit adaptive to load change is composed of a compensation capacitor C1, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8 and a ninth MOS transistor M9; the output of the first-stage amplifying circuit is connected with the input of the second-stage circuit, the output of the second-stage circuit is connected with the output-stage circuit, and the frequency compensation circuit adaptive to load change is connected between the input and the output of the second stage;
the sixth MOS transistor M6 and the seventh MOS transistor M7 are P-type MOS transistors, and the eighth MOS transistor M8 and the ninth MOS transistor M9 are N-type MOS transistors;
the input of the second-stage amplifying circuit is connected to one end of a compensation capacitor C1 in the frequency compensation circuit adaptive to load changes, the output of the second stage amplifying circuit is connected to the drain and the gate of the sixth MOS transistor M6 and the gate of the seventh MOS transistor M7, and the sources of the seventh MOS transistor M7 and the sixth MOS transistor M6 are both connected to a power supply VDD; the drain electrode of the seventh MOS tube M7 is connected with the drain electrode and the grid electrode of the eighth MOS tube M8 and the grid electrode of the ninth MOS tube M9, and the drain electrode of the ninth MOS tube M9 is connected with the compensation capacitor C1 in series and then is connected with the output of the first-stage amplifying circuit; the sources of the eighth MOS transistor M8 and the ninth MOS transistor M9 are both grounded.
In the stabilized telephone, the compensation capacitor C1 and the resistor of the ninth MOS transistor M9 are used as a pole zero compensation pair of the circuit, the load current change is reflected on the voltage of a point C (which is a node output by the second-stage amplifying circuit), and then the load current change is reflected on the voltage of a point F (which is a node connected with the drain electrode of the seventh MOS transistor M7) (namely the gate voltage of the ninth MOS transistor M9) through the current mirror to control the resistance value of the ninth MOS transistor M9, so that the function that the pole zero compensation frequency changes along with the load is realized.
Preferably, the first-stage amplifying circuit comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4 and a tail current source, a power supply VDD is connected to the sources of the first MOS transistor M1 and the second MOS transistor M2 through the tail current source, and the sources of the first MOS transistor M1 and the second MOS transistor M2 are connected; the first MOS transistor M1 and the second MOS transistor M2 are P-type MOS transistors; the grid electrodes of the third MOS transistor M3 and the fourth MOS transistor M4 are connected, and the third MOS transistor M3 and the fourth MOS transistor M4 are both N-type MOS transistors; the sources of the third MOS transistor M3 and the fourth MOS transistor M4 are both grounded; the drain of the first MOS transistor M1 is connected to the drain of the third MOS transistor M3, and the connection section of the drains of the first MOS transistor M1 and the third MOS transistor M3 is provided with a first node a, from which a branch is led out to be connected to the gates of the third MOS transistor M3 and the fourth MOS transistor M4; the drain of the second MOS transistor M2 is connected to the drain of the fourth MOS transistor M4, and a second node B is disposed at a connection section of the drain of the second MOS transistor M2 and the drain of the fourth MOS transistor M4, from which the output of the first stage amplifier circuit is connected.
Preferably, the gate of the first MOS transistor M1 is connected to a reference voltage; the gate of the second MOS transistor M2 is connected to the feedback voltage FBOUT generated by the output stage circuit.
Preferably, the second-stage amplifying circuit includes a fifth MOS transistor M5, a resistor R2 and a resistor R3, the fifth MOS transistor M5 is an N-type MOS transistor, the gate of the fifth MOS transistor M5 is connected to the output of the first-stage amplifying circuit, the source of the fifth MOS transistor M5 is connected in series with the resistor R3 and then grounded, the drain of the fifth MOS transistor M5 is connected to the resistor R2 and then connected to the power supply VDD, and the drain of the fifth MOS transistor M5 is connected to the output-stage circuit.
Compared with the prior art, the invention has the beneficial effects that:
compared with the frequency compensation circuit which takes a fixed resistor as the pole zero point compensation, the frequency compensation circuit which takes the MOS tube as the adjustable resistor and establishes a proper adjustment relation with the load current so that the pole zero point frequency can be automatically adjusted when the load current changes; the system can stably work under different load current conditions, and the precondition of higher current capacity is also provided.
Drawings
Fig. 1 is a basic negative feedback system circuit diagram.
Figure 2 is a bode plot of a stabilization system.
FIG. 3 is a bode plot of an unstable system.
Fig. 4 is a circuit diagram of a conventional frequency compensation scheme of a feedback system in a linear stabilization circuit configuration.
Fig. 5 is an amplitude-frequency diagram without pole zero compensation.
Fig. 6 is an amplitude-frequency diagram after ordinary pole zero compensation.
Fig. 7 is a circuit diagram of a stabilization circuit with an adaptive load change frequency compensation circuit of the present invention.
Fig. 8 is a graph of the amplitude frequency of the follow-up compensation when the load current of the stabilizing circuit of the present invention changes.
Detailed Description
The technical solution of the present invention is described in detail below, but the scope of the present invention is not limited to the embodiments.
In order to make the content of the present invention more comprehensible, the following description is further described with reference to fig. 1 to 8 and the detailed description.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in fig. 7, a stabilizing circuit with a frequency compensation circuit adaptive to load variation of this embodiment includes a first-stage amplifying circuit, a second-stage amplifying circuit, a frequency compensation circuit adaptive to load variation and composed of a compensation capacitor C1, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8 and a ninth MOS transistor M9, and an output-stage circuit; the output of the first-stage amplifying circuit is connected with the input of the second-stage circuit, the output of the second-stage circuit is connected with the output-stage circuit, and the frequency compensation circuit adaptive to load change is connected between the input and the output of the second stage.
As shown in fig. 8, the sixth MOS transistor M6 and the seventh MOS transistor M7 are P-type MOS transistors, and the eighth MOS transistor M8 and the ninth MOS transistor M9 are N-type MOS transistors; the input of the second-stage amplifying circuit is connected to one end of a compensation capacitor C1 in the frequency compensation circuit adaptive to load changes, the output of the second stage amplifying circuit is connected to the drain and the gate of the sixth MOS transistor M6 and the gate of the seventh MOS transistor M7, and the sources of the seventh MOS transistor M7 and the sixth MOS transistor M6 are both connected to a power supply VDD; the drain electrode of the seventh MOS tube M7 is connected with the drain electrode and the grid electrode of the eighth MOS tube M8 and the grid electrode of the ninth MOS tube M9, and the drain electrode of the ninth MOS tube M9 is connected with the compensation capacitor C1 in series and then is connected with the output of the first-stage amplifying circuit; the sources of the eighth MOS transistor M8 and the ninth MOS transistor M9 are both grounded.
The invention of the embodiment replaces the fixed resistor R1 used in the traditional method with a MOS tube resistor controlled by the grid voltage related to the load current, as shown in FIG. 7. The compensation capacitor C1 and the resistor of the ninth MOS transistor M9 serve as a pole-zero compensation pair of the circuit, and the load current variation is reflected on the voltage at point C and then reflected on the voltage at point F (i.e., the gate voltage of the ninth MOS transistor M9) through the current mirror to control the resistance value of the ninth MOS transistor M9.
In the stabilizing circuit of this embodiment, the first-stage amplifying circuit, the second-stage amplifying circuit and the output stage circuit are all known circuits in the art and known to those skilled in the art.
As shown in fig. 7, in the stabilizing circuit of this embodiment, the first-stage amplifying circuit includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, and a tail current source, the power supply VDD is connected to the sources of the first MOS transistor M1 and the second MOS transistor M2 through the tail current source, and the sources of the first MOS transistor M1 and the second MOS transistor M2 are connected; the first MOS transistor M1 and the second MOS transistor M2 are P-type MOS transistors; the grid electrodes of the third MOS transistor M3 and the fourth MOS transistor M4 are connected, and the third MOS transistor M3 and the fourth MOS transistor M4 are both N-type MOS transistors; the sources of the third MOS transistor M3 and the fourth MOS transistor M4 are both grounded; the drain of the first MOS transistor M1 is connected to the drain of the third MOS transistor M3, and the connection section of the drains of the first MOS transistor M1 and the third MOS transistor M3 is provided with a first node a, from which a branch is led out to be connected to the gates of the third MOS transistor M3 and the fourth MOS transistor M4; the drain of the second MOS transistor M2 is connected to the drain of the fourth MOS transistor M4, and a second node B is arranged at a connection section of the drain of the second MOS transistor M2 and the drain of the fourth MOS transistor M4, from which the output of the first-stage amplification circuit is connected; the grid electrode of the first MOS tube M1 is connected with a reference voltage; the gate of the second MOS transistor M2 is connected to the feedback voltage FBOUT generated by the output stage circuit.
In the stabilizing circuit of this embodiment, the second-stage amplifying circuit includes a fifth MOS transistor M5, a resistor R2 and a resistor R3, the fifth MOS transistor M5 is an N-type MOS transistor, a gate of the fifth MOS transistor M5 is connected to an output of the first-stage amplifying circuit, a source of the fifth MOS transistor M5 is connected to the ground after being connected to the resistor R3 in series, a drain of the fifth MOS transistor M5 is connected to the resistor R2 and the power supply VDD in series, and a drain of the fifth MOS transistor M5 is connected to the output stage circuit.
The stabilizing circuit of the present invention uses a frequency compensation circuit adaptive to load variation, the output voltage is fixed, when the load current increases, the output stage analysis shows that the voltage at the point C decreases, the current flowing through the sixth MOS transistor M6 and the seventh MOS transistor M7 increases, the voltage at the point F also increases, that is, the gate voltage of the ninth MOS transistor M9 increases, so that the resistance value of the ninth MOS transistor M9 decreases. From the pole frequency of P1, it is known that the load current increases, the transconductance of the power transistor also increases, and P1 shifts to a higher frequency, and from the compensation frequency of the compensation pole zero, the resistance value of the ninth MOS transistor M9 decreases, and the compensation pole zero frequency also shifts to a higher frequency, as shown in fig. 8. Therefore, when the load changes, the frequency of the compensation pole zero point also changes along with the change, and the purpose of keeping the stability of the circuit is achieved.
Compared with the frequency compensation circuit which uses a fixed resistor as pole zero point compensation, the frequency compensation circuit which uses the MOS tube as an adjustable resistor and establishes a proper adjustment relation with the load current in the stabilizing circuit, so that the pole zero point frequency can be automatically adjusted when the load current changes. The system can stably work under different load current conditions, and the precondition of higher current capacity is also provided.
The parts not involved in the present invention are the same as or can be implemented using the prior art.
As noted above, while the present invention has been shown and described with reference to certain preferred embodiments, it is not to be construed as limited thereto. Various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (4)
1. A stabilizing circuit with a frequency compensation circuit adaptive to load change is characterized by comprising a first-stage amplification circuit, a second-stage amplification circuit, a frequency compensation circuit adaptive to load change and an output-stage circuit, wherein the frequency compensation circuit adaptive to load change is composed of a compensation capacitor C1, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8 and a ninth MOS transistor M9; the output of the first-stage amplifying circuit is connected with the input of the second-stage circuit, the output of the second-stage circuit is connected with the output-stage circuit, and the frequency compensation circuit adaptive to load change is connected between the input and the output of the second stage;
the sixth MOS transistor M6 and the seventh MOS transistor M7 are P-type MOS transistors, and the eighth MOS transistor M8 and the ninth MOS transistor M9 are N-type MOS transistors;
the input of the second-stage amplifying circuit is connected to one end of a compensation capacitor C1 in the frequency compensation circuit adaptive to load changes, the output of the second stage amplifying circuit is connected to the drain and the gate of the sixth MOS transistor M6 and the gate of the seventh MOS transistor M7, and the sources of the seventh MOS transistor M7 and the sixth MOS transistor M6 are both connected to a power supply VDD; the drain electrode of the seventh MOS tube M7 is connected with the drain electrode and the grid electrode of the eighth MOS tube M8 and the grid electrode of the ninth MOS tube M9, and the drain electrode of the ninth MOS tube M9 is connected with the compensation capacitor C1 in series and then is connected with the output of the first-stage amplifying circuit; the sources of the eighth MOS transistor M8 and the ninth MOS transistor M9 are both grounded.
2. The stabilizing circuit of claim 1, wherein the first stage of amplifying circuit comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4 and a tail current source,
a power supply VDD is simultaneously connected to the source electrodes of the first MOS transistor M1 and the second MOS transistor M2 through a tail current source, and the source electrodes of the first MOS transistor M1 and the second MOS transistor M2 are connected; the first MOS transistor M1 and the second MOS transistor M2 are P-type MOS transistors;
the grid electrodes of the third MOS transistor M3 and the fourth MOS transistor M4 are connected, and the third MOS transistor M3 and the fourth MOS transistor M4 are both N-type MOS transistors; the sources of the third MOS transistor M3 and the fourth MOS transistor M4 are both grounded;
the drain of the first MOS transistor M1 is connected to the drain of the third MOS transistor M3, and the connection section of the drains of the first MOS transistor M1 and the third MOS transistor M3 is provided with a first node a, from which a branch is led out to be connected to the gates of the third MOS transistor M3 and the fourth MOS transistor M4;
the drain of the second MOS transistor M2 is connected to the drain of the fourth MOS transistor M4, and a second node B is disposed at a connection section of the drain of the second MOS transistor M2 and the drain of the fourth MOS transistor M4, from which the output of the first stage amplifier circuit is connected.
3. The stabilizing circuit of claim 2, wherein the gate of the first MOS transistor M1 is connected to a reference voltage; the gate of the second MOS transistor M2 is connected to the feedback voltage FBOUT generated by the output stage circuit.
4. The stabilizing circuit of claim 1, wherein the second stage amplifier circuit comprises a fifth MOS transistor M5, a resistor R2 and a resistor R3, the fifth MOS transistor M5 is an N-type MOS transistor, the gate of the fifth MOS transistor M5 is connected to the output of the first stage amplifier circuit, the source of the fifth MOS transistor M5 is connected to the resistor R3 in series and then connected to ground, the drain of the fifth MOS transistor M5 is connected to the resistor R2 and then connected to the power supply VDD, and the drain of the fifth MOS transistor M5 is connected to the output stage circuit.
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| CN117648013A (en) * | 2023-12-04 | 2024-03-05 | 深圳市智创芯微电子有限公司 | Self-adaptive zero setting circuit for phase compensation of low-dropout linear voltage regulator |
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| CN114006610B (en) | 2024-08-16 |
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