JPS5839390B2 - charge injection device - Google Patents
charge injection deviceInfo
- Publication number
- JPS5839390B2 JPS5839390B2 JP54126261A JP12626179A JPS5839390B2 JP S5839390 B2 JPS5839390 B2 JP S5839390B2 JP 54126261 A JP54126261 A JP 54126261A JP 12626179 A JP12626179 A JP 12626179A JP S5839390 B2 JPS5839390 B2 JP S5839390B2
- Authority
- JP
- Japan
- Prior art keywords
- charge
- pixel
- pixels
- switch
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/10—Integrated devices
- H10F39/12—Image sensors
- H10F39/15—Charge-coupled device [CCD] image sensors
- H10F39/154—Charge-injection device [CID] image sensors
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Image Input (AREA)
Description
【発明の詳細な説明】
本発明は光学文字読取やパターン認識における原画像情
報の平滑化、端部検出、線分検出などのいわゆる一次情
報処理を可能とする新規な電荷注入装置(Charge
Injection Device :以下C■Dと
略称する)とその駆動方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention is a novel charge injection device that enables so-called primary information processing such as smoothing of original image information, edge detection, and line segment detection in optical character reading and pattern recognition.
This invention relates to an Injection Device (hereinafter abbreviated as CD) and its driving method.
2次元撮像装置として最近盛んに用いられるCIDは第
1図に示したように、たとえばP型の半導体を基板とし
た受光面1、所定の行または列のアドレス用X、Yシフ
トレジスタ6.7および撮像信号検出回路8とから構成
されている。As shown in FIG. 1, CID, which has recently been widely used as a two-dimensional imaging device, has a light-receiving surface 1 made of, for example, a P-type semiconductor as a substrate, and X and Y shift registers 6.7 for addressing a predetermined row or column. and an imaging signal detection circuit 8.
図中小さく点線で囲んだ1つの区画2は受光面の1画素
分であり、1対の絶縁ゲート電極3aおよび3bから或
っている。One section 2 surrounded by a small dotted line in the figure corresponds to one pixel on the light receiving surface, and is separated from a pair of insulated gate electrodes 3a and 3b.
そして該画素2はマトリックス状に配設され、各画素の
一方の絶縁ゲート電極3aは母線4に並列接続され、他
の絶縁ゲート電極3bは母線5に同じく並列接続されて
いる。The pixels 2 are arranged in a matrix, one insulated gate electrode 3a of each pixel is connected in parallel to the bus bar 4, and the other insulated gate electrode 3b is similarly connected to the bus bar 5 in parallel.
受光面1に結像がなされると光電変換によって生じた電
荷は各々1対の電極の一方の電極たとえば電極3b直下
に蓄積される。When an image is formed on the light-receiving surface 1, charges generated by photoelectric conversion are accumulated directly under one of the pair of electrodes, for example, the electrode 3b.
この状態の各画素をX。Y両シフトレジスタ6.7で番
地指定すれば、指定された画素の蓄積電荷は他の電極3
aで検出されるから、画素の番地指定を順次XY定走査
て行うことにより受光面上の結像に応じた画像信号が母
線4と検出装置8を介して時系列として読み出される。Each pixel in this state is X. By specifying an address using the Y shift register 6.7, the accumulated charge of the specified pixel will be transferred to the other electrode 3.
Since the pixel is detected at point a, the image signals corresponding to the image formed on the light-receiving surface are read out in time series via the generatrix 4 and the detection device 8 by sequentially specifying the address of the pixel by performing constant XY scanning.
一方、画像のパターン認識の手法は、原画像情報の平滑
化、白黒境界部での端部検出、および線分検出などの比
較的単純ないわゆる1次処理と、あらかじめ記憶してお
いた文字、図形などと前記1次処理後の情報との比較、
判断などのごとき更に複雑高度ないわゆる2次処理とに
大別できるが、これら画処理は撮像系と連動する電子計
算器によって行われる。On the other hand, image pattern recognition methods involve relatively simple so-called primary processing such as smoothing of original image information, edge detection at black-and-white boundaries, and line segment detection, as well as pre-memorized character and Comparison of figures etc. with the information after the primary processing,
Image processing can be roughly divided into so-called secondary processing, which is more complex and advanced, such as judgment, and is performed by an electronic computer that works with the imaging system.
このために従来の画像信号処理は、まず前記したCID
面上の各画素をXY定走査て該受光面1上の結像情報を
図示しない記憶装置に残らず収納し、しかる後電子計算
器によって、前記の1次処理、2次処理をほどこして画
像信号の伝送を行うものであったため、撮像系全体とし
ての処理速度の低下、電子計算器の記憶容量の増大など
が問題化していた。For this reason, conventional image signal processing first uses the above-mentioned CID.
Each pixel on the surface is scanned in an XY constant manner, and all image information on the light-receiving surface 1 is stored in a storage device (not shown).Then, an electronic computer performs the above-mentioned primary processing and secondary processing to create an image. Since the system involved transmitting signals, problems such as a decrease in the processing speed of the imaging system as a whole and an increase in the storage capacity of the electronic computer became a problem.
本来OIDは撮像信号の非破壊読み出し機能を有する他
に高速動作が可能であるなどの特徴を有するため、この
OIDの特徴を利用して前記1次処理を行わせることが
考えられる。Originally, OID has features such as not only having a non-destructive readout function of an imaging signal but also being capable of high-speed operation, so it is conceivable to perform the above-mentioned primary processing by utilizing the features of OID.
仮にこのOIDでの1次処理が可能となれば電子計算器
は2次処理だけを行えばよいことになり、その結果は直
ちに必要記憶容量の著しい削減、処理速度の向上をもた
らす筈である。If it were possible to perform primary processing using this OID, the electronic computer would only have to perform secondary processing, which would immediately result in a significant reduction in required storage capacity and an improvement in processing speed.
しかし、この1次処理の実行には所望番地の画素所望数
のランダム読出し機能がOIDに備わっていなげればな
らないのに対し、前記した画素および検出装置などの構
造、ならびに画素走査、信号電荷検出などの駆動法によ
る従来のOIDでは上記ランダム読出しが不可能である
ため、このままの構造では1次処理を行わしめることが
できないという不都合がある。However, in order to execute this primary processing, the OID must have a function for randomly reading a desired number of pixels at a desired address. Since the above-mentioned random readout is not possible with the conventional OID using the driving method described above, there is a disadvantage that primary processing cannot be performed with the structure as it is.
ところで本発明者は先に特願昭54−30732におい
て、OIDの各画素中の前記2電極3a。By the way, the present inventor previously disclosed in Japanese Patent Application No. 54-30732 the above-mentioned two electrodes 3a in each pixel of OID.
3bを遮光すると共に光電変換専用の、透光窓を直上部
に具えた第3の電極3c、つまり感光電極を設けること
により、画素信号のランダム読出しに適した画素構造を
提案した。We have proposed a pixel structure suitable for random readout of pixel signals by shielding electrode 3b from light and providing a third electrode 3c, that is, a photosensitive electrode, which has a light-transmitting window directly above it and is dedicated to photoelectric conversion.
本発明はこのような構成のOIDを利用して上記従来の
問題を解決するようにしたもので、上記3電極構成の画
素群を受光面とし、画素のランダム番地指定が可能なよ
うに従来のX、Yシフトレジスタを、X、Y各方向に配
置されたデコーダに置きかえ、かつ1群もしくは2群か
らなる複数個の画素からの各信号群に対してそれぞれ所
定の重み係数を付与しうる2系統の信号検出器、該検出
器の一方からの信号群に極性反転をほどこす差動増幅器
、ならびに上記各信号群同志間の演算を行う演算器を備
えた新規なOIDを提供するものであって、第2図以下
の図面を用いて詳記する。The present invention utilizes OID with such a configuration to solve the above-mentioned conventional problems.The present invention uses the pixel group with the above-mentioned three-electrode configuration as a light-receiving surface, and uses the conventional method to enable random pixel address designation. It is possible to replace the X and Y shift registers with decoders arranged in each of the X and Y directions, and to assign a predetermined weighting coefficient to each signal group from a plurality of pixels consisting of one group or two groups. The present invention provides a novel OID equipped with a system signal detector, a differential amplifier for inverting the polarity of a group of signals from one of the detectors, and an arithmetic unit for performing calculations between the respective signal groups. This will be described in detail using the drawings from FIG. 2 onwards.
第2図は本発明に係るOIDを模式的に示したもので、
前記第1図と同一部位には同一記号を付して示しである
。FIG. 2 schematically shows the OID according to the present invention.
The same parts as in FIG. 1 are shown with the same symbols.
受光面を構成する各画素2の構造と動作に関しては先に
特願昭54−30732に述べた所であるが、簡単に説
明すれば以下のごとくである。The structure and operation of each pixel 2 constituting the light-receiving surface was previously described in Japanese Patent Application No. 54-30732, but a brief explanation is as follows.
各画素2中には第1および第2の絶縁電極3 a 、3
bの他に透光性の第3絶縁電極3cが設けられており
、各画素中の該第3電極3cは図示しない共通の母線で
電気的に連結され、10で示した端子からパルス電圧が
印加されるようになっている。In each pixel 2 there are first and second insulated electrodes 3a, 3.
In addition to b, a translucent third insulated electrode 3c is provided, and the third electrode 3c in each pixel is electrically connected by a common bus bar (not shown), and a pulse voltage is applied from a terminal indicated by 10. It is now applied.
そして該受光面の上部は、上記第3電極3cの直上部に
のみ図示しない透光窓群を有するこれも図示しない遮光
膜で覆われている。The upper part of the light-receiving surface is covered with a light-shielding film (also not shown) having a group of light-transmitting windows (not shown) only directly above the third electrode 3c.
端子10に印加される電圧が正極性の例えば8Vの値に
ある間は、該電極3c直下に電位の井戸(以下単に井戸
と称する)が生じる。While the voltage applied to the terminal 10 is of positive polarity, for example, 8V, a potential well (hereinafter simply referred to as a well) is generated directly below the electrode 3c.
透光窓からの入射結像光による電荷発生は該井戸中で行
われ、該電荷は上記端子10の電圧が零にもどると該井
戸が無くなるため、隣接する電極3b直下に作られてい
た井戸中へ移されて一時的に蓄積され、さらに電極3a
直下の井戸中へ移された際に電極3aによって検出され
る。Electric charges are generated in the well by the incident imaging light from the light-transmitting window, and when the voltage at the terminal 10 returns to zero, the well disappears. The electrode 3a is transferred inside and temporarily accumulated.
It is detected by the electrode 3a when it is moved into the well directly below it.
このため以下では各電極3 c t 3 b t 3
aをそれぞれ感光電極、蓄積電極、および読出電極と呼
ぶことにする。Therefore, in the following, each electrode 3 c t 3 b t 3
a will be referred to as a photosensitive electrode, a storage electrode, and a readout electrode, respectively.
各電極3b直下の井戸群は番地指定回路7aの端子Y。The well group directly below each electrode 3b is the terminal Y of the address designation circuit 7a.
〜Y4 より該電極にあらかじめ印加されている電圧に
よって作られており、各電極3a直下の井戸群を作るに
は複数のスイッチ9を、スイッチSW1またはSW2と
共に閉じて電源31から例えば8Vの正の電圧を該電極
3a群に印加すればよい。~ Y4 is generated by the voltage applied in advance to the electrodes. To create a well group directly under each electrode 3a, close the plurality of switches 9 together with the switch SW1 or SW2 and apply a positive voltage of, for example, 8V from the power source 31. A voltage may be applied to the group of electrodes 3a.
この電極3a直下に形成された井戸群は上記スイッチ群
が開かれたあとでも数10 m sec程度の間は保持
されているから、感光、蓄積、読出しの過程はこれより
短い時間内に行えばよい。Since the well group formed directly under the electrode 3a is maintained for several tens of milliseconds even after the switch group is opened, the processes of exposure, storage, and readout can be performed within a shorter time than this. good.
6a、7aは先の第1図中のシフトレジスタに代わって
設けられた番地指定回路であって、デコーダとドライバ
からなっている。Reference numerals 6a and 7a designate address designating circuits provided in place of the shift registers in FIG. 1, which are comprised of a decoder and a driver.
該回路6a 、 ?aが有する端子すなわち、Xo 2
XH、X2 t X2 tX4・・・・・・およびY
。The circuit 6a, ? The terminal that a has, that is, Xo 2
XH, X2 t X2 tX4...and Y
.
、 Y、 、 Y2 、 Y3. Y、・・・・・・の
うちから複数個の端子を選んで該端子からの指令電圧に
より所望数の画素を番地指定し、たとえば2種類のブロ
ック状もしくは線状に形成された受光面部分の2群から
なる画素信号電荷をスイッチ5o−S4を介して別々に
信号電荷検出線路20上に時系列として読み出すことが
できる。, Y, , Y2, Y3. Select a plurality of terminals from among Y, . The pixel signal charges consisting of the two groups can be read out separately in time series onto the signal charge detection line 20 via the switches 5o-S4.
そして上記2群の信号電荷群を、信号路導入切替スイッ
チsw、、sw2の選択開閉によって電荷増幅器AI
。Then, the two groups of signal charges are transferred to the charge amplifier AI by selectively opening and closing the signal path introduction changeover switches sw, , sw2.
.
A2の各個に時系列として別々に導き、該両端幅器の各
出力端子すなわち点P1tP2に順次V、。A2 separately as a time series, and sequentially V, to each output terminal of the double-width divider, that is, the point P1tP2.
v2 として現れる各出力電圧を差動増幅器A3 に入
力して、前記電圧V2の極性を反転せしめて電圧V、の
逆極性にする。Each output voltage, appearing as v2, is input to a differential amplifier A3, which inverts the polarity of said voltage V2, making it the opposite polarity of voltage V,.
そしてスイッチSW3、容量C33、および増幅器A4
を用い、後述する手続きによって第1画素ブロックから
の信号と第2ブロツクからの信号との減算操作を行わし
めうるようにもなっている。and switch SW3, capacitor C33, and amplifier A4
It is also possible to perform a subtraction operation between the signal from the first pixel block and the signal from the second pixel block using a procedure described later.
4×4画素分を受光面要部として書いた第2図において
そのうちの3×3画素を基本ブロックとする場合の動作
について以下説明する。In FIG. 2, in which 4×4 pixels are shown as the essential parts of the light-receiving surface, the operation in the case where 3×3 pixels among them are used as a basic block will be described below.
仮に前記した各電荷増幅器A、、A2の入出力端子をつ
なぐ帰還容量をOf、入力端子にまたがる容量をCin
とすれば、該増幅器A、、A2の利得はO1n10
f で決まる。Assume that the feedback capacitance connecting the input and output terminals of each charge amplifier A, A2 mentioned above is Off, and the capacitance spanning the input terminals is Cin.
Then, the gain of the amplifiers A, , A2 is O1n10
It is determined by f.
ここで第2図中にC31゜C21として示された第1の
帰還容量は同じ値に、そして第2の帰還容量C1□と0
2□は前記第1の帰還容量0112012の8倍に選ば
れている、つまり重みづけがなされているとする。Here, the first feedback capacitance shown as C31°C21 in FIG. 2 has the same value, and the second feedback capacitance C1□ and 0
It is assumed that 2□ is selected to be eight times the first feedback capacitance 0112012, that is, it is weighted.
たとえば第2図中の番地指定回路7aと6aによって指
定された1画素Cx、1)からの信号電荷の検出は次の
ようにして行う。For example, detection of a signal charge from one pixel Cx, 1) designated by address designating circuits 7a and 6a in FIG. 2 is performed as follows.
まずスイッチSW2および12を開いておき番地指定回
路6aからの電圧によってスイッチS。First, the switches SW2 and SW12 are opened and the switch S is opened by the voltage from the address designating circuit 6a.
を閉じる。Close.
これと同時にスイッチ11を閉じておくがこの処置によ
って電荷増幅器にはCI2の1/8の値の容量C11が
接続される。At the same time, the switch 11 is closed, and by this action, a capacitor C11 having a value of 1/8 of CI2 is connected to the charge amplifier.
このため該(1,1)画素の電荷は0in1011なる
利得を有する電荷増幅器A、で検出されることになる。Therefore, the charge of the (1,1) pixel is detected by the charge amplifier A having a gain of 0 in 1011.
これに対しく0,0)t(0,1)t(o、2)。On the other hand, 0,0)t(0,1)t(o,2).
(1,0)、(1,1)、(1,2)、(2,0)、(
2,1)。(1,0), (1,1), (1,2), (2,0), (
2,1).
(2,2)の9画素の電荷を順に読み出して積算の上そ
の平均をとる場合においては、受光面の入射光量を均一
と仮定すれば、信号電荷は合計9qとなるため、見掛は
上9倍の出力信号が電荷増幅器A、から出力されてしま
う。When the charges of the 9 pixels in (2, 2) are sequentially read out, integrated, and then averaged, assuming that the amount of incident light on the light receiving surface is uniform, the signal charge will be 9q in total, so the apparent appearance will be higher. An output signal 9 times as large will be output from the charge amplifier A.
これを避けるため、スイッチ11および12を閉じるこ
とにより電荷増幅器A、に011およびその8倍の値を
有する容量012を同時に接続して、該増幅器A、の利
得をあらかじめ1/9に減じることすなわち重み付けを
ほどこすことを行なっておく。In order to avoid this, by closing switches 11 and 12, 011 and a capacitor 012 having a value eight times that value are simultaneously connected to the charge amplifier A, and the gain of the amplifier A is reduced to 1/9 in advance. First, apply weights.
かくすることにより上記9画素分の電荷の積算平均の場
合と、前記1画素分のみの検出の場合とのバランスがと
れる。In this way, a balance can be achieved between the accumulation average of charges for nine pixels and the detection of only one pixel.
また上記9画素のうち8画素分の電荷を読み出す場合に
はスイッチ11を開きスイッチ12を閉じて、011の
8倍の容量の01□だけを電荷増幅器A、に接続して利
得をOin/80. 、としておけばよい。In addition, when reading out charges for 8 of the 9 pixels, open switch 11 and close switch 12, connect only 01□, which has a capacitance 8 times that of 011, to charge amplifier A, and set the gain to Oin/80. .. , it is sufficient to set it as .
なおR,、Tt2は、容量011.021 j C32
2022中の残存電荷を放電するためのリセットスイッ
チで、電荷検出を上記増幅器A3.A2で行う以前は閉
じておき、検出時には開いておく。Note that R,, Tt2 is the capacity 011.021 j C32
A reset switch for discharging the residual charge in the amplifier A3. It is closed before performing A2, and left open at the time of detection.
以上に述べたことがらの上に立って本発明に係るOID
による1次処理動作を説明する。Based on the above-mentioned matters, the OID according to the present invention
The primary processing operation will be explained below.
1)平滑化処理
平滑化処理は読取対象物たとえば白色下地を有する帳票
面上0黒いシミの消去、画像信号の帯域圧縮、または帳
票面上図形のおよその認識に有効である。1) Smoothing Process Smoothing process is effective for erasing black spots on an object to be read, such as a document surface with a white background, compressing the band of an image signal, or roughly recognizing figures on a document surface.
画素の電荷検出にはA、、A2どちらの電荷増幅器を用
いてもよいが、ここでは増幅器A1を用いるものとする
。Although either of the charge amplifiers A, A2 may be used to detect the charge of the pixel, here, the amplifier A1 is used.
まず、感光電極3a直下に作られた井戸中に光電変換に
よる信号電荷を生せしめ、しかるのち前記した番地指定
回路6aの端子X。First, a signal charge is generated by photoelectric conversion in a well made directly under the photosensitive electrode 3a, and then the terminal X of the address designation circuit 6a described above is generated.
−X4のうちX。なる端子からの電圧によってスイッチ
S。-X out of X4. Switch S by the voltage from the terminal.
を開く。次に増幅器A1のリセットスイッチR3を閉じ
た後再び開けば、電源31の電圧VRが増幅器A、の入
力端子、スイッチSW1.Soを介して画素(0,0)
中の感光電極3aに印加されて該電極直下に前記したご
とく井戸が生じ、該井戸中の電荷の読み出し待機状態が
完了する。open. Next, when the reset switch R3 of the amplifier A1 is closed and then opened again, the voltage VR of the power supply 31 is transferred to the input terminal of the amplifier A, the switch SW1. Pixel (0,0) through So
The voltage is applied to the photosensitive electrode 3a in the photosensitive electrode 3a, and a well is formed directly below the electrode as described above, and the standby state for reading out the charges in the well is completed.
次に番地指定回路7aの端子Y。−Y。のそれぞれにあ
らかじめ現れていた各電圧のうちYo端子の電圧のみを
零とすれば蓄積電極2b直下の井戸が消滅し、ここに蓄
積されていた電荷は隣接する読出し電極3a直下の井戸
へ移ることにより該電極3aによって検出される。Next is the terminal Y of the address designation circuit 7a. -Y. If only the voltage at the Yo terminal is made zero among the voltages that appeared in each of the voltages, the well directly below the storage electrode 2b disappears, and the charge stored here moves to the well directly below the adjacent readout electrode 3a. is detected by the electrode 3a.
この検出された電荷はスイッチS。This detected charge is applied to switch S.
、SW、を通じて増幅器A1 に入力された後、差動増
幅器A3に送られ、点P3に電圧v3として現れる。, SW, and then to the differential amplifier A3, and appears as a voltage v3 at point P3.
ここでスイッチSW3が点P3側に倒されていると該電
圧は容量013に電荷として一時的に蓄えられる。If the switch SW3 is turned to the point P3 side, the voltage is temporarily stored in the capacitor 013 as a charge.
A、は演算増幅器であるが、帰還容量014を有してい
るため、該増幅器の負入力端子つまり点P4にはG40
14なる容量が存在するのと等価である。A is an operational amplifier, but since it has a feedback capacitance of 014, G40 is connected to the negative input terminal of the amplifier, that is, the point P4.
This is equivalent to having a capacity of 14.
ここで04は該増幅器の開ループ利得である。Here 04 is the open loop gain of the amplifier.
したがってスイッチSW3が点P4に倒されると上記容
量013中の電荷は上記の容量G4・014 に移され
て蓄えられると見なすことができる。Therefore, it can be considered that when the switch SW3 is turned down to the point P4, the charge in the capacitor 013 is transferred to and stored in the capacitor G4.014.
次に先の画素(010)に隣接する画素(0゜l)を番
地指定し、上と同様の手続きを用いて先に画素(0,0
)の電荷を蓄積していた上記の容量G4・014中に重
ねて蓄積する。Next, specify the address of the pixel (0゜l) adjacent to the previous pixel (010), and use the same procedure as above to first address the pixel (0,0).
) is accumulated in the capacitor G4·014 which had been accumulated.
以下同様にして9個の画素(0,2)、(ItO)、(
1,IL・・・・・・を順次番地指定し、そのたびごと
に画素の出力を容量G4・014中に蓄積して行けば、
最終画素(212)の信号電荷を検出し終った時点で上
記9画素分の全電荷の積算は完了する。Similarly, nine pixels (0, 2), (ItO), (
If addresses 1, IL, etc. are specified in sequence, and each time the output of the pixel is stored in the capacitor G4.014,
At the time when the signal charge of the final pixel (212) has been detected, the integration of all the charges for the nine pixels is completed.
しかるにこれら各電荷は前もって利得を179に減じた
電荷増幅器A、で読み出されたのであるから、結果的に
は前述した9画素分電荷の平均値QMを求める手続き、
つまり
なる演算操作が実行されたことになる。However, since each of these charges was read out by the charge amplifier A whose gain was reduced to 179 in advance, the procedure for calculating the average value QM of the charges for 9 pixels as described above,
In other words, the following arithmetic operation has been executed.
ただしi。jはそれぞれi行j行を意味する副号である
。However, i. j is a subsign that means the i row and the j row, respectively.
上記の3×3画素ブロックについての平滑化処理が終っ
てその結果が最終端子、点P5から出力されれば、次の
画素群、たとえば(3,o ) t(3,IL(a、2
)およびこれらを最上行とスル図示しない他の6画素か
らなる次の3×3画素ブロックを番地指定し直せば、帳
票上の別の部分(ブロック)の原映像に対する上と同じ
平滑化処理を遂行しうる。When the smoothing process for the above 3x3 pixel block is finished and the result is output from the final terminal, point P5, the next pixel group, for example (3, o ) t (3, IL (a, 2
) and the next 3x3 pixel block consisting of the top row and the other 6 pixels (not shown), the same smoothing process as above can be applied to the original image of another part (block) on the form. It can be carried out.
この場合1ブロツクの平滑化処理が完了して次のブロッ
クの平滑化処理に移る際には、増幅器A4のリセットス
イッチR3を閉じて先に04014に蓄積された全電荷
を放電(リセット)させねばならない。In this case, when the smoothing process for one block is completed and the smoothing process for the next block is to be started, the reset switch R3 of the amplifier A4 must be closed to first discharge (reset) all the charges accumulated in 04014. No.
なお増幅器A4の正入力端子に接続された電源32は、
該増幅器A4への入力信号中に含まれている直流分除去
のためのもので該直流電圧と値が等しく逆極性になるよ
うに加えられており、これによって増幅器A4の出力に
は不要な直流成分を含まない信号成分のみが得られるこ
とになる。Note that the power supply 32 connected to the positive input terminal of the amplifier A4 is
This is to remove the DC component contained in the input signal to the amplifier A4, and is added so that the DC voltage and the value are equal and opposite in polarity, so that unnecessary DC components are removed from the output of the amplifier A4. Only signal components containing no components will be obtained.
また増幅器A4の最終出力端子P、に現れる信号出力は
該端子P、に所望の平滑回路を接続しこれを通すことに
より所望のアナログ信号として取り出せる。Further, the signal output appearing at the final output terminal P of the amplifier A4 can be taken out as a desired analog signal by connecting a desired smoothing circuit to the terminal P and passing it therethrough.
1i)端部検出
端部検出はたとえば第3図aに示したような帳票上の斜
線をほどこした黒色部とその右側の白色部からなるパタ
ーンの端部イを線像として検出するものである。1i) End Detection End detection is to detect, as a line image, the end A of a pattern consisting of a diagonally lined black area on a form and a white area to the right of it, as shown in FIG. 3a, for example. .
乙・9ような端部、換言すれば白黒境界線の検出には、
中心となる画素(l、1)の信号電荷をまず読み出し、
次いでこれを取囲む8画素(0,0) 、(0,1)t
(0,2)t(LO)、(1,2)、(2,O)、(2
,1)。To detect edges like Otsu-9, in other words, black and white boundaries,
First read out the signal charge of the central pixel (l, 1),
Next, the 8 pixels surrounding this (0,0), (0,1)t
(0,2)t(LO), (1,2), (2,O), (2
,1).
(2t 2 )の全信号電荷の読み出しと平滑化を行な
った後、両者の差で決まる平均電荷QEを求めること、
即ち
なる演算によって行いうる。After reading and smoothing the total signal charge of (2t 2 ), finding the average charge QE determined by the difference between the two;
That is, it can be performed by the following calculation.
画素番地指定、複数画素信号の平均化などの操作はすで
に述べたところであるので以下では検出処理の手続きに
ついて説明する。Operations such as pixel address designation and averaging of multiple pixel signals have already been described, so the detection processing procedure will be explained below.
まず第2図中の中心画素例えば(1,1)を番地指定し
、電荷増幅器A1 のスイッチ12は開いたままでスイ
ッチ11を閉じ、該増幅器A、に容量011を接続して
その利得を06n1011 とする。First, address the center pixel in FIG. 2, for example (1, 1), close the switch 11 while keeping the switch 12 of the charge amplifier A1 open, and connect the capacitor 011 to the amplifier A to set its gain to 06n1011. do.
そしてスイッチSW、を閉じ、画素(l、■)の信号電
荷を電荷増幅器A、に導げば該増幅器A。Then, the switch SW is closed and the signal charge of the pixel (l, ■) is guided to the charge amplifier A.
の出力端子、点P、に電圧V、として現れた上記画素信
号は差動増幅器A3の正入力端子に加えられて点P3に
電圧V3として現れる。The pixel signal appearing as a voltage V at the output terminal, point P, is applied to the positive input terminal of the differential amplifier A3, and appears as a voltage V3 at a point P3.
ここでスイッチSW3が点P3側に倒されていると電圧
V3は容量C13を充電するが、この充電電荷は差動増
幅器A3の正入力端子に導入された信号時系列の積算結
果であるため便宜上その極性を正と見なす。If the switch SW3 is turned to the point P3 side, the voltage V3 charges the capacitor C13, but this charging charge is the result of integrating the signal time series introduced into the positive input terminal of the differential amplifier A3, so for convenience Its polarity is considered positive.
この正極性電荷はスイッチSW3が点P4に倒された時
に電荷増幅器A4に移されて該増幅器A、の前記した等
個入力容量G、C,,に蓄えられる。This positive polarity charge is transferred to the charge amplifier A4 when the switch SW3 is turned down to the point P4, and is stored in the equal input capacitances G, C, . . . of the amplifier A.
つぎに電荷増幅器A2のスイッチ21は開いたままスイ
ッチ22を閉じ該増幅器A2 に021の8倍の値の容
量022を接続して、その利得をC!1n1022つま
り増幅器A、の利得の178 Fct、ておく。Next, the switch 22 of the charge amplifier A2 is closed while the switch 21 of the charge amplifier A2 remains open, and a capacitor 022 whose value is eight times that of 021 is connected to the amplifier A2, and its gain is reduced to C! 1n1022, that is, the gain of amplifier A is 178 Fct.
そしてスイッチSW2を開き、かわりにスイッチSW2
を閉じた上で(t t i)画素周囲の前記8画素を順
次番地指定し、該8画素分の電荷を遂次電荷増幅器A2
に入力すれば該増幅器A2の出力端子、点P2に電圧v
2として現れた上記8画素分の信号は差動増幅器A3の
負入力端子に加えられる。Then open switch SW2 and switch SW2 instead.
(t t i) The eight pixels around the pixel are sequentially addressed, and the charge of the eight pixels is sequentially transferred to the charge amplifier A2.
If the voltage is input to the output terminal of the amplifier A2, the voltage v at the point P2.
The signals for the 8 pixels appearing as 2 are applied to the negative input terminal of the differential amplifier A3.
このため点P3に現れる該信号は、先に述べた点P1
に現れた電圧とは逆極性で出力されるのでスイッチSW
3が再び点P3側に倒されると、容量CI3には負の極
性を有する8画素分の負電荷が蓄積される。Therefore, the signal appearing at point P3 is
The voltage that appears on the switch SW is output with the opposite polarity.
3 is again moved to the point P3 side, negative charges for eight pixels having negative polarity are accumulated in the capacitor CI3.
ここでスイッチSW3が再び点P4 に倒されると、先
に04014なる容量に蓄積されていた正電荷に上記8
画素分の負電荷が加えられるため、ここに減算操作が完
了する。Here, when the switch SW3 is turned down again to point P4, the positive charge previously accumulated in the capacitor 04014 is added to the above 8
The subtraction operation is completed at this point because the negative charge for the pixel is added.
したがってこの減算結果を検出するには点P5 に現れ
た出力電圧を読み出せばよい。Therefore, in order to detect this subtraction result, it is sufficient to read the output voltage appearing at point P5.
上記の操作を用いれば前記した端部検出が次のごとく行
える。By using the above operations, the above-mentioned end detection can be performed as follows.
まず端部が第3図aの点線■に位置すれば画素(+、1
)を含む9つの画素(0゜O)〜(2,2)はすべて帳
票面の白信号を受けている。First, if the end is located at the dotted line ■ in Figure 3a, the pixel (+, 1
), all nine pixels (0°O) to (2,2) receive the white signal of the form surface.
以下これを白レベルに有ると表現することにするが、便
宜上、各画素(0,0)?(Oyl)、(0,2)・・
・・・・(2,2)が生じる電荷をそれぞれq。Below, this will be expressed as being at the white level, but for convenience, each pixel (0,0)? (Oyl), (0,2)...
...The charges generated by (2, 2) are each q.
O、(101+ qO2t・・・・・・q2□で表現し
、かつ白レベルにおける電荷を10qとする。O, (101+qO2t...q2□), and the charge at the white level is assumed to be 10q.
そして画素が帳票面上の黒色部から受光している時を黒
レベルにあると表現し、その場合の電荷を零とする。The time when the pixel is receiving light from the black area on the form surface is expressed as being at the black level, and the charge in that case is assumed to be zero.
かくすれば上記電荷q。o”Q2□はすべて10qなる
電荷を生じているので、前記(2)式の左辺QEは零と
なる。Thus, the above charge q. o''Q2□ all generate a charge of 10q, so QE on the left side of equation (2) becomes zero.
つぎに端部が第3図の実線■に位置する時は、(0,0
) 、(Ozl)t(1,0L(1ylL(2,0)、
(2jl)なる6画素はすべて白レベルにあり10qな
る電荷を生じるが他の画素(0,2)、(l、2)、(
2,2)は黒レベルにあって生じる電荷は零である。Next, when the end is located at the solid line ■ in Figure 3, (0,0
) , (Ozl)t(1,0L(1ylL(2,0),
The six pixels (2jl) are all at the white level and generate a charge of 10q, but the other pixels (0,2), (l,2), (
2, 2) is at the black level and the generated charge is zero.
このため(2)式のQEは+3.75となる。Therefore, QE in equation (2) is +3.75.
さらに端部が点線■に位置する時は(0,0)。Furthermore, when the end is located on the dotted line ■, it is (0,0).
(l、0)、(2,0)なる3画素が白レベルにあり1
0qなる電荷を生じるが、他の画素(0゜1)、(Q、
2)、(1,1)j(1,2)j(2,1)、(2F2
)はすべて黒レベルにあり。Three pixels (l, 0) and (2, 0) are at the white level and 1
A charge of 0q is generated, but other pixels (0°1), (Q,
2), (1,1)j(1,2)j(2,1),(2F2
) are all at black level.
生じる電荷は零であって(2)式のQEは−3,75と
なる。The generated charge is zero, and QE in equation (2) is -3,75.
最後に端部が点線■に位置すれば(o p o )〜(
2,2)の全画素はすべて黒レベルにあり、生じる電荷
はすべて零となるため、(2)式のQoは再び零にもど
る。Finally, if the end is located on the dotted line ■, (op o ) ~ (
Since all the pixels in 2, 2) are at the black level and all the generated charges are zero, Qo in equation (2) returns to zero again.
上記した各場合のうち、端部が■および■にある場合、
+3.75、−3.75なるQEは互いに符号が逆であ
るが該信号の出力の極性はたとえばこれを第2図の点P
5以降につながる図示しない回路中で自乗することによ
って正と化すことができる。Among the above cases, if the ends are in ■ and ■,
QE of +3.75 and -3.75 have opposite signs, but the polarity of the output of the signal is, for example, at point P in Figure 2.
It can be made positive by squaring it in a circuit (not shown) connected to 5 and onwards.
そしてその値は該端部■から■に移動する期間中維持さ
れるためこの様子を書けば第3図すのごとく1画素分の
幅を有する信号出力となる。Since that value is maintained during the period of movement from the end part (2) to (2), this situation results in a signal output having a width of one pixel as shown in FIG.
ただし第3図ayb中のX、yはそれぞれ帳票面の水平
および垂直方向を示す。However, X and y in FIG. 3 ayb indicate the horizontal and vertical directions of the form surface, respectively.
上記した9画素ブロックで読み出された帳票面の信号検
出が完了すれば、これに隣接するたとえば同ブロックの
垂直方向に位置する図示しない(3tOL(3,IL(
3,2)・・・・・・(5,2)からなる別の9画素で
構成されたブロックを改めて番地指定する。Once the signal detection of the form surface read out in the above-mentioned 9 pixel block is completed, the adjacent signal (3tOL(3, IL(
3,2)...A block consisting of another nine pixels consisting of (5,2) is designated anew.
そして同様の操作が終了すれば更に垂直方向に隣接する
他の9画素ブロックを番地指定する。When the same operation is completed, addresses of other nine pixel blocks adjacent in the vertical direction are specified.
以下同様の操作を行なっていけば、第3図aの端部イが
生じた第3図すの信号は、縦方向−直線に並ぶため、該
端部は縦方向に引かれた線像として検出できる。If the same operation is carried out thereafter, the signals in Figure 3 (S) where the end (A) in Figure 3A occurs will be aligned in the vertical direction - a straight line, so the end will appear as a line image drawn in the vertical direction. Can be detected.
111)線分検出
線分検出は特定方向の線分のみを抽出したい場合に有効
である。111) Line segment detection Line segment detection is effective when it is desired to extract only line segments in a specific direction.
最も簡単な例は、加算記号十における縦描線の部分は検
出せずに横描線の部分のみを抽出したい場合であるので
、以下ではこの場合について説明する。The simplest example is a case where it is desired to extract only the horizontally drawn line part without detecting the vertically drawn line part in the addition symbol 10, so this case will be explained below.
まず例えば横方向に並ぶ画素(1,0L(Ll)、(1
,2)にうづいて該画素配列方向に並ぶ9画素分すなわ
ち(1,0)〜(1,8)を番地指定する。First, for example, pixels arranged in the horizontal direction (1, 0L (Ll), (1
, 2), the addresses of nine pixels arranged in the pixel arrangement direction, that is, (1,0) to (1,8) are specified.
そして該9画素分の信号電荷に対して先に平滑化処理の
所で示したと同じ手続きつまり(1)式で示した平均化
をほどこす。Then, the signal charges of the nine pixels are subjected to the same procedure as described above in the smoothing process, that is, the averaging shown in equation (1).
そのためには第2図の番地指定回路6aの端子X、から
の電圧によってスイッチS、を閉じると共に番地指定回
路1aの端子群のうち端子Y。To do this, switch S is closed by the voltage from terminal X of address designating circuit 6a in FIG. 2, and terminal Y of the terminal group of address designation circuit 1a is closed.
−Y8からの各出力電圧をすべて零とする。- Set all output voltages from Y8 to zero.
一方、増幅器A、には容量012を接続し、利得をC1
VC42、つまりCin/80Hに設定し、スイッチS
W、、増幅器A、およびA3を介して上記9画素分の電
荷を最終的に増幅器A4の等価入力容量040Hに積算
して平均化を完了する。On the other hand, a capacitor 012 is connected to amplifier A, and the gain is set to C1.
Set to VC42, that is, Cin/80H, and switch S.
The charges for the nine pixels are finally integrated into the equivalent input capacitance 040H of the amplifier A4 via W, , amplifier A, and A3 to complete the averaging.
帳票上に画かれた原画像線分の検出は上記手続きによっ
て次のごとく行いうる。Detection of the original image line segment drawn on the form can be performed as follows using the above procedure.
説明の便宜上帳票面は黒地とし、その上に白色で縦横共
に1画素分に等しい幅を有する各描線で構成された十記
号が書かれているとする。For convenience of explanation, it is assumed that the form surface is a black background, and a ten symbol made up of white drawn lines each having a width equal to one pixel in both the vertical and horizontal directions is written on it.
第4図a中の斜線部分は黒地を示すものであるが、符号
口1.ヌ、およびトの各部で形成される白色の該十記号
の横描線上を、(lt o )〜(1,8)で構成され
る画素列がX方向に移動する場合を考えると、まず該横
描線の端部イが点線■に位置する時は全画素は黒レベル
に有ってその出力信号電荷は零であるために前記(1)
式で与えられた平均電荷QMは零である。The shaded area in FIG. 4a indicates a black background, and the code entry 1. Considering the case where a pixel row composed of (lt o ) to (1,8) moves in the X direction on the horizontal line of the white ten symbol formed by each part of When the end A of the horizontal line is located at the dotted line ■, all pixels are at the black level and their output signal charge is zero, so (1)
The average charge QM given by the formula is zero.
該端部イが点線■の位置に来ると画素(i t s )
のみが黒レベルから白レベルに移り、該1画素分の電荷
量(゛便宜上9qとする)が検出されるが他の8画素の
出力電荷はすべて零であるため、上記1画素分の電荷9
qは9画素について平均化され、(1)式の平均電荷Q
Mは1/9でしかない。When the end A comes to the position indicated by the dotted line ■, the pixel (it s )
9 changes from the black level to the white level, and the amount of charge for that one pixel (9q for convenience) is detected, but the output charges of the other 8 pixels are all zero, so the charge for the one pixel 9
q is averaged over 9 pixels, and the average charge Q in equation (1)
M is only 1/9.
しかし上記端部イが点線■に位置すれば(1,8)画素
に加えて(1t7)画素も9qなる電荷を出力するので
QMは2/9となりさらに端部イが点線■に到ると図示
しない(L6)画素もまた9qなる電荷を出力するに及
んで平均電荷QMは3/9となる。However, if the above end A is located on the dotted line ■, the pixel (1t7) in addition to the (1,8) pixel will output a charge of 9q, so QM will be 2/9 and when the end A reaches the dotted line ■ The pixel (L6) not shown also outputs a charge of 9q, so that the average charge QM becomes 3/9.
このようにして平均電荷QMは漸次その値を増すが、こ
こで上記画素列の長さeは、前記横描線の長さの9倍す
なわち81画素分であると仮定すると、前記端部イが点
線■上に到達した時、すなわち9画素全部が白レベルに
位置した時点でQMの値は9/9=1となる。In this way, the average charge QM gradually increases in value. Here, assuming that the length e of the pixel row is 9 times the length of the horizontal line, that is, 81 pixels, the end portion i is When reaching above the dotted line ■, that is, when all nine pixels are located at the white level, the value of QM becomes 9/9=1.
このQM=1なる平均電荷出力は、描線が画素列方向に
1画素ずつ81回移動してすべての画素が白しベルにあ
る間中換言すれば、該画線の他の部分トの左側に位置す
る端部チが点線■の位置に到るまで維持される。In other words, while the drawn line moves 81 times pixel by pixel in the direction of the pixel column and all the pixels are white, the average charge output of QM=1 is calculated as follows: The position is maintained until the end position Q reaches the position indicated by the dotted line ■.
そして該端部チが点線■に位置した時には全9画素のう
ち(l、8)画素のみが白レベルから黒レベルに転する
ため該画素(1,8)の出力電荷は零となる。When the end portion Q is located at the dotted line ■, only the pixel (l, 8) out of the total nine pixels changes from the white level to the black level, so the output charge of the pixel (1, 8) becomes zero.
しかし他の8画素は依然として白レベルにあって、それ
ぞれ9qなる電荷を出力している。However, the other eight pixels are still at the white level and each outputs a charge of 9q.
したがって平均電荷QMは再び8/9に減少し、さらに
該端部チが点線■に位置した時には0Mは一層減じて7
/9となる。Therefore, the average charge QM decreases to 8/9 again, and when the end portion Q is located at the dotted line ■, 0M decreases further to 7.
/9.
以下端部チが右すなわちX方向へ移動して行くにつれて
平均電荷QMは漸減し、最後に該端部チが点線■に至っ
た時点でQMは零となる。Thereafter, as the end portion Q moves to the right, that is, in the X direction, the average charge QM gradually decreases, and finally, when the end portion Q reaches the dotted line ■, QM becomes zero.
以上の経過によって平均電荷QMが呈する変化を書けば
これは第4図すの実線のごとく台形状となる。If the change in the average charge QM due to the above process is plotted, it will be trapezoidal as shown by the solid line in Figure 4.
前述のととく横描線の長さは画素列の長さeの9倍に選
ばれた状態を仮定したから、上記平均電荷QMが書く第
4図すの曲線における平坦部の長さebは画素列の長さ
eに等しくなる。As mentioned above, it is assumed that the length of the horizontal line is selected to be 9 times the length e of the pixel row, so the length eb of the flat part of the curve in Figure 4 drawn by the above average charge QM is the pixel length. The length of the column is equal to e.
これは画素列中の各画素が描線のX方向移動中に81回
にわたって同じ9qなる電荷を出力したためである。This is because each pixel in the pixel column outputs the same charge of 9q 81 times while the drawn line moves in the X direction.
めなみに描線長と画素列長とが等しげれば9個の画素が
同じ9qなる電荷を出力する機会は1回しか存在しない
から、この場合の6Mの変化は第4図す中において点線
りを1斜辺とする2等辺3角形状と化し、平担部はなく
なる。For reference, if the drawn line length and pixel column length are equal, there is only one chance for nine pixels to output the same charge of 9q, so the change in 6M in this case is shown by the dotted line in Figure 4. It becomes an isosceles triangular shape with one oblique side, and there is no flat part.
な、お、この第4図す中の斜辺部分つまりQMの漸増部
、漸減部のX方向の長さec、eaは共に9画素分の長
さeに等しいことになる。Incidentally, the lengths ec and ea in the X direction of the hypotenuse portions of the QM, that is, the gradually increasing portions and the gradually decreasing portions in FIG. 4, are both equal to the length e of 9 pixels.
さらに言えば上述の場合には第4図a中のたとえば画素
(1,1)の上下にそれぞれ位置する画素(o t 1
)および(2,l)は番地指定されていない。Furthermore, in the above case, the pixels (o t 1 ) located above and below the pixel (1, 1) in FIG.
) and (2,l) are not addressed.
このため前記十記号の縦描線部分二ならびにホの部分が
この両画素上に位置して該画素が共に電荷9qを出力し
ても該電荷は検出されずに終りしたがって前記平均電荷
QMには何等寄与することはない。Therefore, even if the vertical drawn line part 2 and the part E of the above-mentioned cross symbol are located on both pixels, and both of these pixels output a charge 9q, the charge will not be detected, and therefore nothing will be added to the above-mentioned average charge QM. It will not contribute.
これに対し、改めて上記画素列(LO)〜(1゜8)の
直上部に横方向に並ぶ前記(o、i)を含む図示しない
画素列(0,0)〜(0,8)を番地指定し直せば十記
号の縦描線のうちの前記二の部分が検出される。On the other hand, the pixel rows (0,0) to (0,8), not shown, including the above pixel rows (o, i) arranged horizontally directly above the pixel rows (LO) to (1°8), are set as addresses. If you specify it again, the above two parts of the vertically drawn lines of the ten symbol will be detected.
そして上記画素列(1t o )〜(i、s)の直下部
にやはり横方向に並ぶ前記(2,l)を含む図示しない
画素列(2,0)〜(2,8)を同じく番地し直した場
合にも同様に+記号の縦描線のうちホで示した部分が検
出される。Then, pixel rows (2,0) to (2,8), not shown, including the pixel rows (2,l), which are also arranged in the horizontal direction directly below the pixel rows (1t o ) to (i,s), are similarly addressed. Even when the image is corrected, the portion indicated by E among the vertically drawn lines of the + sign is detected in the same way.
しかしこれら各場合において上記縦描線部分二およびホ
がX方向へ移動しても検出される電荷は共に1画素分の
電荷9qでしかなく、これは黒レベルにある他の8画素
と前記白レベルにある1画素との計9画素について平均
されるため、結果としての平均電荷QMは179以上の
値をとることはない。However, in each of these cases, even if the vertical drawn line portions 2 and 5 move in the X direction, the detected charge is only the charge 9q for one pixel, and this is the same as the other 8 pixels at the black level and the white level. Since the average charge is calculated for a total of 9 pixels including 1 pixel in , the resulting average charge QM never takes a value of 179 or more.
つまり、縦描線の各部二またはホの部分から得られた平
均電荷QMは横描線から得られた平均電荷のほぼ10%
である。In other words, the average charge QM obtained from each part 2 or E of the vertically drawn line is approximately 10% of the average charge obtained from the horizontally drawn line.
It is.
ここで信号処理上よく用いられる手法すなわちスライス
レベルの設定を行い、たとえば7もしくは8画素分の電
荷に相当する第4図す中の一点鎖線ルなるレベルで第2
図の点P、の出力電圧をスライスするならば上記縦描線
部分二およびホは無視されて横描線のみが抽出できるこ
とになる。Here, we set a technique often used in signal processing, that is, a slice level. For example, at the level indicated by the dashed-dotted line in Figure 4, which corresponds to the charge of 7 or 8 pixels, the second
If the output voltage at point P in the figure is sliced, the vertically drawn line portions 2 and 5 will be ignored and only the horizontally drawn line will be extracted.
しかも第4図す中の曲線の漸増部分eaならびに漸減部
分ecは上記横描線の長手方向両端に画像の長いボケ部
分をもたらすものであるが、上記のようなスライスレベ
ルの最適設定によって、該横描線の端部イおよびチに近
い部分を明瞭な画像として再生することができる。Moreover, the gradually increasing part ea and the gradually decreasing part ec of the curve in Figure 4 cause long blurred parts of the image at both ends of the horizontal line in the longitudinal direction. Portions near the ends A and C of the drawn line can be reproduced as clear images.
以上では3×3画像を基本画素数として用いた例を記述
したが、このCIDによって行い5る処理は3×3に限
定されるものでなく、それ以上もしくはそれ以下にも拡
張し得るものすなわちn×m画素を基本画素数としても
行わせうるものである。Above, we have described an example using a 3x3 image as the basic number of pixels, but the processing performed using this CID is not limited to 3x3, but can be expanded to more or less. This can also be done using n×m pixels as the basic number of pixels.
その場合には前記2系統の検出用電荷増幅器AHI A
2の帰還容量としては与えられた拡張ケースに応じた値
の設定、換言すれば検出の際の重みづげを行う必要があ
るが、所望の重みづげを行わしめるには第2図中の11
,12もしくは21゜22なるスイッチの数ならびに0
11 j 012もしくは021.C2□なる容量の数
あるいはそれらの値の適切な設定によって容易に行いう
る。In that case, the two systems of detection charge amplifiers AHI A
It is necessary to set a value for the feedback capacitance of 2 according to the given expansion case, in other words, to increase the weighting during detection. 11
, 12 or 21°22 and the number of switches 0
11 j 012 or 021. This can be easily done by appropriately setting the number of capacitances C2□ or their values.
また第4図の説明では複数の画素を横1行に番地指定す
る場合を例にとって示したが、これと対照的に複数画素
を縦1列に指定することも、さらには斜め方向に指定す
ることも、番地指定回路6a 、7aの操作によって可
能である。Furthermore, in the explanation of Fig. 4, we took as an example the case where multiple pixels are specified in one row horizontally, but in contrast, it is also possible to specify multiple pixels in one column vertically, or even in a diagonal direction. This is also possible by operating the address designation circuits 6a and 7a.
たとえば画素の縦1列の番地指定を行なった場合には、
複数からなる十記号と一記号だけが分布/′シて書かれ
ている帳票面上のどこに十記号が点在するかを知る上で
効果がある。For example, if you specify the address of one vertical column of pixels,
The distribution of multiple ten symbols and only one symbol is effective in knowing where the ten symbols are scattered on the form surface where the ten symbols are written.
そのためには十記号の横描線を無視すると同時に縦描線
のみを抽出することによって該記号が十記号であるか一
記号であるかの判定を行えばよい。To do this, it is sufficient to ignore the horizontal drawn lines of the ten symbol and at the same time extract only the vertical drawn lines to determine whether the symbol is a ten symbol or one symbol.
類似の判定はアルファベットのV、XまたはWの認識が
、複数画素の1回もしくは数回にわたる斜め方向番地指
定と信号電荷の読み出しによって遂行し5る。Similar determination is performed by recognizing the alphabet V, X, or W by specifying the diagonal address of a plurality of pixels once or several times and reading out the signal charges.
以上に述べた本発明に係るOIDとその駆動方法によれ
ば、前記したような平滑化処理、端部検出、線分検出な
どの1次処理がOID面上で済ませ5るために、撮像系
全体としての処理速度の向上および連動する電子計算機
の必要記憶容量の低減が実現でき、実用上着しい効果が
期待できる。According to the OID and its driving method according to the present invention described above, the imaging system It is possible to improve the overall processing speed and reduce the required storage capacity of the interlocking computer, and is expected to have significant practical effects.
第1図は従来のOIDの構造を示す模式図、第2図は本
発明に係る新しいOIDの構造を示す模式図、第3図a
)bは第2図のCIDによる帳票面上におけるパターン
の端部検出手段を、また第4図a)bは同じく第2図の
0IDi/i:よる帳票面上の線分検出手段を、それぞ
れ説明するための図である。
1:受光面、2:単位画素、3at3bt3c:蓄積、
検出および感光用の各電極、4,5:母線、6at7a
:番地指定回路、10:電極3C群への電圧印加端子、
11.12,21.22.SW、。
SW2 t SWs pso=s4 t R1t R2
t R3:スイッチ、20:検出線路、31,32:直
流電源、011 j C12t 013 y 014
:容量、(o t o )〜(3ツ3)二画素番号、e
:画素列長さ、イ、チ:原映保の端部、ロ、ヌ、ト:原
映像の横描線の一部、二、ホ:原映像の縦描線の一部、
x、y:水平および垂直方向。Fig. 1 is a schematic diagram showing the structure of a conventional OID, Fig. 2 is a schematic diagram showing the structure of a new OID according to the present invention, and Fig. 3 a
) b is the pattern edge detection means on the form surface using CID in FIG. 2, and FIG. 4 a) and b are the line segment detection means on the form surface using 0IDi/i: in FIG. It is a figure for explaining. 1: Light receiving surface, 2: Unit pixel, 3at3bt3c: Accumulation,
Each electrode for detection and photosensitivity, 4, 5: bus bar, 6at7a
: address designation circuit, 10: voltage application terminal to electrode 3C group,
11.12, 21.22. SW. SW2 t SWs pso=s4 t R1t R2
t R3: Switch, 20: Detection line, 31, 32: DC power supply, 011 j C12t 013 y 014
: Capacity, (o t o ) ~ (3 3) 2 pixel number, e
: Pixel row length, A, C: End of the original image, B, N, G: Part of the horizontal drawn line of the original image, 2, E: Part of the vertical drawn line of the original image,
x, y: horizontal and vertical directions.
Claims (1)
マトリックス状に配列した受光面と所望番地の画像を指
定する水平および垂直方向番地指定手段を主体とする電
荷注入装置において、各画素中の検出電極は番地指定ス
イッチを介して信号電荷検出線路に接続され、該検出線
路は信号路導入切替スイッチを介して2系列の電荷増巾
器に接続され、それぞれの電荷増幅器の入出力端子間に
はリセットスイッチにより短縮されうる複数の帰還容量
が該容量のそれぞれに直列なスイッチを介して接続され
、かつ上記2系列の電荷増幅器出力が入力される差動増
幅器を具えたことを特徴とする電荷注入装置。1. In a charge injection device mainly consisting of a light-receiving surface in which unit pixels each having a photosensitive electrode, a storage electrode, and a detection electrode are arranged in a matrix, and a horizontal and vertical address specifying means for specifying an image at a desired address, The detection electrode is connected to a signal charge detection line via an address designation switch, and the detection line is connected to two series of charge amplifiers via a signal path introduction changeover switch. A charger comprising a differential amplifier in which a plurality of feedback capacitors that can be shortened by a reset switch are connected to each of the capacitors via a switch in series, and to which the outputs of the two series of charge amplifiers are input. Injection device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54126261A JPS5839390B2 (en) | 1979-09-29 | 1979-09-29 | charge injection device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54126261A JPS5839390B2 (en) | 1979-09-29 | 1979-09-29 | charge injection device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5650582A JPS5650582A (en) | 1981-05-07 |
JPS5839390B2 true JPS5839390B2 (en) | 1983-08-30 |
Family
ID=14930797
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54126261A Expired JPS5839390B2 (en) | 1979-09-29 | 1979-09-29 | charge injection device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5839390B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
LU86084A1 (en) * | 1985-09-20 | 1987-04-02 | Faco Sa | ELECTRIC MASSAGE APPARATUS |
JP2579218B2 (en) * | 1989-09-26 | 1997-02-05 | 日本特殊陶業株式会社 | Manufacturing method of artificial head |
-
1979
- 1979-09-29 JP JP54126261A patent/JPS5839390B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5650582A (en) | 1981-05-07 |
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