JPS5839333B2 - Information processing method and device - Google Patents

Description

[Detailed description of the invention] The present invention relates to an information processing method and device.

In recent years, with the development of LSI (Large Scale Integrated Circuit) and microcomputers, system prices have come down significantly.

For this reason, a method has been considered in which inexpensive microprocessors are functionally assigned and connected, and the microprocessors are operated systematically.

That is, a dedicated microprocessor is used for arithmetic control or input/output control of an information processing device, which has conventionally been configured with hardware logic, and device-specific exchanges are performed using software instructions possessed by the microprocessor.

This makes it easy to reduce costs and expand the functionality of the device.

A group of software instructions implemented by the microprocessor is also called firmware, and is usually composed of a microprogram.

These instruction sets are stored in a ROM or RAM, from which microinstruction groups corresponding to software instructions written by the user are read out and executed.

The outline of the above-mentioned information processing apparatus will be briefly explained using FIG.

As is clear from the figure, the arithmetic and control unit ACU12, the main memory MMU13, and the input/output control units 10C14 and 15 are connected to the common bus 11.

The common lot 11 is composed of a plurality of signal lines for address/data control.

Further, a keyboard, a serial printer, a floppy disk, and a CRT display (all not shown) are connected to the input/output control devices 10C14 and 15 as input/output devices.

Each device 12, 14, 15 connected to the common bus 11 is
Each has a microprocessor and a bus contention circuit, and when the common bus 11 is free, it contests and occupies the bus and transfers interrupt information to the device with which it wants to communicate.

Communication with other devices is performed in this manner. By the way, in the information processing device having the above configuration, when the ACU 12 is about to issue a request to use the common bus 11 by executing a bus access command (command to access the MMU 3 and input/output devices), or when the ACU 12 is about to issue a request to use the common bus 11, Other devices connected to the common bus 11 use the common bus 11 when issuing a use request, when executing an interrupt disabling instruction such as a jump instruction, or when the ACU 12 suspends instruction execution. When the ACU 12 is first contested and the ACU 12 is accessed, the interrupt is not accepted until the instruction execution processing of the ACU 12 is completed.

Therefore, this has been a cause of deterioration in the processing efficiency of the system.

The present invention has been made based on the above circumstances, and is based on the AC
When U executes a firmware instruction (for example, memory READ) that accesses each device connected to the bus, when an interrupt request becomes valid, activates the firmware execution timing, enables the output from the instruction execution prohibition circuit, and executes the firmware instruction. An object of the present invention is to provide an information processing device that improves throughput by having a configuration that blocks interrupt requests and accepts interrupt requests.

Hereinafter, the present invention will be explained in detail using FIG. 2 and subsequent figures.

FIG. 2 is a block explanatory diagram showing only extracted portions of the ACU that are related to the present invention.

In the figure, a transmitting/receiving circuit 31 is connected to an address bus 35, a data bus 36, and a control bus 37 via drivers/receivers 32, 33, and 34, respectively, and each of the buses 35, 36, and 37 is connected to a common bus 11, respectively. ing.

This transmitting/receiving circuit 31 reads information when executing a bus access command, and sends information corresponding to a write command to an address bus 35 and a control bus 37. The data bus 36 is switched to a receiving mode or a transmitting mode by a read command or a write command.

The above explanation is for data transfer from the mask (communication device) to the slave (communication partner device), but conversely, if an interrupt occurs from the slave to the mask, and the interrupt is accepted, the mask will control the Depending on the control information on the bus 37, the modes of the address bus 35 and data bus 36 are set to receive mode, or
Send data to 6.

Further, the interrupt level check circuit 39 monitors the data bus 36 via the driver/receiver 33 and checks the input interrupt level.

The control circuit 40 also controls the driver/receiver 32,34.
are connected to an address bus 35 and a control bus 37, respectively.

This control circuit 40 monitors the address bus 35 and control bus 37 to check whether its own device is being accessed.

Further, one of the output terminals of the control circuit 40 is connected to the control terminal of the transmission/reception circuit 310, and the other output terminal is connected to the first output terminal.
and one input terminal of a second AND gate 43.

Further, the output terminal of the interrupt level check circuit 39 is connected to the other input terminal of the AND gate 41 via the inverter gate 42 and also to the other input terminal of the AND gate 43.

The output terminal of the first AND gate 41 is the driver/
The output terminal of the second AND gate 43 is connected to the common bus 38 via the receiver 44, and the output terminal of the second AND gate 43 is connected to the timing control circuit 45.
0 control terminal.

When the bus access command is input, the timing control circuit 45 instructs the bus control circuit 46 to start bus contention, receives a bus access end signal from the bus control circuit 46, and ends the bus access command.

Also, when the interrupt request signal is input, the warpage timing,
Furthermore, the timing of bus access commands and interrupt prohibition commands is controlled.

Further, if the control circuit 40 and the interrupt level check circuit 39 are accessed and the interrupt level is interruptible,
It sends an interrupt signal to the timing control circuit 45, and returns a NACK signal to the common bus 11 if it is accessed and the interrupt level is disabled.

The timing control circuit 45 is connected to a bus control circuit 46 and to the common bus 11 via a driver/receiver 47.

Further, the other output terminal of the bus control circuit 46 is connected to the transmitter/receiver circuit 3.
1 is connected to the other control terminal of 1.

FIG. 3 is a detailed block diagram showing the internal configuration of the timing control circuit 45. As shown in FIG.

In the figure, the output terminal of the AND gate 43 is connected to the D input terminal of an interrupt accepting flip-flop 51 as an interrupt permission circuit, and the Q side output terminal of this flip-flop 51 is connected to the transmitting/receiving circuit 31.

This interrupt acceptance flip-flop 51 is set by an interrupt request signal determined by the interrupt level check circuit 39 to have an interrupt level higher than the interrupt level currently masked by the ACUI 2, and an interrupt is accepted.

Furthermore, the output terminal of the AND gate 43 is connected to the D input terminal of an instruction execution inhibiting flip-flop 52 serving as an instruction execution inhibiting circuit, and further connected to a timing generation circuit 53.

The instruction execution inhibiting flip-flop 52 is for temporarily placing the execution of a firmware instruction (bus access instruction) in a wait state when an interrupt is accepted by the flip-flop 51.

The output terminal of the AND gate 43 is connected to the inverter 5.
40 input terminal.

The output terminal of this inverter 54 is the Nantes gate 5.
5 is connected to the first input terminal of 5.

The output terminal of this Nant gate 55 is the NOR gate 5.
It is connected to one input terminal of 6.

The output terminal of this NOR gate 56 is the shift circuit 5γ.
is connected to the first input terminal of.

This shift circuit 57 is composed of, for example, four D-type flip-flops 58, 59, 60, and 61.

For example, 5N74175 manufactured by Texas Instruments is suitable as a flip-flop.

The Q-side output terminal of the flip-flop 58 constituting the shift circuit 57 is connected to the D input terminal of the flip-flop 59, and the Q output terminal of the flip-flop 58 is connected to the second input terminal of the Nandt gate 55.

Further, the Q output terminal of the flip-flop 59 is connected to the D output terminal of the flip-flop 60, and also to one input terminal of a Nandt gate 62, and further connected to one input terminal of an AND gate 63.

Further, the Q output terminal of the flip-flop 60 is connected to the D input terminal of the flip-flop 61 and to one input terminal of the Nandt gate 64.

Further, the Q output terminal of the flip-flop 61 is connected to the other input terminal of the Nant gate 64 and to one input terminal of the AND gate 65, and is further connected to the maintenance panel flip-flop 67 and C0M which constitute the timing wait circuit 75. It is connected to each clock input terminal of flip-flop 68.

Further, the Q output terminal of the C0M flip-flop 68 is connected to one input terminal of the NOR gate 69, and the Q output terminal of the maintenance panel flip-flop 67 is connected to the other input terminal.

The output terminal of the NOR gate 69 is connected to the third input terminal of the Nandt gate 55 and also to one input terminal of the NOR gate 70.

The other input terminal of this NOR gate 70 is connected to the other input terminal of the Nands gate 65.

The output terminal of the NOR gate 70 is the instruction execution prohibition circuit 5.
The D input terminal of the circuit 52 is connected to the D input terminal of the interrupt reception flip-flop 51.

The Q output terminal of this flip-flop 52 is connected to the other input terminal of a Nant gate 63, and the output of this AND gate 63 is provided within the ACUI 2 as a clock signal for the arithmetic circuit.

Therefore, when the timing circuit is stopped or the instruction execution prohibition circuit (flip-flop 52) is set, instruction execution is interrupted and the device is in a wait state.

Further, the output terminal of an AND gate 65 and the output terminal of a Nants gate 62 are connected to the clock input terminal and the clear input terminal of the interrupt acceptance flip-flop 51, respectively.

Next, a timing chart will be explained.

4a"e shows a basic timing chart of the information processing apparatus in the embodiment of FIG. 3.

In the figure, a is a clock signal output from the oscillator γ1.

Timing signals Tlt T2 and T35 T4 are output from the shift circuit 570 and the flip-flop 58 to flip-flop 61, respectively.

The timing signal T1 shown in b is obtained from the Q output terminal of the flip-flop 58 of the shift circuit 57, this high level signal of T1 is input to the D input terminal of the flip-flop 59, and the timing signal T2 shown in is obtained from the Q output terminal of

Then, the timing signal T2 is applied to the D of the flip-flop 60.
The timing signal T3 shown in d is applied to the input terminal at 7
It is obtained from the Q output terminal of lip-flop 60.

The timing signal T3 from this Q output terminal is applied to the D input terminal of the flip-flop 61, and the timing signal T3 is applied to the D input terminal of the flip-flop 61.
4 is obtained.

The timing signal T3 from the Q output terminal of the flip-flop 60 and the timing signal T4 obtained from the Q output terminal of the flip-flop 61 are applied to the Nant gate 64.

As a result, the output signal of this Nantes gate 64 becomes low level, this signal is applied to the Nantes gate 56, and the output terminal of the Nantes gate 56 outputs a low level signal.

This low level signal is applied to the D input terminal of the flip-flop 51.

As a result, the timing signal T1 falls and is sequentially applied to the flip-flops 59, 60, 61, and the timing signal T2. T3. T4 falls.

This constitutes one machine cycle, and each firmware instruction is executed based on this basic cycle.

First, explanation will be given using the timing chart shown in FIG.

Figure 5 shows that the ACU is
12 is a timing chart showing that timing No. 12 enters the "wait" state.

In the figure, a is a waveform diagram of the clock signal, b to e are timing signals T1. T2. T3. Waveform diagram of T4, f is waveform diagram of calculation control signal, g is C0M flip-flop 68
h is an output signal waveform diagram, and h is a BAT signal waveform diagram.

In the figure, a bus access instruction is executed during a period A1, and the next instruction is executed during a period A2.

First, based on the basic clock signal, the timing signal T,
, T2. T3. T rises one after another.

At this time, the timing signal T4 is applied to the clock terminal of the C0M flip-flop 68 and the clock terminal of the maintenance panel flip-flop 67.

When the bus access command is executed, the transmitter/receiver circuit 31
A COM signal is input to the C0M flip-flop 68 from the C0M flip-flop 68.

As a result, the output of the C0M flip-flop 680G is inverted and applied to one input terminal of the NOR gate 69, and the other input terminal of the maintenance flip-flop 680G is inverted and applied to one input terminal of the NOR gate 69.
7 Q outputs are added.

Then, the output signal of this NOR gate 69 is applied to the third input terminal of the NAND gate 55 as a high level signal.

Further, the input signal (second input terminal) supplied to the Nant gate 55 via the inverter 54 is a high level signal when there is no interrupt.

Furthermore, the output of a flip-flop 5800 is applied to the first input terminal of the Nant gate 55, and since this signal becomes high level, the AND condition is satisfied, and a low level signal is output as the output of the Nant gate 55. can get.

This low level signal is applied to one input terminal of the NOR gate 56.

A low level signal is obtained as the output signal of this NOR gate 56.

This low level signal is applied to the D input terminal of flip-flop 58.

As a result, the timing signal T1. T2. T3. T4 falls sequentially, the output of the AND gate 63 becomes low level, and therefore the timing of the ACU 12 becomes a wait state.

This state is maintained while C0M flip-flop 68 is set.

(FIG. 5g) When the bus access is completed, a response signal from the common bus 11 is applied to the clear input terminal of the C0M flip-flop 68, as shown in h, thereby resetting the flip-flop 68.

FIG. 6 is a timing chart showing that the timing of the ACU12 is put into a "wait" state by pressing the stop switch located on the maintenance panel.

a to e are clock signals as well as respective timing signals T1. T2. T3. It is T4.

First, based on the basic clock signal, the timing signal T1. T2. T3. T4 rises.

Then, as in the case of COM instruction execution, the timing signal T
4 is applied to the clock terminal of maintenance panel flip-flop 67.

When the stop switch of the maintenance panel is pressed as shown in b, the signal output from the Q side terminal of the maintenance panel flip-flop 67 rises as shown in g.

This output signal is applied to the flip-flop 58 of the shift circuit 57 via the NOR gate 69 and the NAND gate 55.

As a result, the output signal of the NOR gate 56 becomes a low level signal, and this low level signal is transmitted to the flip-flop 58.
is applied to the D input terminal of

As a result, the timing signal T1 of the shift circuit 57. T2.
T3. T4 becomes low level one after another, and the AND gate 63
Since the output also becomes low level, the timing of ACU12 becomes a wait state.

FIG. 6 is a timing chart showing the operation when an interrupt, which will be described later, occurs during the wait state.

When an interrupt request is outputted via the AND gate 43, a low level signal is applied to the Nandt gate 55 via the inverter 54, thereby causing the timing signal T1. T2. T3. T4 rises sequentially.

By the way, the interrupt request signal is D of the flip-flop 52.
Since it is supplied to the input terminal and the D input terminal of the flip-flop 51, the flip-flop 52 has T1. The flip-flop 51 is set at the timing T4.

When the flip-flop 52 is set, its Q output turns off the AND gate 63 and the timing of ACU12 continues in the wait state.

When the flip-flop 51 is set and an interrupt is accepted, the interrupt request signal is cut off and the timing signal T1. which is the output of the shift circuit 57 is output again. T2. T3. T4 becomes low level one after another until the flip-flop 67 is reset, and execution of the instruction is interrupted during this time.

The maintenance panel flip-flop 67 is reset by turning on the start switch shown in i, so that the output signal of the maintenance panel flip-flop 67 falls as shown in g.

As a result, the ACU 12's timing signal T1. T2. T3
．． T4 becomes the state of no level and no level in sequence.

That is, the timing WAIT state of ACU12 is released and the next firmware instruction is executed.

For example, 5 top ways to use the maintenance panel
5TA while keeping 5w1tch ON”
Firmware instructions can be executed one by one by repeatedly pressing RT 5w1tch.

Furthermore, synchronization of interrupt requests from each device connected to the common bus 11 for bus contention and the timing circuit is performed as follows.

First, the interrupt level of the interrupt request signal for bus contention from each device is checked by the interrupt level check circuit 39.

As a result of the check, if the interrupt level is lower than the interrupt level currently masked by the ACU 12, the interrupt request will not be accepted.

In this case, ACUl2 returns a NACK signal to l0C14 or MMU 13.

On the other hand, if the interrupt request signal is at a higher interrupt level than the currently masked interrupt level, the interrupt request signal is output from the AND gate 43 and sent to the interrupt reception flip-flop 5.
It is added to the D input terminal of 1.

Then, the interrupt request signal is set in the interrupt reception flip-flop 51 by the timing signal T4.

When the interrupt request signal is set in the interrupt acceptance flip-flop 51, an interrupt operation end signal is sent to the device that outputs the interrupt request signal.

Next, the operation of the ACU12 will be described when each device on the common bus 11 acquires the bus first and accesses the ACUI 2 while the ACU12 is executing a C0M instruction, that is, a bus access instruction.

FIG. 7 shows that the flip-flop 68 is set by executing the C0M instruction.
The output signal is sent to a bus request circuit (not shown), and the operation timing is shown when an interrupt request signal is generated before this bus request circuit acquires the common bus 11.

That is, when an interrupt request signal is output from the AND gate 43 at the timing signal T4 as shown in j, the interrupt reception flip-flop 51 is set, and its output signal rises as shown in i.

Also, since the bus access instruction is being executed, the COM control flop 68 rises at timing T4 as shown in g.

Also, the interrupt request signal is transmitted to the instruction execution prohibition flip-flop 52.
is applied to the D input terminal of

A shift circuit 5707 and a flip-flop 58 are connected to the flip-flop input terminal of this instruction execution prohibition flip-flop 52.
A timing signal T1 is applied.

As a result, the timing signal T1 rises as shown in e.

As a result, a low level signal is applied to one side of the AND gate 63.

Therefore, the output signal T2 of flip-flop 59 is applied to the other input terminal of AND gate 63.

As a result, the output signal of the AND gate 63 is turned off, and A
The timing of the CU 12 is in a wait state.

Then, the output signal of the Nant gate 62 is supplied to the clear input terminal of the interrupt acceptance flip-flop 51, and the output signal of the flip-flop 51 falls as shown at i.

and timing signal T1. T2. T3. T4 falls sequentially.

And each timing T, , T2. T3. Because T4 is set with C0M flip-flop 68 lol
The ACU12 is in the ait state and the timing is wait.
Continue the state.

Thereafter, when the bus access is completed, the bus access termination (BAT) signal rises as shown in h, and this BAT signal is applied to the clear input terminal of the C0M flip-flop 68, which is reset and then rises as shown in g. Go down.

At this falling timing, the instruction execution inhibiting flip-flop 62 falls as shown by l.

The instruction execution inhibit flip-flop 52 operates only when the C0M flip-flop 68 is set or when the stop switch on the maintenance panel is pressed, that is, when the maintenance panel flip-flop 67 is set.

FIG. 8 is a timing chart showing an interrupt operation from the bus during execution of an interrupt disabling instruction.

During execution of an interrupt disabling instruction, ie, a jump instruction, the output of the interrupt level check circuit 39 acts via the AND gate 43 so that the interrupt request signal is not set in the interrupt enable flip-flop 51.

That is, a low level signal for jumping is supplied to the AND gate 65 and the timing signal of T4 is turned off, so that no signal is applied to the clock input terminal of the flip-flop 51.

As a result, the interrupt request signal is not set in flip-flop 51.

Then, as shown in j, after the jump instruction is executed, the jump signal becomes high level, and at the rising edge of the timing signal T4, the interrupt acceptance flip-flop 51 activates the AND gate 43.
It accepts interrupt request signals obtained via.

As a result, the output signal of the interrupt acceptance flip-flop 51 rises as shown in g.

The timing signals T2 and T3 output from the Nant gate 62 become low level, and this low level signal is applied to the clear input terminal of the interrupt reception flip-flop 51.

As a result, the output signal of the interrupt acceptance flip-flop 51 falls as shown in g.

Then, when the stop switch on the maintenance panel is pressed while the interrupt prohibition command is being executed, the timing circuit 5 of the ACU 12
If an interrupt request signal is generated while 3 is in the wait state, the timing circuit is activated, thereby executing the next instruction.

Since a jump signal is applied as a reset signal to the instruction execution inhibition flip-flop 52 via the NOR gate 70, the execution of the instruction is not inhibited by this flip-flop 52.

Therefore, in this case, the interrupt request signal is accepted while executing the instruction.

In the information processing device configured as described above, the AC
Bus 1 is accessed by U12 by executing a bus access command.
1 or when attempting to request the use of bus 11.
If an interrupt request to acquire the bus occurs from another device on the bus 11 when a request to use the bus is issued, the timing signal for executing the firmware's bus access command is
state, interrupt execution of the instruction, and accept the interrupt.

Also, when the ACU 12 is executing an interrupt prohibition instruction, the interrupt is placed in a waiting state until the execution of the interrupt prohibition instruction is completed.
After the instruction processing is completed, the interrupt can be accepted.

Therefore, the throughput of the information processing device is improved, and processing is more effectively distributed.

Also, while the information processing unit is executing a command, the timing of the ACU 12 can be adjusted by using the stop switch on the maintenance panel.
Since the configuration is based on the ait state, it is more effective for firmware debugging and the like.

Note that this invention is not limited to the above embodiments,
Various modifications can be made without departing from the gist of the invention.

[Brief explanation of drawings]

Fig. 1 is a block explanatory diagram showing an overview of an information processing device to which the present invention is applied, Fig. 2 is a block explanatory diagram showing main parts of an arithmetic control circuit, and Fig. 3 is a detailed block explanation of a timing control circuit. Fig. 4a ”'-e are FIG.
Timing chart showing the output signal of the timing generation circuit shown in 4, Fig. 5 a = h is C0M of the firmware.
A timing chart showing how the arithmetic and control unit enters the wait state in response to a command.
Timing chart showing how to enter the ait state, No. 7
Figure a"e is a timing chart showing an interrupt from the bus during the execution of a firmware COM instruction, Figure 8a =
j is a timing chart showing an interrupt operation during execution of, for example, a jump instruction as an interrupt-disabled instruction. 11... Bus, 12... Arithmetic control unit, 13... Main memory, 14, 15...
Input/output control device, 39... interrupt level check circuit, 45... timing control circuit, 51...
...Interrupt acceptance flip-flop, 52...
... Flip-flop for inhibiting instruction execution, 57...
・Shift circuit, 67...5TOP flip-flop, 68...C0M flip-flop, 71
......oscillator.

Claims (1)

[Scope of Claims] 1. In an information processing device in which devices including arithmetic control units that are controlled by firmware and mutually accessible are commonly connected via a bus, the arithmetic control units have timings for executing firmware instructions. a timing signal generating means for generating a signal; a timing signal interrupting means for interrupting the timing signal generation by the timing signal generating means; and an interrupt level detecting means for checking the level of an interrupt request issued from another device connected to the bus. , an interrupt reception means for accepting an interrupt request signal output from this circuit, and an instruction execution prohibition means for prohibiting execution of the firmware instruction, and executes a firmware instruction for accessing each device connected to the bus. When the output by the interrupt accepting means is enabled due to the above interrupt request, the execution timing of the firmware instruction is activated, the output by the instruction execution inhibiting means is enabled, and the execution of the firmware instruction is blocked, and the above interrupt request is disabled. An information processing method characterized by reception. 2. An information processing device in which devices including arithmetic and control units that are controlled by firmware and mutually accessible are commonly connected via a bus, and the arithmetic and control units are one of the following a, b, c, d, It is characterized by having a timing control circuit composed of e and f. 80 oscillator, a timing signal generation circuit that generates a timing signal by applying the clock output from the 60 oscillator to a shift register, and executes a firmware instruction based on this timing signal, c. A first flip-flop that is set/reset by a manual operation command and thereby instructs to suspend or restart the operation of the timing signal generation circuit; a second flip-flop that is set at a certain timing when the 61 interrupt request signal arrives; While the flip-flop, e, and the first flip-flop are set, the first gate circuit, f, which operates to restart the timing signal generation circuit by the interrupt request signal, is set. A third flip-flop is enabled only when the next firmware instruction is to be executed.