JPH08180027A - Arbitration circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To reduce the wait time during competition and improve the processing efficiency of the system. [Configuration] When a low-speed MPU 2 outputs a memory selection signal b to the shared memory 10 and an access request is made, M
The arbitration circuit 7 sends the memory control signal e to the memory 10 in accordance with the access timing of the PU 2, and at the time of read access, the memory access permission signal g is sent to the latch circuit 21 and to the buffer circuit 22 in the case of write access. Send the permission signal h. The latch circuit 21 temporarily holds the read data output from the memory 10 onto the bus 11 and then transfers the read data to the bus 4 on the MPU 2 side. The buffer circuit 22 transfers the write data sent from the MPU 2 onto the bus 4 onto the bus 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arbitration circuit used when two processors having different access speeds are connected to a shared resource such as a memory or a bus.

[0002]

2. Description of the Related Art Conventionally, there are the following two types of arbitration circuits used when connecting two processors having different access speeds to a shared resource such as a memory and a bus. (1) Method of controlling by dedicated request signal (request signal) and permission signal (acknowledge signal) This is to connect a plurality of processors on a common data bus and address bus respectively, and share resources on the bus as well. Normally, one main processor (hereinafter, main processor) uses the bus and the shared resource after being connected. When another processor wants to use the bus and the shared resource, it outputs a request signal (request signal) to the main processor. On the other hand, the main processor returns an enable signal (acknowledge signal) and sends an address bus, data bus, etc. when the operation during its own processing is completed and the right to use the bus can be transferred. To high impedance. The processor that has received the permission signal performs the necessary access processing using the bus because the use of the bus is recognized.

(2) Method of controlling by response signal (ready signal) In this method, a plurality of processors are connected to independent buses, shared resources are also connected on independent buses, and further each processor is connected. A buffer circuit is installed between the bus and the bus to which the shared resource is connected. Each processor accesses the shared resource by enabling the function of the buffer circuit only during access and logically connecting the bus of the processor and the bus of the shared resource. In addition, when multiple processors try to access the shared resource at the same time, the processor that started the access normally starts the access, and the processor that tries to start the access later starts the response signal input to the processor. The (ready signal) is made inactive by setting it in a wait state, and after the access of the processor that started the access is completed, the wait state is released and the access is executed.

FIG. 4 is a block diagram showing a configuration of a conventional example using the latter method, and FIG. 5 is a timing chart showing its operation. In this conventional example, as shown in the figure, a high-speed microprocessor (MPU) 1 and a low-speed microprocessor (MPU) 2 are dedicated MPs.
It is connected to the address decoders 5 and 6 and the transceiver circuits 8 and 9 via the U-side data buses 3 and 4. The transceiver circuits 8 and 9 are connected to a shared memory 10 via a data bus 11. Furthermore, these M
The PU 1, the address decoders 5 and 6, the transceiver circuits 8 and 9, and the memory 10 are connected to the arbitration circuit 7 via signal lines, respectively.

As shown in FIG. 5, the operation of the arbitration circuit 7 includes MPU1 and MPU via address decoders 5 and 6, respectively.
The memory selection signals a and b sent from 2 are monitored at the rising edges of the respective system clocks, and the right of use is given to the one who has detected the signal first. When the memory selection signals a and b are sent at exactly the same time, the signal b is given priority and the usage right is given to the MPU 2. Further, when the access to the memory 10 by the MPU1 and MPU2 competes with each other,
During access period of low-speed MPU2 (time t1 to t2)
Becomes a wait state even if an access request is issued from the MPU 1. Here, as shown at the time of access conflict in the right part of the figure, the worst case is when the access start of MPU2 is earlier than the access start of MPU1 by one clock, and the MPU1 has the longest waiting time (time t3 to t).
4). Meanwhile, in the illustrated example, the wait state T
14 1w are inserted.

[0006]

However, each of these conventional methods has the following problems. (1) In the former request signal / permission signal system, the main processor yields the shared bus and allows the other processors to use it, during which time the main processor cannot use the bus and shared resources. Further, there is a problem that extra time is required for the procedure for surrendering the bus using the request signal / permission signal, and the processing capacity is reduced accordingly. (2) The latter method of controlling the response signal is a preemptive priority method. Therefore, if the processing speed of one processor is particularly slower than that of the other, the access time of the slow processor becomes long, and in the meantime, a high speed processor Even if the access is started, there is a problem that the high-speed processor does not exhibit its full performance because it has to wait for a long time.
This is exactly the worst case case in FIG.

(3) Similarly, in the latter method based on response signal control, when contention occurs, it is necessary to extend the access time of the processor with a slow request to put it in the wait state. There was a restriction that it could not be applied to processors that do not have it. The present invention has been made to solve the above problems,
The purpose is to shorten the waiting time of the high-speed processor when contention occurs, improve the processing efficiency related to the access of the entire system, and use a processor with a fixed access time for the low-speed processor. To provide an arbitration circuit.

[0008]

In order to achieve the above object, a first aspect of the present invention is provided between two processors having different access speeds from each other and a shared memory bus-connected to the two processors. When the memory selection signal for the shared memory is output from the processor, the transceiver transmits a control signal for permitting access to the shared memory and is installed on the data bus connecting the access request processor and the shared memory. In the arbitration circuit that sends a data transfer permission signal to the circuit,
As a transceiver circuit on the low-speed processor side, a latch circuit that holds read data sent from the shared memory on the data bus and then transfers it to the low-speed processor side, and write data sent on the data bus from the low-speed processor The buffer circuits that transfer the data to the shared memory side are installed in parallel on the data bus. A means for transmitting a control signal for permitting access to the shared memory and transmitting a permission signal for data transfer to the latch circuit in the case of read access and to the buffer circuit in the case of write access. And

According to a second aspect of the present invention, in the first aspect, the access permission control signal and the data transfer permission signal are set at a timing when a predetermined number of system clocks of the high speed processor are counted after the memory selection signal is output from the low speed processor. It is characterized by occurring.

[0010]

According to the first aspect of the present invention, when the memory selection signal is output from the low speed processor to the shared memory and an access request is made, the control signal for permitting access is shared in synchronization with the access timing of the low speed processor. Simultaneously with the transmission to the memory, a data transfer permission signal is sent to the latch circuit for read access and to the buffer circuit for write access. In the latch circuit to which the data transfer permission signal is sent, the read data sent from the shared memory onto the data bus is once held and then transferred to the low-speed processor side for reading.
Similarly, the write data sent from the low-speed processor onto the data bus is transferred to the shared memory side and written via the buffer circuit to which the data transfer permission signal is sent.

In the second aspect of the invention, after the memory selection signal is output from the low speed processor, the system clock of the high speed processor is counted by a predetermined number, and the access permission control signal and the data transfer permission signal are generated based on the count.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a system to which the present invention is applied, and FIG. 2 is a timing chart showing its operation. As shown in the figure, this system is composed of two microprocessors having different access speeds and a memory shared by them. That is, the high speed microprocessor (MPU) 1
It is connected to the address decoder 5 and the transceiver circuit 8. The transceiver circuit 8 is connected to the shared memory 10 via the bus 11.

The low speed microprocessor (MPU) 2 is connected to an address decoder 6, a latch circuit 21 and a buffer circuit 22 via a bus 4. Latch circuit 2
1, the buffer circuit 22 is connected to the memory 1 via the bus 11.
Connected to 0. The buses 3, 4, 11 are each composed of a data bus and an address bus. Also,
The address decoders 5 and 6 are connected from the MPUs 1 and 2 to the bus 3,
The addresses output to 4 are decoded to generate memory selection signals a and b, which are sent to the arbitration circuit 7. When the memory selection signals a and b are input, the arbitration circuit 7 arbitrates and gives the exclusive right to either one of the MPUs.

Here, as shown in FIG. 2, the MPUs 1 and 2 form a read or write access cycle by the time corresponding to four system clocks. In this embodiment, the MPU1 has clock cycle T1.
1, T12, T13, T14, MPU2 is T21, T22, T23,
Each access cycle is constituted by T24. Since the high-speed MPU1 has an access speed four times that of the low-speed MPU2, one access cycle of the MPU2 has a length corresponding to 16 system clocks of the MPU1.

In the read operation of the MPU 1, the data on the bus 3 is read at the trailing edge of the cycle T14, and in the write operation, the data is output on the bus 3 in the cycles T13 and T14. Similarly, in the read operation of MPU2, cycle T24
The data on the bus 4 is read at the trailing edge, and the data is output on the bus 4 in cycles T23 and T24 in the write operation. Further, the memory 10 is read or written within the time corresponding to three system clocks of the MPU 1.

Next, the access of the MPU 1 will be described in detail. The memory selection signal a is input to the arbitration circuit 7 and MP
When U1 obtains the right to use the memory 10, the arbitration circuit 7 sends a memory access permission signal c, which is a data transfer permission signal, to the transceiver circuit 8. Similarly, the ready signal f is sent to the MPU 1 and the memory control signal e is sent to the memory 1
Sent to 0 respectively. This memory access permission signal c
Specifies the direction of the transceiver circuit 8 and permits data transfer between the bus 3 and the bus 11. That is, in the case of read, the data is transferred from the bus 11 to the bus 3, and in the case of write, the data is transferred from the bus 3 to the bus 11.

The ready signal f is a signal for terminating the access of the MPU1 and the result of the arbitration is the MPU1.
If you want to wait for
It is activated when PU1 can be accessed.
The memory control signal e is a signal for writing data on the bus 11 to the memory 10 or outputting data on the bus 11.

Similarly, when the memory selection signal b is input to the arbitration circuit 7 and the MPU 2 obtains the right to use the memory 10, the arbitration circuit 7 sends the memory control signal e to the memory 10 and reads it. In the case, to the latch circuit 21,
When the memory access permission signal g which is a data transfer permission signal is a write, the memory access permission signal h which is a data transfer permission signal to the buffer circuit 22 is written.
Are sent respectively. When the memory access permission signal g is sent to the latch circuit 21, the read data output from the memory 10 onto the bus 11 is once held in the latch circuit 21, sent to the bus 3 side, and read into the MPU 2. When the memory access permission signal h is sent to the buffer circuit 22, the write data sent from the MPU 2 onto the bus 3 is sent to the bus 11 side via the buffer circuit 22 and written in the memory 10.

In the arbitration circuit 7, arbitration of contention is performed based on the access request from the MPU 2. That is, as shown in FIG. 2, the MPU 2 reads the data at the trailing edge of the cycle T24 and the write timings at the cycles T23 and T24.
The period of T22 is an extra time, and it is meaningless to precede the memory control signal e and the memory access permission signals g and h during this period. Therefore, the system clock of the MPU 1 is counted from the timing when the memory selection signal b is input, and the memory control signal e and the memory access permission signal g or h are output for a period of 3 clocks from the 10th clock, The occupied time of the bus (memory bus) is set to the minimum required time between times t1 and t2.

Further, when the MPU 2 reads the data, the data needs to be present on the bus 4 until the end of the cycle T24. Therefore, the latch circuit 21 holds the data and outputs it on the bus 4 during that period. As a result, MPU2
If there is an access request from MPU1 while accessing
Put U1 on standby. Further, when there is an access request from MPU1 during the access request of MPU2, if there is a margin before the access start of MPU2, MPU1 is accessed first, and if there is no margin before the access start, MPU1
Wait 1

As a result, the MPU 2 has no wait and the input of the ready signal becomes unnecessary, and it becomes possible to use a microprocessor of the type having a fixed access time as the MPU 2. It should be noted that contention under the same conditions as the worst case shown in the conventional example of FIG. 5 is shown as a case of access contention on the right side of FIG.
MP even after the access request is made to
U1 accesses first without waiting.

FIG. 3 shows the worst case in the competition of this embodiment. First, memory selection signal b from MPU2
Is output, the system clock of MPU1 is counted, and at time t1 when eight clocks are counted, MP
The memory selection signal a is output from U1. However, at this point, only the time of 2 clocks remains until the 10th clock pulse at which the MPU 2 starts the access, and therefore the access of MPU 1 which requires the time of 3 clocks is impossible. Therefore, the ready signal f to the MPU1 is made inactive, and the MPU1 is placed in the wait state until time t2 when the memory use of the MPU2 ends. The wait state T1W at this time has a length of 5 clocks, which is less than half the time compared to the worst case of the conventional example of FIG.

As described above, in the embodiment of the present invention, in the system in which the high-speed MPU1 and the low-speed MPU2 compete with each other, the wait time of the high-speed MPU1 is shortened, so that the processing capacity of the MPU1 can be suppressed. it can. In the embodiment of the present invention, the high speed MPU 1 and the low speed M
I applied the arbitration of the shared memory 10 with PU2,
The same can be applied to shared resources such as bus systems and networks.

[0024]

As described above, according to the first invention,
As a transceiver circuit on the low-speed processor side, a latch circuit and a buffer circuit are installed in parallel on the data bus, and when the low-speed processor outputs a memory selection signal to the shared memory to request access, the low-speed processor The control signal for permitting access to the shared memory is transmitted at the same access timing as the above, and the data transfer permission signal is sent to either the latch circuit or the buffer circuit. As a result, the waiting time of the high speed processor is shortened correspondingly, and the operating efficiency of the high speed processor is not impaired. Further, since the arbitration is performed by giving priority to the access of the low-speed processor, the low-speed processor has no wait, and the processor having the fixed access time can be used for the low-speed processor.

According to the second aspect of the present invention, the system clocks of the high speed processors are counted by a predetermined number to generate the access permission control signal and the data transfer permission signal. By controlling the access timing,
Further, the operating efficiency of the system is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment according to the present invention.

FIG. 2 is a timing chart showing the operation of FIG.

FIG. 3 is a timing chart showing a worst case in competition of the embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional example.

FIG. 5 is a timing chart of a conventional example.

[Explanation of symbols]

 1 High-speed microprocessor (MPU) 2 Low-speed microprocessor (MPU) 3, 4 Bus 5, 6 Address decoder 7 Arbitration circuit 8 Transceiver circuit 10 Memory 11 Bus 21 Latch circuit 22 Buffer circuit

Claims (2)

[Claims] 1. When a memory selection signal for the shared memory is output from one processor between two processors having different access speeds and a shared memory bus-connected to both processors, the shared memory is notified to the shared memory. Arbitration circuit that transmits a control signal for permitting access by a processor and sends a permission signal for data transfer to a transceiver circuit installed on the data bus connecting the access request processor and the shared memory. As a transceiver circuit on the side, a latch circuit that temporarily holds the read data sent from the shared memory to the data bus and then transfers it to the low-speed processor side, and the write data sent from the low-speed processor to the data bus on the shared memory Side buffer circuits on the data bus. Parallel to each other, and when a memory selection signal is output from the low-speed processor to the shared memory and access is requested, a control signal for permitting access to the shared memory at the access timing of the low-speed processor. And an arbitration circuit for transmitting a data transfer permission signal to a latch circuit for read access and to a buffer circuit for write access. 2. The arbitration circuit according to claim 1, wherein the access permission control signal and the data transfer permission signal are generated at the timing when a predetermined number of system clocks of the high speed processor are counted after the memory selection signal is output from the low speed processor. An arbitration circuit characterized by: