JPS5839067A - Non-volatile semiconductor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] The present invention relates to nonvolatile semiconductor memories.

Semiconductor memory has the advantage of being smaller than magnetic memory and the like, and information can be written and read at high speed. The amount of information stored in memories such as magnetic memory, which used to be small, is rapidly increasing thanks to the recent remarkable semiconductor technology IWK. In the case of non-volatile semiconductor devices, the amount of storage information C or less (referred to as the degree of integration) is increasing as well. However, electrically rewritable non-volatile semiconductor memory generally requires high voltage resistance due to the high operating voltage. It has the disadvantage that it cannot improve the degree of integration. The reason why non-volatile semiconductor devices require a high operating voltage is that the programming voltage required to store information is high. Therefore, in order to realize a highly integrated nonvolatile semiconductor memory, it is desired to develop a nonvolatile semiconductor memory with a low programming voltage.

FIG. 1 is a sectional view of an embodiment of a conventional nonvolatile semiconductor memory. The operating principle is N type M memory transistor.
OS F XT (MefaL-0xide-B
mmiconductforBa1d-Effect
-Transaisfor) will be explained. An N-type source region 2 and a drain region 3 are provided on a P-type semiconductor substrate 1.
A first gate insulating film 4t- is formed on the surface of the semiconductor substrate 10 between
In this structure, a floating gate electrode 6 is provided through the floating gate electrode 6, and a control gate electrode 7 is provided on the floating gate electrode 6 with a second gate insulating film 8 interposed therebetween. Further, a partially thin insulating film 5 (film thickness: fax) is provided between the drain region 3 and the floating gate insulating film 6. The floating gate electrode 6 covers all the insulating films included in the first and second gate electrodes M4, 8 and the thin insulating film 5'. The control gate electrode 7 is connected to other regions (source region 2, drain region 3
, the capacitive coupling is stronger with the second gate insulating film 8 than with the substrate 1). That is, the control gate electrode 7 is an electrode that controls the potential of the floating gate electrode 6.

Reading the memory of the nonvolatile semiconductor memory shown in FIG. Writing (injecting electrons from the substrate element to the floating gate electrode 6) and erasing (injecting electrons from the floating gate F electrode 6 to the substrate l)
Explain the principle of "flowing into the water".

First, the reading method will be explained. drain region 3
A constant voltage drain voltage vDt- is applied to the control gate voltage 1
When voltage V6o is applied to i7, a drain current, Xo, flows as shown in FIG. (hereinafter referred to as the channel)
is easy to reverse, and the drain current xD suddenly flows at a certain control gate voltage V6@. The threshold voltage vI above the control gauge voltage at which this drain current Xv suddenly begins to flow
Call t.

This threshold voltage VffX is determined by the fact that when a large number of electrons are injected into the floating gate electrode 6 (writing), the channel is inverted (
On the other hand, when a large number of electrons flow out from the floating gate electrode 6, the channel tends to invert, so the threshold voltage Vqw decreases as shown in FIG. By applying a constant voltage for reading to the gate electrode 7 and detecting the channel conductance at Y, the memory of the memory can be read out in accordance with the electron density in the floating gate electrode.

Next, writing to a memory device will be explained. When a write voltage Vv, which is a positive voltage with respect to the drain electrode 3, is applied to the control gate electrode 7, almost the write voltage Vv is applied to the thin insulating film 5 on the drain region 3. When V voltage is applied to the thin insulation layer 5, a tunnel current flows from the floating gate electrode 7 to the drain region 3 through the thin insulation film 5 as shown by arrow 5 in FIG. injected into. The larger the electric field generated in the thin insulating film, the more
A large tunnel current flows.

Next, for erasing, which is the opposite of writing, an erase voltage V#, which is a positive voltage, is applied to the control gate electrode 7 and the drain electric field 3. Then, as in writing, approximately voltage V# is applied to the thin insulation M5 between the floating gate electrode 7 and the drain electrode 3. A tunnel current ar flows as indicated by the arrow M in the figure. That is, electrons in the floating gate electrode 7 exit (erase) the drain region 3Kfi.

As explained above, the write and erase voltages (
Both program voltages are collectively referred to as program voltages), which greatly depend on the type and film thickness fox of the thin insulating film 5. Third
The figure is a graph showing the dependence of the program voltage Vp on the film thickness foπ when the thin insulating film 5 is a silicon dioxide film. The thinner the film thickness fox is, the smaller vp can be.

However, if the film thickness is thin, the memory retention characteristics will deteriorate, so it can only be made as thin as /@s = 200 μm.As a result, the programming voltage vp cannot be reduced, making it difficult to use highly integrated non-volatile memory. It was making it difficult.

The present invention was made in order to overcome the above-mentioned conventional problems and to provide a floating gate non-volatile memory with excellent retention characteristics and a low programming voltage suitable for high integration. This is what we provide.

The nonvolatile semiconductor memory of the present invention will be explained in detail using FIGS. 1 and 4.

In the nonvolatile semiconductor memory of the present invention, the optimum film and thickness of the thin oxide film from which electrons are injected or drained from the floating gate electrode are set. In a nonvolatile semiconductor memory having the structure as shown in FIG. 1, if the thin oxide film thickness fox is reduced to, for example, 60 μm, the memory retention time will shorten (elapse) as the number of rewrites increases, as shown in FIG. Also, the film thickness is 1
In the 005 memory, as shown in FIG. 4, the retention time increases as the number of rewrites increases. Therefore, when 60 μm is prepared, as shown in FIG. The dependence was small. This optimal film thickness slightly differs depending on the process conditions. Although it varies depending on the process conditions, this optimal film thickness fox falls within the range of 70 μm < fore < 90 μm. If the memory is made thicker, a non-volatile semiconductor memory with a long retention time and a low programming voltage can be formed.

It goes without saying that the embodiments of the present invention are not limited to memories having the structure as shown in FIG. The present invention is applicable to any nonvolatile semiconductor memory having a structure in which electrons can be injected or flowed out to a floating gate electrode by tunnel injection means through a thin oxide film.

As described above, according to the present invention, in a floating gate type non-volatile semiconductor memory in which electrons are injected or flowed out (by tunnel injection means) through a thin oxide film to a floating gate electrode, a thin oxide film that eliminates the decrease in retention time due to the number of rewrites. By setting the minimum film thickness to 90 μm, where 70 μm<fO, it is possible to increase the number of rewrites and reduce the programming voltage without deteriorating the retention characteristics.As a result, The breakdown voltage that needs to be taken into consideration in the design of memory cells is small], and high integration becomes possible through miniaturization technology for non-volatile semiconductor devices.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of one embodiment of a general conventional nonvolatile semiconductor memory, and FIG. 2 is a graph diagram showing transistor characteristics of the memory. FIG. 3 is a graph showing the relationship between the thin oxide film thickness of the memory of FIG. 1 and the programming voltage. FIG. 4 is a graph showing the dependence of memory retention time on the number of rewrites for explaining the present invention. 1°. P-type semiconductor substrate 2°. M-type source region 3°. Summer type drain region 4°. First gate insulating film 5°. Thin insulation film 6°. Floating gate electrode 70. control gate electrode 8; Second gate insulating film 9°. Field insulating film 2a e 3 a -*Aluminum electrode Applicant Daini Seikosha Co., Ltd. Agent Patent Attorney Mogami Fig. 1 Fig. 2

Claims (1)

Claims: A source of a second conductivity different from the first conductivity type provided in a first semiconductor region of the first conductivity type. a drain region and at least the source. on the drain/region and the source. In the memory cell in which at least a part of the constituent element is a floating gate electrode provided in the first semiconductor memory between the drains with an insulating film interposed therebetween, a part of the insulating film is
A first voltage is applied to the first semiconductor region in the source or drain region as a thin silicon dioxide film of 0 to 90 μm in thickness in the floating gate electrode through the thin silicon dioxide H. the amount of charge in the floating gate electrode is detected by applying a second voltage to the drain region with respect to the first semiconductor region; A non-volatile conductor memory characterized by: