JPS583242A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for manufacturing a semiconductor device. More particularly, it applies to a semiconductor*to manufacturing method that can prevent the deterioration of characteristics caused by isolation between elements. In general, in a semiconductor device with one integrated circuit or large-scale integrated circuit, - A large number of circuit elements such as transistors, diodes, and resistors are incorporated into the semiconductor pellet to form a circuit function. In this case, each element must be isolated (isolated) so that these elements are not electrically influenced by each other.

As a method to perform this isolation attack, (a) PNI
I combination separation, e1 insulating layer separation, e1 air layer separation, etc. have been proposed. Figures 1II and 2 show isolation carbon by the conventional method □ In this method, the p-type silicon group II I K n ”m Jl-inclusive diffusion region 2 is formed by diffusion, and then a channel cut region 3 is formed between #Taai-gome diffusion region 2.2. Next, the device silicon is formed by a conventional method.
An epitaxial layer 11141 is grown, and then an oxide film 5 is formed on the epitaxial layer 4. Next, by reactive ion etching (RIE) K using 8F, the U groove 6
Here, reactive ion etching includes reactive ion beam etching, reactive sputter etching, reactive plasma etching, etc. Next, a 5-ins film 7 is formed. When such an isolation structure M and t is adopted, there are disadvantages in that the parasitic capacitance increases and the withstand voltage between the collector and the substrate decreases.

The gS diagram shows ein rasin by another conventional method.

By this method, the Fip-original silicon base f 8 K n+ type collapsed diffusion region IIt is diffused, and then the h-silicon self-epitaxial layer 10 is grown by a conventional method, and then an oxide film 111ft is formed on the epitaxial layer 10. Then by reactive ion etching using SF, n
"11m1 in the diffusion area 9 to form KUIII12.

Furthermore, impurities are introduced all around the circumference of the U groove 12 using a gas diffusion method to form a p+ channel stopper 13. If such an isolation-based structure is adopted, it is possible to create an ICt with a high degree of integration, but the p+ channel stopper 13 has a wide range of l! Parasitic capacitance increases due to the close contact.

For this reason, there is a drawback that the switching speed is low.
−.

The purpose of the 0ll- is to prevent the increase in stirrup parasitic capacitance in such a situation and to achieve complete isolation between elements without reducing the switching speed. The semiconductor substrate [KUIll] is formed, an insulating film is then formed on the entire surface of the ULlll, and then an impurity of the conductivity type is introduced by ion implantation to form an impurity region only at the bottom of the MU#lI. Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 4 to 6.

Pus! Semiconductor substrate 14Kn” WIM! included diffusion region 15
After diffusing, an n-type epitaxial layer 16 is grown. Next K 5ift I! 37 and Sis round membrane] 8
to debossed. Next, the 5ins film 17 and the 51iN4 film 18t were removed from the area scheduled for ion implantation.
Reactive ion etching using - is performed to form the old layer 19 up to the semiconductor substrate 4. Here, reactive ion etching includes reactive ion beam etching, reactive sputter etching, reactive plasma etching, and the like. Next, oxidation No. 11 was carried out at about 1000°C in a hydrochloric acid atmosphere.
Then, an oxide film 20 having a circumference WK of, for example, 500 to 2000 Å is formed around the U groove. The thickness of this oxide film is the same at the bottom and side portions 4 of the U-groove. The oxidation stage m is used when the epitaxial layer has low resistance or when ion implantation is performed.
When using ions that are implanted shallowly during the process, such as Bd, this is a process that does not require I'llF, and when the epitaxial layer has a high resistance, or when using ions that are implanted deeply such as B+, it is necessary. ve process. In addition, it is possible to form a thermal nitride film by heating in an N6 atmosphere instead of a thermal oxidation layer.Also, it is possible to form an insulating film by vapor phase growth. Boron ions (B+) are implanted in order to form. The ion implantation is performed directly with respect to UwK, for example, using an acceleration voltage of 60 keys and an implanted ion dose (3-'') 5X.
Ion implantation is performed directly into the U-groove, but ion implantation into the groove part with a deviation of 0-101 is also possible), but when the oxide film thickness W1 deviation is 10°. Masking film thickness for side ion implantation My FiM
y = W/aia 10 = 5.8 W, so even if ions are implanted at the bottom of the trench, they will not pass through the oxide film in the groove. The semiconductor device is manufactured by filling the tIU trench with the tIU and planarizing it, and performing the necessary normal operations.

That's all for the present invention! As described above, a conductivity type semiconductor substrate 1 [KU groove is formed by reactive ion etching, an oxide film is formed on the surface of the U groove from place wK, and then an impurity of the conductivity type is introduced by ion implantation 1c, Since the impurity region is formed only at the bottom of the trench, complete isolation can be obtained and parasitic capacitance can be reduced, so that the switching speed will not be slowed down.

[Brief Description of the Drawings] Figures 1 to 3 are explanatory diagrams of the manufacturing process of a semiconductor device according to a conventional method, and Figures 4 to 6 are explanatory diagrams of the manufacturing process of a semiconductor device showing an embodiment of the present invention. It is a diagram. 14...p-type semiconductor substrate, 15...n
"ll placed diffusion region, 16... nW epitaxial connection, 19... oxide film, 20... U
Groove, 21... Impurity region O Patent applicant Fujitsu Kinsha Patent application agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney 1) Yuuben Yuki 1st attorney Akira Yamaguchi Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. Form a υ groove on the conductive wrinkled semiconductor substrate by etching, then form an insulating film on the entire surface of the U groove in step 11, and then introduce impurities of the conductivity type by ion implantation. The semiconductor 5IIlf) characterized in that an impurity region is formed only at the bottom of the IIU groove.
Production method.