JPH0685269A - Manufacture of reverse-conducting insulated-gate bipolar transistor - Google Patents

Abstract

PURPOSE:To facilitate the integration of a reverse-conducting IGBT and a diode in one semiconductor element and improve the reliability and achieve the size reduction by a method wherein the manufacture of the IGBT is started from a substrate which is to be a high resistance layer. CONSTITUTION:The manufacture of a reverse-conducting IGBT is started from an n-type F2 silicon wafer 30. Phosphorus ions are implanted selectively to form an n<+>-type diffused layer and annealing is performed to form an n<+>-type layer 20 on the collector side of the wafer 30. The remaining part of the wafer 30 is used as an n-type layer 3. Further, boron ions are implanted selectively and annealing is performed to form a p<+>-type layer 1 on the collector side of the n<+>-type layer 20. The remaining part of the n<+>-type layer 20 is used as an n<+>-type buffer layer 2. Then a window 13 is formed in an oxide film on the surface of the p<+>-type layer 1 by a photoprocess. At that time, the emitter side and the collector side are aligned with each other. That is, the diode part and the IGBT part must be aligned with each other along a vertical direction. Then phosphorus ions are implanted from the collector side and annealing is performed to form an n<++>-type layer 10 which is deeper than the p<+>-type layer 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reverse conducting IG in which an insulated gate bipolar transistor (IGBT) and a diode connected in anti-parallel thereto are incorporated in the same semiconductor element body.
The present invention relates to a method for manufacturing BT.

[0002]

2. Description of the Related Art When a diode is connected to an IGBT in anti-parallel, the IGBT chip and the diode chip are conventionally incorporated in the same module, and the chips are connected by bonding a conductive wire. But I like this
The GBT module has a large size, and a large number of connecting conductors are arranged in the module, which causes a problem in reliability such as disconnection of the connecting conductors. This problem,
This can be solved by integrating the diode in the IGBT chip.

FIG. 2 shows a sectional structure of an IGBT, p⁺Ko
N on the rectifier layer 1⁺Laminated via the buffer layer 2
The p layer 4 is selectively formed on the surface layer of the n layer 3 and the p layer 4 is formed.
Selectively on the surface layer of⁺The emitter layer 5 is formed
It And the n layer 3 and the n of the p layer 4 ⁺Part sandwiched by layer 5
A gate electrode 7 is provided on the gate insulating film 6
And p⁺Collector electrode 8, n in contact with the layer⁺Emi
The emitter electrode 9 that is commonly contacted with the
Each is provided. And, the gate electrode has a gate terminal G
, The collector terminal C to the collector electrode, and the emitter electrode
The emitter terminals E are respectively connected to the. I like this
GB p⁺Layer 1, n⁺The buffer layer 2 and the n layer 3 are
It is generally formed at the stage of aha. sand
Wow, p⁺Low p-type layer with a thickness of about 500 μm as layer 1
Resistor CZ silicon wafer is used as the substrate and 10
n type with a thickness of about μm and low resistance⁺Layer 2 epitaxy
Stacking by the jar method, and further n-type and high resistance n layer 3 on top of it.
Stacked by the epitaxial method. That is, p⁺Layer on board
Expanded from a wafer with a two-step epitaxial growth layer
The p-layer 4, n⁺Form layer 5.

When an anti-parallel connection diode is built in such an IGBT chip, a sectional structure as shown in FIG. 3 is obtained.
That is, the n ⁺⁺ layer 10 in contact with the collector electrode 8 is connected to the n ⁺ layer 2, and the p layer 11 in contact with the emitter electrode 9 is formed on the surface layer of the n layer 3.

[0005]

However, since the thickness of the p ⁺ layer 1 of the IGBT of FIG. 2 is 500 μm or more as described above, it is 500 μm or more to form the n ⁺⁺ layer by the diffusion method. A diffusion depth of is needed, which is not possible in practice. It is an object of the present invention to provide a method of manufacturing a reverse conducting IGBT which can solve the above problems and incorporate a diode into an IGBT chip.

[0006]

In order to achieve the above-mentioned object, the present invention is directed to a first layer of the first conductivity type, which is laminated directly or with a buffer layer having a high impurity concentration of the second conductivity type. The third layer of the first conductivity type is selectively formed on the surface layer of the second layer of the second conductivity type having a low impurity concentration, and the fourth layer of the second conductivity type is selectively formed on the surface layer of the third layer. Selective to the IGBT part formed by forming the second conductive type buffer layer or the second conductive type fifth and second surface layers having a high impurity concentration reaching the second conductive type buffer layer or the second layer from the surface of the first layer. In a method of manufacturing a reverse conducting IGBT having a diode portion formed by forming a sixth layer of the first conductivity type in the same semiconductor element body, a semiconductor substrate of the second conductivity type and a low impurity concentration is used as the second layer, The first layer is formed on one side either directly or via a buffer layer, and impurities are introduced from the surface of the first layer. The fifth layer is formed by, a third layer by impurity introduction from the other side of the semiconductor substrate, and to form a fourth layer and fifth layer. Then, it is effective to manufacture the semiconductor substrate by the floating zone (FZ) method.

Further, it is effective to form the first layer or the first layer and the buffer layer by introducing impurities from the surface of the semiconductor substrate or by epitaxial growth on the surface of the semiconductor substrate.

[0008]

[Function] Since the semiconductor substrate is used as the second layer, the first layer is 10 μm thick by introducing impurities or by epitaxial growth.
It can be controlled to a certain thickness. Therefore, the fifth layer of the diode portion penetrating the first layer can be easily formed by introducing impurities from the surface of the first layer.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, the same parts as those in FIGS.
Figure showing the cross-sectional structure marked with and corresponding impurity concentration distribution
The embodiments of the present invention will be described with reference. Figure 1 (a)
In the example of (d), the n-type has a specific resistance of 100 Ω · cm and a thickness of 250.
We started with a 30 μm FZ silicon wafer [Fig.
 ]. Then n⁺In order to form a diffusion layer, P (phosphorus) ions are removed.
Dose 5 × 10¹⁴/cm², 1250 with acceleration voltage of 100 keV
Annealed for 2 hours at ℃, surface concentration on the collector side
5 x 10¹⁶/cm³, With a diffusion depth of 15 μm⁺Formed layer 20
[Fig. (B)]. The remaining part of the wafer 30 is the n-layer 3.
It In addition, the dose of B (boron) ions is 1 × 10¹⁶/
cm², Accelerating voltage 50keV, annealing at 1250 ℃ for 30 minutes
The surface concentration of 1 × 10 on the collector side.¹⁹/cm ³, Expansion
Dispersion depth 5μm p⁺Layer 1 was formed [(c) in the figure]. n⁺
The remaining part of layer 20 is n⁺It becomes the buffer layer 2. Then
p⁺A window 13 is formed in the oxide film 12 on the surface of the layer 1 by a photo process.
I got it. At this time, align the emitter side and collector side
Need to That is, the diode section and the IGBT
The parts must be aligned vertically. Therefore, both sides
Use a device such as a photomask aligner to
At the same time as opening the window 13
I will use this marker to
Used when. Then, P ion implantation from the collector side
And p by annealing⁺N deeper than layer 1⁺⁺Formed layer 10
[Fig. (D)]. Then, the conventional IGBT manufacturing method
Similarly, ion implantation from the emitter side and annealing
As shown in FIG. 3, p layer 4, p layer 1 and n⁺Emi
Layer 5 was formed.

In the embodiment shown in FIG. 4, an FZ silicon substrate is used.
Was started from a two-stage epitaxial wafer using. Basis
The plate has a specific resistance of 100 Ω · cm and a thickness of 230 μm to be the n-layer 3.
FZ silicon wafer with n on it⁺Epitaxial
Layer 2 has a specific resistance of 0.1 Ω · cm, thickness of 10 μm, p⁺Epitaxy
The layer 1 has a specific resistance of 0.02 Ω · cm and a thickness of 10 μm.
(a)]. After this, the same work as described in Fig. 1 (d) is performed.
N of the diode part ⁺⁺A layer 10 was formed [(b) in the same figure].
Further, the structure of FIG.
It was

Reverse conduction IG obtained by the above embodiment
It was confirmed that each of the BTs has a withstand voltage of 1500 V, and both the collector current and the saturation voltage have the same characteristics as the IGBT of the conventional reverse conducting IGBT in which the emitter side is formed with the same mask pattern. It was also confirmed that the diode operation was performed normally. It should be noted that the same can be applied to a structure having no n ⁺ buffer layer 2 interposed.

[0012]

According to the present invention, it is possible to integrate the IGBT and the diode in the same semiconductor element, which has been considered impossible in the past, by starting the manufacturing of the reverse conducting IGBT from the substrate which becomes the high resistance layer. Thus, a highly reliable reverse conducting IGBT having a small size was obtained.

[Brief description of drawings]

FIG. 1 is a sectional structural view and an impurity concentration distribution diagram showing a part of a manufacturing process of a reverse conducting IGBT according to an embodiment of the present invention in the order of (a) to (d).

FIG. 2 is a sectional structure view of an IGBT.

FIG. 3 is a cross-sectional structure diagram of a reverse conducting IGBT.

FIG. 4 is a sectional structural view and an impurity concentration distribution diagram showing a part of a manufacturing process of a reverse conducting IGBT according to another embodiment of the present invention in the order of (a) and (b).

[Explanation of symbols]

1 p ⁺ layer 2 n ⁺ buffer layer 20 n ⁺ layer 3 n layer 30 silicon wafer 4 p layer 5 n ⁺ emitter layer 6 gate insulating film 7 gate electrode 8 collector electrode 9 emitter electrode 10 diode part n ⁺⁺ layer 11 diode part p layer

Claims (4)

[Claims] 1. A surface layer of a second layer of the second conductivity type, which is laminated directly on the first layer of the first conductivity type or through a buffer layer of the second conductivity type having a high impurity concentration. An IGBT part formed by forming a third layer of the first conductivity type and a fourth layer of the second conductivity type selectively on the surface layer of the third layer, and a buffer of the second conductivity type from the surface of the first layer. A diode formed by selectively forming a sixth layer of the first conductivity type on the surface layer of the fifth layer of the second conductivity type high impurity concentration reaching the first layer or the second layer and the surface layer of the second layer In the method of manufacturing a reverse conduction insulated gate bipolar transistor having, a semiconductor substrate of a first conductivity type and a low impurity concentration is used as a second layer, and the first layer is formed on one side thereof directly or through a buffer layer, The fifth layer is formed by introducing impurities from the surface of one layer, and the other side of the semiconductor substrate is formed. Third layer, the manufacturing method of the reverse conducting insulated gate bipolar transistor, and forming a fourth layer and fifth layer by an impurity introduction al. 2. The method for producing a reverse conducting insulated gate bipolar transistor according to claim 1, wherein the semiconductor substrate is produced by a floating zone method. 3. The method for manufacturing a reverse conducting insulated gate bipolar transistor according to claim 1, wherein the first layer or the first layer and the buffer layer are formed by introducing impurities from the surface of the semiconductor substrate. 4. The method for producing a reverse conducting insulated gate bipolar transistor according to claim 1, wherein the first layer or the first layer and the buffer layer are formed by epitaxial growth on the surface of the semiconductor substrate.