JPS63175463A - Bi-MOS integrated circuit manufacturing method - Google Patents
Bi-MOS integrated circuit manufacturing methodInfo
- Publication number
- JPS63175463A JPS63175463A JP62007787A JP778787A JPS63175463A JP S63175463 A JPS63175463 A JP S63175463A JP 62007787 A JP62007787 A JP 62007787A JP 778787 A JP778787 A JP 778787A JP S63175463 A JPS63175463 A JP S63175463A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- type
- region
- integrated circuit
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
- H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Landscapes
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はバイポーラトランジスタとＭＯＳトランジスタ
とを同一基板上に形成するバイＭＯＳ集積回路の製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a bi-MOS integrated circuit in which a bipolar transistor and a MOS transistor are formed on the same substrate.
バイポーラトランジスタとＭＯＳ）ランジスタとを同一
基板上に形成したバイＭＯＳ集積回路は、バイポーラト
ランジスタの大電流駆動、高速動作、低雑音と、ＭＯＳ
）ランジスタの高入力インピーダンス性、高集積度とを
同時に実現できることから近年多くの試みが報告されて
いる。A biMOS integrated circuit, in which a bipolar transistor and a MOS transistor are formed on the same substrate, has the high current drive, high speed operation, and low noise of the bipolar transistor, and the high current drive, high speed operation, and low noise of the MOS
) Many attempts have been reported in recent years because it is possible to simultaneously achieve high input impedance and high integration of transistors.
第２図に縦形ＰＮ、Ｐ）ランジスタとＰチャネルＭｏＳ
トランジスタとを含む従来のバイＭＯ３ＩＣの断面図を
示す。以下にこのバイＭＯ３ＩＣの製造方法を説明する
。Figure 2 shows vertical PN, P) transistors and P channel MoS.
1 shows a cross-sectional view of a conventional bi-MO3 IC including a transistor. The method for manufacturing this bi-MO3IC will be explained below.
まず、Ｐ−形シリコン下地板１にＮ＋形埋込層２−１．
２−２、Ｐ′″形埋込層３−１〜３−４を形成し、Ｎ形
エピタキシャル層４（図では４−１〜４−４）を形成し
た半導体基板に、縦形ＰＮＰトランジスタのＰ＋形コレ
クタ領域５とＰ＋形雄絶縁分離領域５１〜５−４とを、
Ｐ＋形埋込層３−１〜３−４と接触するように同時に形
成する。First, an N+ type buried layer 2-1.
2-2. On the semiconductor substrate on which the P'' type buried layers 3-1 to 3-4 and the N type epitaxial layer 4 (4-1 to 4-4 in the figure) are formed, the P+ type collector region 5 and P+ type male insulation isolation regions 51 to 5-4,
It is formed simultaneously so as to be in contact with the P+ type buried layers 3-1 to 3-4.
次いで所定の形状をしたシリコン窒化膜を形成し、この
窒化膜を耐酸化用マスクとして、素子分離用酸化１１ｉ
７を形成する。次に、ゲート酸化膜８を形成後、ゲート
多結晶シリコン層９を形成する。次いで、縦形ＰＮＰト
ランジスタのＮ＋形ベースコンタクト領域１０を形成し
、縦形ＰＮＰトランジスタのＰ＋形エミッタ領域１１お
よび■〕“形コレクタコンタクト領域１２とＰチャネル
ＭＯＳトランジスタのＰ＋形ソース、ドレイン領域１３
とを同時に形成する。次に、絶縁膜層１４を形成して、
最後に酸化膜８を開口し、これを通じて縦形ＰＮＰ）ラ
ンジスタのベース、エミッタ、コレクタ電極１５．１６
．１７およびＰチャネルＭｏｓ＋−ランジスタのソース
、ドレイン電極１８を形成する。Next, a silicon nitride film having a predetermined shape is formed, and using this nitride film as an oxidation-resistant mask, an oxide 11i for element isolation is formed.
form 7. Next, after forming a gate oxide film 8, a gate polycrystalline silicon layer 9 is formed. Next, an N+ type base contact region 10 of the vertical PNP transistor is formed, a P+ type emitter region 11 of the vertical PNP transistor, a collector contact region 12 of the P channel MOS transistor, and a P+ type source and drain region 13 of the P channel MOS transistor.
and are formed at the same time. Next, an insulating film layer 14 is formed,
Finally, the oxide film 8 is opened, and the base, emitter, and collector electrodes 15 and 16 of the vertical PNP transistor are opened through it.
．． 17 and source and drain electrodes 18 of a P-channel Mos+- transistor are formed.
上述した従来のバイ、 Ｍ ＯＳ集積回路の製造方法で
は、例えば縦形ＰＮＰトランジスタのベース領域が低濃
度のＮ形エピタキシャル層で形成されているため、エミ
ッタ接地電流増幅率（以下ｈＦＥと記す）の電流特性が
悪いという欠点がある。すなわち、低電流においてはｈ
ＦＥのリニアリティが悪く、高電流においてはｈＰＥの
電流に対する伸び（以下Ｉ Ｃｔｍａｘと記す）が小さ
い。また、利得帯域幅積（以下ｆｔと記す）が小さく、
高周波特性が悪いという欠点もある。In the above-described conventional method for manufacturing a bi-MOS integrated circuit, for example, since the base region of a vertical PNP transistor is formed of a lightly doped N-type epitaxial layer, the current of the common emitter current amplification factor (hereinafter referred to as hFE) is It has the disadvantage of poor characteristics. That is, at low current h
The linearity of FE is poor, and the elongation of hPE with respect to current (hereinafter referred to as I Ctmax) is small at high currents. In addition, the gain bandwidth product (hereinafter referred to as ft) is small,
It also has the disadvantage of poor high frequency characteristics.
一方、ＰチャネルＭＯＳトランジスタに関しては、チャ
ネル領域がエピタキシャル層で形成されているため、エ
ピタキシャル層の比抵抗のばらつきによるしきい電圧（
以下Ｖ、ｈと記す）のばらつきが大きく、Ｖｔｂの制御
性が悪いという欠点がある。On the other hand, regarding P-channel MOS transistors, since the channel region is formed of an epitaxial layer, the threshold voltage (
The disadvantage is that there are large variations in V and h (hereinafter referred to as V and h) and poor controllability of Vtb.
本発明の目的は、縦形ＰＮＰ （又はＮＰＮ＞１−ラン
ジスタにおける高周波特性およびｈＦＥの電流特性を改
善し、かつＰ（又はＮ）チャネルＭＯＳトランジスタに
おけるしきい電圧の制御性を改善することの可能なバイ
ＭＯ３集積回路の製造方法を提供することにある。An object of the present invention is to improve the high frequency characteristics and current characteristics of hFE in a vertical PNP (or NPN>1-transistor) and to improve the controllability of the threshold voltage in a P (or N) channel MOS transistor. An object of the present invention is to provide a method for manufacturing a bi-MO3 integrated circuit.
本発明のバイＭＯ３集積回路の製造方法は、第１、第２
導電形領域をそれぞれ選択的に形成した第１導電形半導
体下地板に第２導電形エピタキシャル層を成長させて第
１．第２導電形埋込層を設けた半導体基板に縦形ＰＮＰ
（又はＮＰＮ＞）ランジスタとＰ（又はＮ）チャネル
ＭＯ９）ランジスタを設けたバイＭＯ３集積回路を形成
するに際し、前記バイポーラトランジスタのベース領域
の少なくとも一部とＭｏＳトランジスタを形成するウェ
ル領域とを同一工程で選択的に不純物を導入して形成す
るというものである。The method for manufacturing a bi-MO3 integrated circuit of the present invention includes a method for manufacturing a bi-MO3 integrated circuit.
A second conductivity type epitaxial layer is grown on a first conductivity type semiconductor base plate on which conductivity type regions are selectively formed. Vertical PNP on semiconductor substrate with second conductivity type buried layer
(or NPN>) transistor and a P (or N) channel MO9) transistor, when forming a bi-MO3 integrated circuit provided with a transistor, at least a part of the base region of the bipolar transistor and a well region where the MoS transistor is formed are formed in the same process. It is formed by selectively introducing impurities.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の一実施例を説明するた
めの工程順に配置した半導体チップの断面図である。FIGS. 1(a) to 1(d) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining one embodiment of the present invention.
まず、第１図（ａ）に示すように、Ｐ−形半導体（シリ
コン）下地板１にＮ＋形領領域Ｐ＋形領領域選択的に形
成したのち、Ｎ形エピタキシャル層４を成長させて、Ｎ
＋形埋込層２−１．２−２、Ｐ＋形埋込層３−１〜３−
４を設けた半導体基板を形成する６次に、第１図（ｂ）
に示すように、縦形ＰＮＰ）ランジスタのＰ＋形コレク
タ領域５とＰ”形絶縁分離領域５−１〜５−４とを、そ
れぞれその下方にあるＰ＋形埋込層３−１〜３−４と連
続するように同時に形成する。次いで縦形ＰＮＰトラン
ジスタのベースの一部となるＮ＋形ベース領域６−２と
、ＰチャネルＭＯＳトランジスタのＮ＋形ウェル領域６
−１とを、例えばリンのイオン注入により形成する。な
お、６−１゜６−２は後述する縦形ＰＮＰ）ランジスタ
のエミッタ領域１１およびＰチャネルＭｏＳトランジス
タのソース、ドレイン領域１３より深く形成する。次に
、シリコン窒化膜を用いて選択的に厚い素子分離用酸化
膜７を形成する。次いで、第１図（Ｃ）に示すように、
ゲート酸化膜８、Ｎ＋形のゲート多結晶シリコン層９を
形成する。次に、第１図（ｄ）に示すように、縦形ＰＮ
Ｐ）ランジスタのＮ＋形ベース領域６中にＮ”形ベース
コンタクト領域１０を、例えばヒ素のイオン注入により
形成する。次いで、Ｎ＋形ベース領域６−２中に縦形Ｐ
ＮＰトランジスタのＰ＋形エミッタ領域１１およびＰ“
形コレクタコンタクト領域１２を、ＰチャネルＭＯ３）
ランジスタのＮ＋形ウェル領域６−１中にＰ＋形ソース
、ドレイン領域１３を、例えばボロンのイオン注入によ
り同時に形成する。最後に、第１図（ｄ）に示すように
、絶縁膜１４を形成し、ゲート酸化膜８を選択的に開口
し、これを通じて縦形ＰＮＰトランジスタのベース、エ
ミッタ、コレクタ電極１５．１６゜１７およびＰチャネ
ルＭＯＳトランジスタのソース、ドレイン電極１８を形
成する。First, as shown in FIG. 1(a), after selectively forming an N+ type region P+ type region on a P- type semiconductor (silicon) base plate 1, an N type epitaxial layer 4 is grown.
+ type buried layer 2-1, 2-2, P+ type buried layer 3-1 to 3-
6 to form a semiconductor substrate provided with 4. Next, FIG. 1(b)
As shown in FIG. Next, an N+ type base region 6-2, which becomes a part of the base of the vertical PNP transistor, and an N+ type well region 6 of the P channel MOS transistor are formed simultaneously.
-1 is formed by, for example, phosphorus ion implantation. Note that 6-1 and 6-2 are formed deeper than the emitter region 11 of a vertical PNP transistor and the source and drain regions 13 of a P-channel MoS transistor, which will be described later. Next, a thick element isolation oxide film 7 is selectively formed using a silicon nitride film. Next, as shown in FIG. 1(C),
A gate oxide film 8 and an N+ type gate polycrystalline silicon layer 9 are formed. Next, as shown in FIG. 1(d), vertical PN
P) forming an N'' type base contact region 10 in the N+ type base region 6 of the transistor by, for example, ion implantation of arsenic;
P+ type emitter region 11 and P“ of the NP transistor
type collector contact region 12, P-channel MO3)
P+ type source and drain regions 13 are simultaneously formed in the N+ type well region 6-1 of the transistor by, for example, boron ion implantation. Finally, as shown in FIG. 1(d), an insulating film 14 is formed and the gate oxide film 8 is selectively opened, through which the base, emitter, collector electrodes 15.16° 17 and Source and drain electrodes 18 of the P-channel MOS transistor are formed.
なお、ＰチャネルＭＯ８）ランジスタのＶｔｂ制御のた
め、Ｎ＋形ウェル領域６−１には例えばボロンをイオン
注入することにより表面濃度の適正化を行なってもよい
。In order to control the Vtb of the P-channel MO8) transistor, the surface concentration may be optimized by implanting, for example, boron ions into the N+ type well region 6-1.
この実施例はＮ＋形ウェル領域６−１、Ｎ＋形ベース領
域６−２をリンのイオン注入により同一工程で形成する
以外は従来例と同じである。This embodiment is the same as the conventional example except that the N+ type well region 6-1 and the N+ type base region 6-2 are formed in the same process by phosphorus ion implantation.
又、導電型を逆にすれば縦形ＮＰＮ トランジスタとＮ
チャネルＭＯ３）ランジスタの場合に本発明を適用し得
ることは言をまたない。Also, if the conductivity types are reversed, it becomes a vertical NPN transistor and an NPN transistor.
It goes without saying that the present invention can be applied to channel MO3) transistors.
以上説明したように本発明は、縦形ＰＮＰ （又はＮＰ
Ｎ）トランジスタのベースの一部となるＮ” （又は
Ｐ”）形ベース領域と、Ｐ（又はＮ）チャネルＭＯＳト
ランジスタのソース、ドレイン領域を含むＮ” （又
はＰ＋）形ウェル領域とをＮ（又はＰ）形エピタキシャ
ル層表面より同時に形成することによって、縦形ＰＮＰ
（又はＮＰＮ）トランジスタにおける高周波特性およ
びｈＦＥの電流特性を改善でき、かつＰ（又はＮ）チャ
ネルＭＯＳトランジスタにおけるしきい電圧の制御性を
改善できる効果がある。As explained above, the present invention provides vertical PNP (or NP
N" (or P") type base region, which becomes part of the base of the transistor, and N" (or P+) type well region, which includes the source and drain regions of the P (or N) channel MOS transistor. Or by simultaneously forming the P) type epitaxial layer from the surface, vertical PNP
This has the effect of improving the high frequency characteristics of the (or NPN) transistor and the current characteristics of the hFE, and improving the controllability of the threshold voltage in the P (or N) channel MOS transistor.
縦形ＰＮＰ （又はＮＰＮ） トランジスタにおいては
、エピタキシャル層に比べて高濃度のＮ＋（又はＰ＋）
形ベース領域をエミッタ領域を含むように形成している
ため、エミッタ・ベース接合空乏層幅およびエミッタ・
ベース接合空乏層面積が減少し、よって表面および空乏
層内での再結合電流が減少してｈＦＥのリニアリティが
向上する。In vertical PNP (or NPN) transistors, the concentration of N+ (or P+) is higher than that in the epitaxial layer.
Since the shaped base region is formed to include the emitter region, the width of the emitter-base junction depletion layer and the emitter-base region are
The base junction depletion layer area is reduced, thereby reducing the recombination current at the surface and within the depletion layer, improving the linearity of the hFE.
また、エミッタ直下のベース領域が高濃度になるのでウ
エブスタ（Ｗｅｂｓｔｅｒ）効果の影響が緩和され、Ｉ
Ｃａ＋ａｘが上昇する。さらにこのＮ” （又はＰ
＋）形ベース領域が不純物濃度勾配を有し、かつエミッ
タ領域よりかなり深く形成して実効ベース幅を小さくし
ているため、ｆＴが大きくなり高周波特性が向上する。In addition, since the base region directly under the emitter becomes highly concentrated, the influence of the Webster effect is alleviated, and the I
Ca+ax increases. Furthermore, this N” (or P
Since the (+) type base region has an impurity concentration gradient and is formed much deeper than the emitter region to reduce the effective base width, fT is increased and high frequency characteristics are improved.
Ｐ（又はＮ）チャネルＭＯＳトランジスタにおいては、
エピタキシャル層に比べて高濃度のＮ＋（又はＰ”）形
ウェル領域を形成するため、イオン注入等によりこのウ
ェル領域を精度良く形成すれば、エピタキシャル層の比
抵抗のバラツキの影響をなくしてチャネル領域の不純物
濃度を一定にすることが可能となる。したがって、一定
のしきい電圧を得ることができ、しきい電圧の制御性が
改善される。In a P (or N) channel MOS transistor,
In order to form an N+ (or P'') type well region with a higher concentration than the epitaxial layer, if this well region is formed with high precision by ion implantation etc., the effect of variations in the resistivity of the epitaxial layer can be eliminated and the channel region It becomes possible to make the impurity concentration constant. Therefore, a constant threshold voltage can be obtained, and the controllability of the threshold voltage is improved.
また、上述のように高濃度のベース領域およびウェル領
域とを形成することによって、縦形ＰＮＰ（又はＮＰＮ
）トランジスタにおけるコレクタ・ベース接合のパンチ
スルー耐圧およびＰ（又はＮ）チャネルＭＯ３）ランジ
スタにおけるソース・トレイン間のパンチスルー耐圧を
上゛げることかでき、素子寸法の縮小化が図れる。Furthermore, by forming the highly doped base region and well region as described above, vertical PNP (or NPN
) It is possible to increase the punch-through voltage of the collector-base junction in a transistor and the punch-through voltage between the source and train of a P (or N) channel MO3) transistor, and the device size can be reduced.
第１図（ａ）〜（ｄ）は本発明の一実施例を説明するた
めの製造工程順に配置した半導体チップの断面図、第２
図は従来例を説明するための半導体チップの断面図であ
る。
１・・・Ｐ−形シリコン下地板、２−１．２−２・・・
Ｎ１形埋込層、３−１〜３−４・・・Ｐ＋形埋込層、４
．４−１〜４−４・・・Ｎ形エピタキシャル層、５・・
・Ｐ＋形コレクタ領域、５−１〜５−４・・・Ｐ＋形絶
縁分離領域、６−１・・・Ｎ＋形ウェル領域、６−２・
・・Ｎ＋形ベース領域、７・・・素子分離用酸化膜、８
・・・ゲート酸化膜、９・・・ゲート多結晶シリコン層
、１０・・・Ｎ＋形ベースコンタクト領域、１１・・・
Ｐ＋形エミッタ領域、１２・・・Ｐ＋形コレクタコンタ
クト領域、１３・・・Ｐ＋形ソース、ドレイン領域、１
４・・・絶縁層、１５・・・ベース電極、１６・・・エ
ミッタ電極、１７・・・コレクタ電極、１８・・・ソー
ス・トレイン電極。1(a) to 1(d) are cross-sectional views of semiconductor chips arranged in the order of manufacturing steps for explaining one embodiment of the present invention;
The figure is a sectional view of a semiconductor chip for explaining a conventional example. 1...P-type silicon base plate, 2-1.2-2...
N1 type buried layer, 3-1 to 3-4...P+ type buried layer, 4
．． 4-1 to 4-4...N type epitaxial layer, 5...
・P+ type collector region, 5-1 to 5-4...P+ type insulation isolation region, 6-1...N+ type well region, 6-2.
... N+ type base region, 7... Oxide film for element isolation, 8
... Gate oxide film, 9... Gate polycrystalline silicon layer, 10... N+ type base contact region, 11...
P+ type emitter region, 12... P+ type collector contact region, 13... P+ type source, drain region, 1
4... Insulating layer, 15... Base electrode, 16... Emitter electrode, 17... Collector electrode, 18... Source/train electrode.
Claims (1)
導電形半導体下地板に第２導電形エピタキシャル層を成
長させて第１、第２導電形埋込層を設けた半導体基板に
縦形ＰＮＰ（又はＮＰＮ）トランジスタとＰ（又はＮ）
チャネルＭＯＳトランジスタを設けたバイＭＯＳ集積回
路を形成するに際し、前記バイポーラトランジスタのベ
ース領域の少なくとも一部とＭＯＳトランジスタを形成
するウェル領域とを同一工程で選択的に不純物を導入し
て形成することを特徴とするバイＭＯＳ集積回路の製造
方法。A first structure in which first and second conductivity type regions are selectively formed.
A vertical PNP (or NPN) transistor and a P (or N) transistor are formed on a semiconductor substrate in which a second conductivity type epitaxial layer is grown on a conductivity type semiconductor base plate and first and second conductivity type buried layers are provided.
When forming a bi-MOS integrated circuit provided with a channel MOS transistor, at least a part of the base region of the bipolar transistor and a well region in which the MOS transistor is formed are formed by selectively introducing impurities in the same process. A method for manufacturing a bi-MOS integrated circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62007787A JPS63175463A (en) | 1987-01-14 | 1987-01-14 | Bi-MOS integrated circuit manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62007787A JPS63175463A (en) | 1987-01-14 | 1987-01-14 | Bi-MOS integrated circuit manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63175463A true JPS63175463A (en) | 1988-07-19 |
Family
ID=11675375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62007787A Pending JPS63175463A (en) | 1987-01-14 | 1987-01-14 | Bi-MOS integrated circuit manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63175463A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02174256A (en) * | 1988-12-27 | 1990-07-05 | Nec Corp | Manufacture of bi-mos integrated circuit |
| JPH03129874A (en) * | 1989-10-16 | 1991-06-03 | Nec Yamagata Ltd | Bi-CMOS integrated circuit |
| EP0948046A1 (en) * | 1998-03-26 | 1999-10-06 | Texas Instruments Incorporated | Merged bipolar and CMOS circuit and method |
| EP0736898A3 (en) * | 1995-04-07 | 1999-11-03 | Matsushita Electric Industrial Co., Ltd. | BICMOS device and method for the fabrication thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57136358A (en) * | 1981-02-17 | 1982-08-23 | Seiko Instr & Electronics Ltd | Integrated circuit device and manufacture thereof |
| JPS57198650A (en) * | 1981-06-01 | 1982-12-06 | Toshiba Corp | Semiconductor device and manufacture therefor |
-
1987
- 1987-01-14 JP JP62007787A patent/JPS63175463A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57136358A (en) * | 1981-02-17 | 1982-08-23 | Seiko Instr & Electronics Ltd | Integrated circuit device and manufacture thereof |
| JPS57198650A (en) * | 1981-06-01 | 1982-12-06 | Toshiba Corp | Semiconductor device and manufacture therefor |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02174256A (en) * | 1988-12-27 | 1990-07-05 | Nec Corp | Manufacture of bi-mos integrated circuit |
| JPH03129874A (en) * | 1989-10-16 | 1991-06-03 | Nec Yamagata Ltd | Bi-CMOS integrated circuit |
| EP0736898A3 (en) * | 1995-04-07 | 1999-11-03 | Matsushita Electric Industrial Co., Ltd. | BICMOS device and method for the fabrication thereof |
| EP0948046A1 (en) * | 1998-03-26 | 1999-10-06 | Texas Instruments Incorporated | Merged bipolar and CMOS circuit and method |
| JP2009016856A (en) * | 1998-03-26 | 2009-01-22 | Texas Instr Inc <Ti> | Merged bipolar and CMOS circuits and their manufacturing methods |
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