JPS58215565A - Peak value detecting circuit - Google Patents

Abstract

PURPOSE:To obtain the titled circuit which allows precise measurement, by eliminating an error due to leaking because of the error is digitally storaged, and the need to consider frequency dependency of noise because of a high-speed A/D conversion is used. CONSTITUTION:A storage circuit LA1 and a comparing circuit CM1 detect whether an analog signal rises or falls at the present time. Storage circuits LA2 and LA3, a selecting circuit SE, and a comparing circuit CM2 compare current data with the maximum value of data when the waveform is in a leading edge state or compare the current data with the minimum value of data. Then, a writing control circuit sends a clock pulse to the storage circuits to update the data in such a way that the current data is regarded as a new maximum value when the current data is greater than the current maximum value or as a new minimum value when the current data is smaller than the current minimum value Consequently, the current minimum value is stored in the control circuit LA2 and the current minimum value is stored in the storage circuit LA3; and their difference is found to obtain an expected peak value.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is in the field of analog circuits and relates to measurement of analog circuits.

Generally speaking, among analog device measurements, there is something called noise measurement. This measures the level non-uniformity (also called drift) that appears at the output terminal when the input conditions of the analog device are held constant, and is obtained by measuring the difference between the maximum and minimum values of the waveform. It is something.

Conventionally, measurements have been made using a well-known peak value detection circuit as shown in FIG. In this operation, an analog signal is input to the analog input terminal VrN, and if a positive voltage is applied, the capacitor (C1) is charged as a positive voltage from the operational amplifier (ICI) through the diode (Dl). When the analog signal is lower than the voltage of the capacitor (C1), the charge stored in the capacitor remains unchanged, but when the analog signal is higher than the voltage of the capacitor (C1), the capacitor (C1) is further charged. Of course.

In this way, the peak value for positive voltage will be held in the capacitor (C1). Also, if the analog input signal is negative, it passes from the ground potential through the capacitor (C2) and the diode (
A current flows through the operational amplifier (IC2) and the capacitor (C2), and the capacitor (C2) is charged as a negative voltage. The operation is the same as when the voltage is positive, and the peak value of the negative voltage is held in the capacitor (C2). Then, the peak value can be obtained by taking the difference between each output OUT (-1-1 and 0UT If there is a leak in the components, an error will occur.Also, there is noise at fast and slow frequencies, and there are also problems in the selection of capacitors for tracking performance.

The present invention has been devised to solve these problems.

The present invention will be explained below.

FIG. 2 shows an embodiment of the present invention.

As shown in Figure 2, an analog-to-digital converter (hereinafter referred to as A/D
The digital output terminal (DOU) of the converter (AD)
T) as memory circuit (LAI), (Li2) and (Li2
) data input terminal (LII).

(LI2) and (LI3) respectively, and further connected to one data input terminal (CA1) and (CA2) of the comparison circuit (CMl) and (0M2), respectively, and the data output terminal ( LOI) to the other data input terminal (CB1) of the comparison circuit (CMI), and the data output terminal (LO2) of the storage circuit (Li2) to one data input terminal (SA) of the selection circuit (SE). In addition, the data output terminal (LO3) of the memory circuit (Li2) is connected to the other data input terminal (SB) of the selection circuit (SE), and the data output terminal (SO) of the 1 selection circuit (SE) is connected.
to the other data input terminal (CB2) of the comparison circuit (0M2).
) and the control output terminal (C0
1) Selection control input terminal (SIN) of selection circuit (SE)
and write control circuit (WC) selection input terminal (WIII
N) and the control output terminal (C
02) to the clock control input terminal (WtN) of the write control circuit (WC), and the three clock input terminals (WOI), (WO2) and (WtN) of the write control circuit (WC).
O3) to memory circuits (LAI), (Li2) and (L
i2) clock input terminal (CL 1 ).

(CL2) and (CL3), respectively.

The operating principle is as follows. First of all, is the analog signal currently in the rising state?

A memory circuit (LAI) and a comparison circuit (CMI) detect whether it is in a falling state. Next, if the waveform is in the rising state, compare the current data with the maximum value of the data,
If the waveform is in a falling state, the current data and the minimum value of the data are compared.
Do it with.

Next, when the current data is larger than the previous maximum value or the current data is smaller than the previous minimum value, the write control circuit stores the current data as the maximum or minimum value. Send clock pulses to the circuit to update data. By repeating the above three operations, the maximum value,
Find the minimum value.

Now the analog signal VIN is input to the A/D converter input (AIN).
Suppose that comes in. At a certain point in time, the analog signal is sampled and taken into the A/D converter (AD), the digital value is converted, and the data taken in at the present moment is output from the data output (Dour) of the A/D converter (AD). . First, this data is input to the data input (CAI) of the comparator circuit (CMI), while the memory circuit (LAI) stores the previous sampling data sampled at the present moment. Comparison circuit (CM
It can be input to the data input (CBI) of l). Here, the current data and the previous data will be compared. As a result, if the current data is large, it is found that the analog signal is currently in a rising state, and if the current data is small, it is found that the analog signal is in a falling state. The comparison result is input to the selection control input terminal (SxN) of the selection circuit (SE). If it is in the rising state at the moment, it will be compared with the maximum value of the data up to now, and a memory circuit (Li
2) The data input terminal whose maximum value is selected times*(8E) (
8A) to the data input terminal (C) of the comparator circuit (0M2).
B2). Current data is input to the data input terminal (CA2) of the comparison circuit (0M2), and these data are compared. Here, if the current data is larger than the maximum value, the output (CO2) of the comparison circuit (0M2) is output to the clock control input terminal (WIN) of the write control circuit (WC).
) K is input, and the comparator circuit (CMI, ) and the output (co
When B is input to the selection input terminal (W8IN), a clock is output from the clock output terminal (WO2) and input to the clock input terminal (CL2) of the memory circuit (Li2) that stores the maximum value so far. The current sampling data from the input terminal (LI 2 ) will be newly stored as the maximum value. Also, if the current data is smaller than the maximum value, the maximum value data is not updated and the write control circuit (WC
) The maximum value issued by the clock pulse for updating the maximum value does not change. Also, in the falling state, as in the rising state, the data output (LO3) of the memory circuit (Li2) that stores the minimum value is selected by the selection circuit (SE), and the data of the comparison circuit (0M2) is selected by the selection circuit (SE). It will be input to the input (CB2) and compared with the current data. When the current data is smaller than the minimum value, as before, a clock pulse is input from the clock output terminal (WO3) of the write control circuit (WC) to the clock input terminal (CL3) of the memory circuit (Li2), and the current data is It is newly stored as the minimum value.

Also, if the current data is larger than the minimum value, there is no change. Roughly, until the A/D converter (AD) samples the next analog signal, the clock is output from the clock output terminal (WOI) of the write control circuit (WE) and sent to the clock input terminal (CLI) of the memory circuit (LAI). entered,
The current data is stored in the storage circuit (LA1). The above is the operation of the A/D converter from one sampling to the next sampling.

By repeating this for an arbitrary period of time, the memory circuit (
The maximum value up to now is stored in the memory circuit (Li2).
) will store the previous minimum value. Therefore, by finding this difference, the expected peak value can be obtained.

By using the present invention, errors due to leakage, which is a problem with conventional methods, can be avoided because they are stored digitally.
By using a high-speed A/D converter,
There is no need to consider the frequency dependence of noise, and highly accurate measurement becomes possible.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional peak value detection circuit, and FIG. 2 is a diagram showing a peak value detection circuit according to the present invention. V IN-----Analog signal input, IC1, IC
2...Operational amplifier, D1. D2...Diode. CI, C2...Capacitor, 0UT(+), 0
UT (→...Maximum and minimum data output.

Claims (1)

[Claims] The data output of the analog-to-digital converter is supplied to the data input terminals of the first to third memory circuits. Furthermore, the first and second comparison circuits are supplied to one data input terminal thereof, the data output of the first storage circuit is supplied to the other data input terminal of the first comparison circuit, and the second The data output of the storage circuit is supplied to one data input terminal of the selection circuit, and the data output of the third storage circuit is supplied to the other data input terminal of the selection circuit, and the data output terminal of the selection circuit is connected to the selection circuit. the control output terminal of the first comparison circuit is connected to the selection control input terminal of the selection circuit and the selection input terminal of the write control circuit; A peak value configured by connecting a control output terminal to a clock control input terminal of the write control circuit, and connecting three clock output terminals of the write control circuit to clock input terminals of the first to wc3 storage circuits, respectively. Detection times V! &.