JPS58201138A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To speed up arithmetic processing, by giving two pieces of address information to an instruction code set in an instruction register, and providing two memories accessed on the basis of those pieces of address information and two registers for arithmetic. CONSTITUTION:The instruction code set in the instruction register IR is given two pieces of address information, which are applied to address circuits ADR1 and ADR2, respectively. Control information is applied to a CNT to control respective circuit parts. Therefore, the memories MEM1 and MEM2 are accessed by address signals from the address circuits ADR1 and ADR2 to read data simultaneously, and those read data are set in input registers AR and BR. Then, they are processed by an arithmetic circuit ALU and the result is set in an accumulator ACC. Consequently, the number of cycles is reduced and the arithmetic processing is speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a digital signal processing circuit that performs arithmetic operations on data read from a memory at high speed in accordance with an instruction code.

Prior art and problems A conventional configuration for executing operations according to an instruction code is shown in Fig. 1. In the figure, TR is an instruction register (2) for setting an instruction code, and ADH is an address register. The circuit 3M is a memory 1c which stores data, T is a control circuit which controls each part, DB is a data bus, AR, B
R is an input register, ALU is an arithmetic circuit, and ACC is an accumulator. FIG. 2 is an explanatory diagram of the operation, and (a) is an operation cycle clock.

(bl is the instruction code, (C) is the contents of the instruction register IR.

(d+ is the data on the data bus, (e) is the content of the large register AR, (f) is the content of the input register BR, (g)
is the operation of the arithmetic circuit ALU, (h) is the accumulator AC
This shows the contents of C.

When the instruction code is set in the instruction register IR, the address information contained therein is added to the address circuit ADR, and the control information is added to the control circuit CNT, and the control circuit CNT controls each section according to the control information by control lines indicated by dotted lines. control. Further, an address signal for the memory M is created by the address circuit ADH, and the memory M is accessed. The data read from the memory M is input to the input register AR via the data bus DB, and by the same operation (3), the data is input to the long sword register BR according to the instruction code of the next cycle. Input register AR, BR
The data is calculated by the calculation circuit ALU, and the calculation result is set in the accumulator ACC.

In FIG. 2, arrows indicate the operation according to the command (1) and the operation according to the command (2). That is, 5 cycles are required to obtain a calculation result, and even if all processes are considered to be pipeline processing, 3 cycles are required to obtain a single calculation result.

In addition, in the case of the operation of (constant x variable), as shown in Figure 3,
Constant data and RAM keep coming out of memory M1 such as ROM
The variable data sequentially outputted from the memory M2, etc., are input to the arithmetic circuit ALU via the input registers AR and BR, and arithmetic is performed, and the result of the arithmetic operation is set in the accumulator ACC. In this case, memory M1 is accessed by sequentially incrementing address signals to read constant data, memory M2 is accessed (4) by address information included in the instruction code to read variable data, and at the same time each register AR
, BR.

However, there may be cases where it is necessary to perform the calculation (variable x variable), and in that case, as shown in Figure 4, the memory M2
It would be sufficient if the configuration was such that the variable data read from the memory M2 can be input to the input registers AR and BR, respectively. First, the variable data read from the memory M2 is set in the input register AR, and then the variable data read from the memory M2 is input to the input register BR. The variable data read from memory M2 will be set,
Since the variable data is read out twice from the memory M2, the processing speed is slower than in the case of the (constant×variable) operation.

OBJECT OF THE INVENTION The present invention is to improve the calculation speed by making it possible to read data from a memory in a small number of cycles, and also to make it possible to speed up calculations using an external expansion memory. The purpose is to Examples will be described in detail below.

(5) Embodiment of the invention FIG. 5 is a block diagram of an embodiment of the invention.
is an instruction register, ADRI, ADH2 are address circuits,
MEMI and MEM2 are memories, CNT is a control circuit that controls various parts by control lines indicated by dotted lines, AR and BR are input registers, ALU is an arithmetic circuit, and ACC is an accumulator. The instruction code set in the instruction register IR includes two pieces of address information, which are respectively applied to address circuits ADRI and ADR2. Control information is also applied to the control circuit CNT. Therefore memory MEMI, M
EM2 is accessed by address signals from address circuits ADRI and ADR2, and data is simultaneously read out from input register AR.

Set to BR. Then, the calculation circuit ALU performs calculation, and the calculation result is set in the accumulator ACC.

FIG. 6 is an explanatory diagram of the operation, where (a) is the operating cycle clock, (mountain) is the instruction code, (C) is the content of the instruction register IR, (d) is the content of the input register AR, and (e) is the input (
6) The contents of the cash register BR, (f) the operation of the arithmetic circuit ALU, and (g) the contents of the accumulator ACC. For instruction code (1), as shown by the arrow,
After being set in the instruction register TR, the addresses of the memories MEMI and MEM2 are set according to the address information contained therein.
The data read from is input to the input registers AR and BR as shown in (d) and (el), and these data are calculated in the arithmetic circuit ALU and then input to the accumulator ACC as shown in (g). Therefore, the number of cycles is reduced by one cycle compared to the conventional example (see FIG. 2).

FIG. 7 is a block diagram of another embodiment of the present invention;
The same symbols as in the figure indicate the same parts, and 5ELI
~5EL3 is a selector, MEM3 is a read-only memory (ROM>, etc.) that stores constants, etc., MEM4 is an external expansion memory, and DB is a data bus.Instruction register IR
When the instruction code is set to , address information is added to the address circuits ADRI and ADR2, respectively, and control information is added to the control circuit CNT. The stored memory MEM3 becomes accessible, and one of the memories MEMI and MEM2 storing variable data becomes accessible, and an address signal is applied to the accessible memory under the control of the selector SEL1.

That is, when the memory MEM1 is made accessible, the selector 5EL1 performs a switching operation so as to apply the address signal from the address circuit ADR2 to the memory MEM1, variable data is read from the memory MEM1, and at the same time, the memory MEM1 is
Constant data is read from M3.

Further, the selector 5EL2 selects successive data in the memory MBM1, and the selector 5EL3 selects successive data in the memory MBM1 on the data bus DB.
Select the continuation data of EM3.

Therefore, variable data is set in the input register AR, constant data is set in the input register BR, and the calculation of (constant x variable) is performed by the calculation circuit ALU. Note that if the variable data at this time is stored in the memory MEM2.

The memory MEM2 becomes accessible and is accessed by the address signal from the address (8) circuit ADR2.

In addition, in the case of the operation of (variable x variable), the memories MEMI and MEM2 are accessed by the address signals from the address circuits ADR1 and ADR2, respectively, and the variable data read out at the same time is , input registers AR and BR via selectors 5EL2 and 5EL3.
is set, the calculation is performed by the calculation circuit ALU, and the calculation result is set in the accumulator ACC.

Selected by selector 5EL2, input register AR
Or it is input to the input register BR. Therefore, memory M
It is possible to perform arithmetic operations on successive data from any of EM1 to MBM3 and successive data from external expansion memory MEM4, and data can be set in input registers AR and BR at the same time, thereby speeding up the arithmetic processing.

It is also possible to control the continuous flow of data by regarding the memories MEMI and MEM2 as one memory (9).
In this case, the same 7dress signals are sent to each memory MEM1. M
It will be accessed in addition to EM2. As described above, various types of memory selection control are possible.

DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention includes two pieces of address information in an instruction code, and provides address circuits ADRI and ADR2 that add each piece of address information, thereby making it possible to access two memories at the same time. , input register AR, B
Since data can be set in R at the same time, arithmetic processing can be speeded up. Furthermore, the selector allows selection of address signals, input register AR,
Since data to the BR can be set from memory or a data bus, arithmetic processing can be performed by selectively controlling a plurality of memories in which various types of data are stored. Therefore, even when an external expansion memory is used, arithmetic processing can be performed at high speed.

[Brief explanation of the drawing]

(10) Figure 1 is a block diagram of a conventional digital signal processing circuit.
FIG. 2 is an explanatory diagram of the operation of FIG. 1, and FIGS. 3 and 4 are block diagrams for explaining conventional arithmetic processing. FIG. 5 is a block diagram of an embodiment of the present invention, and FIG. 6 is a block diagram of an embodiment of the present invention.
FIG. 7 is a block diagram of another embodiment of the present invention. IR is an instruction register, CNT is a control circuit, DB is a data bus, ADRI, A, DR2 are address circuits, MEMI
~MEM3 is memory, MEM4 is external expansion memory, 5R
LL~5EL3 are selectors. ALU is an arithmetic circuit, and ACC is an accumulator. AR and BR are input registers. Patent applicant Fujitsu Ltd. Representative Patent Attorney Gobe Tamamushi and 3 other people (11) Figure 1 Figure 2 (1m) Figure 3 □□ Figure 5 Figure 6

Claims (2)

[Claims] (1) In a digital signal processing circuit that performs calculations on data read from memory according to an instruction code. an instruction register for setting the instruction code; an address circuit for inputting two pieces of address information added to the instruction code set in the instruction register; and at least two memories accessed by the address information from the address circuit. , comprising two input registers into which data respectively read from the two memories or data via a data bus are input, and an arithmetic circuit which performs arithmetic operations on the data from the two input registers. digital signal processing circuit. (2) In a digital signal processing circuit that performs arithmetic operations on data read from memory in accordance with an instruction code. an instruction register for setting the instruction code; an address circuit for inputting the two pieces of address information (1) added to the instruction code set in the instruction register; a selector for selecting address information from the address circuit; At least two memories accessed by address information selected by a selector or address information from the address register, selecting data read from the two memories or data via a data bus 2
A digital signal processing system comprising: a selector, two input registers into which data selected by the two selectors are respectively input, and an arithmetic circuit that performs an arithmetic operation on data from the two input registers. circuit.