JPS58200296A - Envelope signal generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an envelope signal generating device that generates various envelope signals of musical tone signals used in electronic musical instruments as digital data, and in particular, it is capable of generating signals of a wide range of shapes with a small amount of data. It is 37" in size.

FIG. 1 is a block diagram of an electronic musical instrument employing the frequency control device of the present invention. 1 is a keyboard section, KO is an operation section consisting of a tone tablet switch, a vibrato effect on/off switch, a volume for setting the depth of the vibrato effect, etc., and 3 is a central processing unit (CPU), which is used for computers etc. 4 is a read/write storage device (random access memory, usually called RAM), and 6 is a read-only storage device (read-only memory) in which the program that determines the operation of the CPU 3 is stored. , usually referred to as ROM), 7 is a ROM that stores envelope parameters among the parameters for timbre synthesis, and 6 is a ROM that stores frequency-related data among the parameters for timbre synthesis.
It is.

8 is an uninvented frequency control device; 9 is a patent application filed in 1986-165.
A sine wave generator such as No. 189, 1o is an envelope signal generator, 11 is a multiplier that multiplies and combines envelope data representing the sine wave and envelope signal, and 12 is a multiplication result that is time-division multiplexed. Among them, you can add certain things together,
A time slot control device 13 for changing the order of time division multiplexing 71. phase modulator, 1
4 is a digital-to-analog converter, and 15.16 is an electroacoustic transducer.

Keyboard section 1. Operation unit 2. CPU3. RAM4゜ROM5.
ROMe, ROM7. The frequency control device 8 and the envelope signal generator 1o are coupled by a data bus, an address bus, and a control line.

The method of coupling data buses, address buses, and control lines in this manner is a well-known method for configuring minicomputers and microcomputers. As a data bus, 8 to 16 buses are used.
Data is transmitted and received on this bus line not in one direction but in multiple directions in a time-division manner.

A plurality of address buses, for example 16, are prepared.Usually, the CPU 3 outputs the □address code, and other parts receive and receive the address code. The control line is usually the memory request line (MREQ).

6” -' Ilo Request line (IORQ), lead line (
R.D.).

The light line (WR) fi is not used.

MREQ indicates reading and writing of the memory and indicates the timing to read data, and WR indicates the timing to write data to the memory and Ilo. An example of a microprocessor using such a control line is the microprocessor Z8O manufactured by Zilog.

Next, the operation of the electronic musical instrument shown in FIG. 1 will be described.

The keyboard section 1 is configured such that a plurality of key switches are divided into a plurality of groups and the ON-OFF states of the key switches in the groups can be sent to the data bus all at once. For example, 6
For an octave keyboard, there are 61 keys (half an octave)
It is divided into 11 groups, 10 groups with each key and 1 group with only one key, and one address code f: is assigned to each group. An address code indicating one of the above groups arrives on the address line, and when 1L1i1 and 1113 are decoys, the keyboard section 1 decodes the 6-page address code and responds accordingly. 6-bit or 1-bit data indicating ON-OFF of the key switch in the group to be outputted to the data bus. These devices can be constructed using decoders, bus drivers, and some gate circuits. Of the operation section 2, the tablet switch can have the same configuration as the keyboard section 1. Regarding the setting state of the volume, the voltage output from the volume is converted into a digital code by an analog-to-digital converter, and this code is converted into an address code.

The CPU 3I/i reads the instruction code from the ROM 6 address corresponding to the code of the internal program counter, decodes this code, and performs arithmetic operations.

Performs tasks such as logical operations, reading and writing data, and jumping instructions by changing the contents of the program counter. The procedures for these operations are written in the ROM5. The CPU 3 reads from the ROM 5 a command for importing the data of the keyboard section 1, and then imports codes indicating ON-OFF of each weight of the keyboard section 1 for each group. Then, the key code being pressed or pressed is assigned to a finite channel of the musical tone generator.

Next, the CPU 3 sequentially reads a group of instructions from the ROM 5 for importing the data from the operation section 2, decodes these commands, outputs the corresponding data to the operation section 2, and sends the switches of the operation section 2 and the like to the data bus. A code expressing the state of the volume is output and read into the CPU 5. Then, the CPUa knows which timbre of musical tone signals should be synthesized.

Now that it is clear which tone with which frequency should be generated in which channel of the musical tone generator,
The CPU 3 stores the frequency parameters of the desired tone from the ROMA that stores data regarding the frequency of each tone.
I! : Outputs Q and HD, reads desired frequency parameters onto the data bus, takes them into the CPUa, and writes them into the frequency control device 8. In order to write, the CPU 3 outputs the address code corresponding to the data register provided inside the frequency control device 8, and at the same time, at 9 o'clock, the data representing the frequency parameter being output to the data bus is changed to -. 1. Write to the data register. Next, a timbre parameter representing the content of the timbre to be output is read from the iROM memory and written to the internal register of the envelope generator 1o. Next, when a sound output command of 77 is given to both the frequency control device 8 and the envelope generator 1o, the frequency control device 8 transmits the jump number J to the sine wave generator 9.
, and the envelope signal generator 10 generates envelope data.

The sine wave data having a frequency proportional to the jump number J output from the sine wave generator 9 and the envelope data are multiplied and an envelope is given to the sine wave. The upper limb data and the envelope data are time-division multiplexed.
, occurs. The time division multiplexing is, for example, 160 multiplexing, and 92Q9 and 1'' sine waves are assigned to each channel to provide eight channels.

Normally, one musical tone is synthesized by synthesizing 20 sine waves. Therefore, sine wave data of 9.20 is added to n, which is known from the Fourier series formula. Data addition between time slots for this purpose is performed by the time slot converter 12. The time slot converter performs time division multiplexing on 160 time slots and adds predetermined data among the sine wave data strings modulated with envelope data to reduce the number of time slots, or , Patent Application 1982-202PO4
This is a device that exchanges time slots like the time division multiplex converter of No. 1. The time division multiplex phase modulator 13 is
Like the 182083 [digital musical tone modulation device], it simultaneously performs multiple types of modulation through time division multiplexing.

The output of the time-division multiplexing phase modulator 13 is converted into an analog signal by an analog-to-digital converter 14, and outputted to an electroacoustic transducer 16.degree. 16 as a V output.

1 0tj-" Although not shown in FIG. 1, the time slot converter 12
It is connected to the CPU 3 via the address bus, data path, and control line to the time-division multiplex phase modulation device 13, and the time slot is controlled in response to the settings of the tone and modulation effect performed by the operation section 2. The conversion and modulation conditions can be changed and set.

In FIG. 1, the envelope signal generator 10 outputs an address and a read command signal to the ROM 7 so that desired data can be directly read.

FIG. 2 is a block diagram of an embodiment of the envelope signal generator of the present invention. In FIG. 2, reference numeral 7 denotes the above-mentioned parameter ROM, in which data obtained by compressing the sample values of the envelope signal is stored. 20 is a sample calculator, 21 is a tablet interface, 22 is a key interface, and 23 is an interpolation calculator.

The tablet interface 21 and the parameter ROM 7 have the (3PU to V tone code 1 11i, . . .
-: Supplied. The upper three bits of the timbre code are applied to the upper address of the parameter ROM 7 as a code specifying one of the eight types of musical instruments.
The area in M7 in which the parameters of the specified musical instrument sound are stored is selected.

The lower bits of the timbre code include data indicating the mode of the timbre, for example, whether the envelope shape is organ-shaped or piano-shaped, and is supplied to the sample calculator 20 via the tablet interface 21. . The tablet interface 21 includes a data launch, where CPtTs write a tone code to the data latch,
After that, at the necessary timing, the sample calculator 2o
reads out. The CPUa supplies the key interface 22 with note octave data representing the pitch of the sound to be generated, and a key CAM, OFF signal, , representing whether the key of the pitch is ON or OFF, Write to internal latch. The sample calculator 2o reads out the data held by the tablet interface 21 and the key interface 22 according to internal predetermined timing, outputs address data to the parameter ROM 7 based on this data, and reads the contents. The sample is read out, generated by calculation, and supplied to the interpolation word calculator 23.

The interpolation calculator 23 performs an interpolation calculation, for example, linear interpolation, on the middle of the n envelope samples supplied one after another, and outputs smoothly changing envelope samples.

FIG. 3 shows examples of envelope signals and their sample values for explaining sample operations applied in the present invention. Figure 3(b) shows the envelope to be generated on a 68 scale, with the maximum value being OdB,
The minimum value is -80 dB. A black point (S
o, Sl, Sl, ...) is the time interval Ti =
Represents sample values sampled at T and 2T. Based on such data, if we take the difference value of each sample value in dB1 scale, we get (ΔN O + Δ
Violet 1. ΔE2. ...). Figure 3 (0
) converts the sample values shown by the black dots in Figure 3(b) from the 68 scale to the linear scale values (LIEo, IJC,,LE
2. ...1 31j-:' ...), and the respective points are connected with dotted straight lines. In the present invention, the dB difference values ΔEo, Δz1 . ΔE2. . . . is stored in the parameter ROM 7. By sequentially reading and accumulating these n dB difference values, p, envelope samples So, S1 . S2. obtain...

Next, the envelope samples on the dB scale are subjected to logarithmic-linear transformation to obtain envelope samples LXo, LE, on the linear scale.

Lm! 2. obtain... The sandal period of this envelope sample is the above-mentioned Ti=T or 2T, but this period is the period Ts of the musical tone sample that is finally output.
bigger. Therefore, in order to successively generate envelope samples at times corresponding to the sample period of the musical tone,
Sample Lm! :o, LEl, LIC2,...
. . . A linear interpolation calculation is performed between two adjacent samples, and an envelope sample having a shape as shown by the dotted line in FIG. 3(0) is obtained every period Ts.

FIG. 4 is a block diagram of an embodiment of the present invention, which implements the calculation procedure described in FIG. In FIG. 4, the readout calculation control unit 25Fi reads the tone code, note off 14be-5: tarp data, and key 0NOFF data, and according to these data, generates the envelope signal corresponding to the tone code and note octave data. Representing dB difference value ΔK
i is stored, an address program D at a certain address is sequentially generated, a read command signal HD is output, and the parameter ROM 7J
: 9 dB The difference value ΔIEi is read out to the output terminal D6 and stored in the latch 30. It is assumed that the latch 31 always contains zero. The adder/subtractor 32 adds ΔEi and zero to produce ΔXi, and supplies f'L to one input of the adder/subtractor 32. The output of the adder/subtractor 33 is sent to the register 3
The signal is stored in the logarithm-to-linear converter 36 at the same time. The output of the register 34 is supplied to the other input of the adder/subtractor 33. Register 34 is a one word latch. The adder/subtractor 33 and the register 34 function as an accumulator that accumulates ΔICi to generate and output 1 in Sn-, ΣΔEi (1). The logarithm-linear converter 35 is a read-only memory 151 (ROM) that generates a linearized output code LEn for the input code Sn.The input is 8 bits and the output is 16 bits. This results in a ROM of 256×16=4096 bits.The envelope sample LEnU is added to the register 36 and delayed by one sample time.

Then, in the subtracter 37, Δ1. +Kn=IJn
-LIICn.

is calculated. The output ΔLXn of the subtracter 37 is shifted downward by a predetermined bit in the bit shift register 38 and is supplied to one input of the n1 adder/subtracter 39. The output of the adder/subtractor 39 is delayed by a musical tone sample period Ts in a shift register 40, and then supplied to the other input of the adder/subtractor 39. The bit shift register 38 is a kind of divider, and Sn = (LEn LEn-1)/(Tn-t/T
s ) (2) (n=2.3, 4.
・) Execute.

Tn-1/Ts = 2'
If it is a power of 2 like (s), shifting □ and P bits corresponds to division.

When Sn is accumulated 2P times, ΔLEn=IJn-LEn-, (n==2+3+4-"
') becomes (4). Therefore, LEn−, to L
Linear interpolation can be performed between En in a time of Tn-1. The interpolated envelope sample is "n+ j-LEn-+ + j (LEn""n-1
)/(Tn-1/T8)(j=・1,--1Tn-
+/Ts ) (5).

Sn, LEn, ΔLm! The generation of :n and δn is performed every Ti period. Therefore, latch 30. The latch pulses of the registers 34 and 36 and the bit shift register are output from the read operation control section 26, and
Updated. The output code ΔLXn is obtained by performing a plurality of consecutive 9 shifts using the code representing P corresponding to the bit shift register shift bit force n and Ti/Ta.

ΔLEJ2, ΔIJn/22, . . . are selected and their outputs are latched. Since the contents of the register 40 are updated every cycle T8, a latch pulse is supplied from the read operation side or the 11-tone IX 26 every cycle Ts.

Figure 6 shows the simplified envelope data (ΔKi) (
1-I L 2 + "a + ......, N
) is an example. dBB10 7t. −． 'The minute value ΔEi is the address 1 to N in parameter 1'tOM.
It is placed in a place. At address 0 at the beginning, a release address RAD is stored. Now, for simplification, Ti (i=1. 2, 3. . .
...) are all equal. When the key O N O F F' signal input to the read operation control unit 25 becomes "1" and the key is pressed, first, the address D indicating the address o1 is output to the ROM 7, and the clove becomes "1". 0”,
The release address RAD stored at address 0 is read out, and this n is stored in an internal register. Next, increase MuD by 1 and set RD to "o" to set Δ to address 1.
, is written to the latch 30. Registers 30, 34, 36, 38 as the initial state.

If zero is stored in 4o, then S1=o.

Ll! :1=Q, ΔLIJ:=o, δ1=Q. Therefore, the output of the adder/subtractor 33 is 82-Δ! It becomes 1. After this, calculations are performed according to the procedure described above. i
Addressum D increases by 1 each time .

If you keep pressing the key, Ti will advance more and more, but "i ='
Just before I'+s, stop increasing addressum D1
If the contents of the bit shift register 38 are cleared to zero and the previous accumulated value is held after 8 pages, the envelope signal will remain at LF15. Then the key ONO
When the FF signal becomes 0' and it is known that the key is lost, ΔE15 is read out corresponding to Ti=T+s, and the attenuation process from 8+s to S16 is started. T15 is the starting point of release, and Δ”1 corresponding to this
Let the address where 5 is stored be the release address RAD.

When the key ONOFF signal becomes "o" before Ti=T+5, instead of incrementing address D by 1, it is rewritten to RAD and output, and ΔR15 is read out.

And after that, RAI)-1-1, RAI)+2
, . . . so that the release process progresses. In this way, no matter what time the key is turned OFF, it is possible to jump to RAD at that time or at a predetermined time closest to the key OFF, and to immediately enter the release after the key is OFF. Moreover, since the dB difference value is used, the connections become smooth. For example, from S1z to 81
When jumping to 5, there is a discontinuity of about 5 dB, but from ΔE11 to 19・−Δ1! :, If you jump to 5, S12 Noa Toni, S15-S2
This results in a smoother connection with a lower sdB compared to 0 Kamoto data. Therefore, no discontinuity occurs in the connection before and after the flight, no matter what the envelope shape.

Also, since it is on the 48 scale, a 90 dB change per unit time in the release process (slope on the 48 scale) is maintained. Therefore, the listening sensation of the time change in the decay of musical tones will be the same no matter at what point the key is turned off.

The read arithmetic control unit 26 that realizes the above-mentioned operations includes a register that controls address control, a register that stores RAD, a 9-j arithmetic unit that increases, decreases, or changes addresses, so-called MLU, and It can be realized 1:1 using the same method as sequential control of microcomputers, using elemental circuits used in microcomputers, such as a ROM containing a control program and its decoder. .

FIG. 5 shows envelope data consisting of one dB difference value. This group of data can be held separately for each different octave of the keyboard, and also separately for each different note within one octave. Having separate data in this way allows you to use the optimal envelope for each key in each range, allowing you to create excellent tones in any range. For this purpose, the note octave data shown in FIG. 4 is received, the addresses of the parameter ROM are changed according to this data, and the same type of format is stored at addresses different from the O-N address in FIG. 6. It is also possible to select data.

In the data format of FIG. 5, Ti is kept constant, but since the envelope generally changes drastically at the rise of a musical tone, it is better to reduce Ti and increase the number of sample points. In order to be able to change the size of the turtle by 1, the data format shown in FIG. 6 should be used. In FIG. 6, the release address RAD is at address 0.

Slope at address 1, point interval P and point number PN at address 12, then 3 to 7
ΔE1 to ΔE5 are stored at addresses. Next, PI and PH, and then ΔΣ6~Δ”+4 are stored.
After that, Δ"+5 to Δ"+9 are stored.

RAD is as described in Fig. 5, and 5LOPK is data indicating the average increment of the rising edge, for ΔE1 to ΔE5.
and n is added in common. PI is a code indicating the interval Ti between sample points, and PN is a code indicating how many points the sample point interval Ti lasts.

Using the envelope shown in FIG. 3(b), the PI at address 2 specifies T1 and the PN is 6. At address 8, PI is +6 (-2
T1) and the pH is 9. In the release address RAD, PI specifies T1 and PN is 6.

The procedure for reading out the parameter ROM'i in the data format shown in FIG. 6 in the embodiment shown in FIG. 4 will be explained. The key is '? When it reaches 5N, the RAD at address 0 is first stored in the RAD register. Next, the slope data 8LOPE is stored in the full readout register 31 (FIG. 4).

After that, PI and PNi are read and stored in the PI register and PM register. Next, all 1 of ΔE1 is read from address 3 and stored in register 3o. Then, it is subtracted by PNil and supplied to a 22-page bit shift 38 corresponding to TvTs determined according to PI. In this way, the envelope sample LEI,j during the interval T1 is calculated. Immediately before the end of T1, read ΔE2 from address 4 and store it in the register 30,
PNf, (Decrement by 1. In this way, when you advance to address 7, PH=o, so next you can see that PI and PN are stored. Therefore, read address 8, and write the P register and PN Store it in a register, and
Thereafter, ΔE6 is read and stored in the register 3o, and the register 31 is cleared. Further, calculate P N - 1, and according to the PI code, write the bit shift code corresponding to +6 (-2T+) to the bit shift register 38.
supply to. Since PN becomes zero when the address RAD-1 is reached, it can be seen that PI and PH are stored next. Then, by performing the same operation as at address 8, the release process begins. The fact that RAD is the release process is RAD.
Since this can be determined by comparing the data in the register with the current address, after reading ΔlE19, it is possible to read out +9 at the same Δ, setting it to 23·−1. If the key continues to be ON, it is sufficient to stop in front of the RAD address. If the key turns OFF in the state before RAD, @(d, AD register contents 1RA
Just change it to D and enter the release process.

If 5LOPE data is provided as shown in Figure 6, ΔF1~
The data length at the rising edge of ΔE5 can be reduced,
Data can be compressed. The 5LOP data shows the average slope of the envelope shape of FIG. 3(b), and ΔE1 to ΔE5 are 0 minutes from the slope. In the release process, reverse slope data, that is, negative slope data may be provided to RAD.

The read arithmetic control device 26 for reading out the parameter ROM for data formation shown in FIG.
Equipped with I register, PN register, Muku register, RAD register, etc., and MLU (arithmetic logic unit), j
It can be constructed using well-known circuits such as a ROM that instructs the operating procedures of 'rt, a program counter, and an instruction decoder for a nato microcomputer. Furthermore, it is also possible to construct the system using the microcomputer itself.

In the above description, the case where one type of envelope signal is generated has been explained. Since a musical tone generally includes a plurality of frequency components, a plurality of envelope signals are required. In addition, when producing not only i1i notes but also compound tones, a separate envelope signal is required for the zo 扛 zo 扬 sound. To this end, in the embodiment shown in FIG. 4, a plurality of registers are provided inside the registers 34, 36, 40, and adders/subtracters 33, 39, subtracters 37, . Log-linear converter 36. The bit shift register 38 can be used by time division multiplexing. Register 34 t 3
6) 40 may be a shift register having the number of stages equal to the number of multiplexing. The operating procedure of the first read operation control unit 26 may also be configured to perform time-division operations in accordance with the number of multiplexed units.

FIG. 8 shows a system in which the sampling arithmetic unit of the uninvented envelope signal generator explained in FIG. This is an embodiment in which the data is transmitted and the calculation procedure 261''-7 is executed under program control.

In FIG. 8, reference numeral 60 is an address controller which connects the address code DR from CPtT3 in FIG.

Data DB, input/output command signal xoRQ, write command signal W
In response to R, the address program DI is sent to the parameter ROM 7, and n data specified by the address program D is read from the parameter ROM 7 via the data bus RI)B. 51t
j. A timing pulse generator (TPG) generates internally necessary pulse signals from the master clock frequency. The TPO-51 can be constructed using a clock oscillator, a counter, and a gate. 62 is a sequencer, and an RO that stores a procedure for outputting an address, a write command signal, a read command signal, etc., which will be described later, according to a calculation procedure.
It is M. Reference numeral 63 denotes an instruction decoder which inputs the instruction code output from the sequencer 62 and outputs an address code, a write command signal, and a read command signal.

Reference numeral 64 denotes a tremolo modulation register which receives a difference value of periodic fluctuation data that produces a 26-basis tremolo modulation from a data bus RDB and stores it at the rising edge of input jLWR1. ? 5
When c1 is 11", the contents are output to the bus. The slope register 66 receives slope data from the data bus RDB and stores it at the rising edge of 11.W R2. When 002 is °'1", it is output to the bus. . ADl has one of the 120 registers in the slope register 56.
1. No address code is given to specify the address. Ru. 66 is a dB difference register consisting of 120 data registers, one of which has a constant value of 111 for each person D1. Then, at the rising edge of WR3, the data bus RDBjvdB receives and stores the differential data, and when OC3 is "1",
The contents are output to the B bus. 67 is an envelope
“The pre-register consists of 120 data registers, one of which is specified by the address code D2.
, C bus J:0 is supplied and the data S, 1i is stored at the rising edge of WR4. When OC4 is t1'', it outputs the envelope sample data Sn on the dB scale to the bus. 68 is a logarithm-linear converter, which latches the data Sn supplied from the C path at the rising edge 9 of WRa. Then, the envelope sample LEn subjected to logarithmic-linear conversion is output to the bus when OC6 is 1''. 69 is an envelope sample register, which is made up of 120 registers, one of which is specified by the address code D3, and the envelope sample LEn supplied from the C bus is latched at the rising edge 9 of WRa. When is "1", it is output to the B bus.

60 is a working register (WRlo) which is composed of two word registers, one of which is selected by the n1 address code D3, and the data supplied by V from the C bus is stored internally at the rising edge of WB2. 607 people °′1
”, the contents are output to Mbus, and 6C7B is °1
”, the contents are output to the B bus. 61 is an adder/subtractor that calculates each input data of the bus and the B bus, and outputs it to the C bus. The selection of addition/subtraction is made by the instruction decoder s3.
i,・9 specified.

62 is a differential envelope data register that stores ΔLXn. It consists of 2o q registers, one of which is selected by the address code D4 and internally stores ΔLEn output from the adder/subtractor 61 at the rising edge of jL and WRlo.

63Fi, the difference envelope data register is composed of 120 data registers, one of which is address data A.
The input data specified by D5 is stored when WRa rises? It is output when 508 is "1".

64 is a shift gate for shifting input data by a predetermined number of pits. How many bits to shift is 5HI
Specified by FT signal. The shifted n signal corresponds to data δnK:iJ. 65 is an adder/subtractor for accumulation. 66 is a register that receives and stores the output of the adder/subtractor 66, and is made up of 120 registers. Address data AD
One of them is specified by 5, WB9 stands -1-
It is stored as 5 and output when QC9 is "1".

In the embodiment shown in FIG. 8, 2:0 envelope signals corresponding to 920-order frequency components per row are generated simultaneously for 8 channels, that is, 8 tones, by 2°×82160.
160-fold time division multiplexing operation is performed. 8
The number of the notes is expressed as 129”: ~8, and the number of the 20 notes is expressed as Knee 1 to 2o.
represents.

The calculation procedure will be explained next. Instead of the subscript n used earlier, i is used here.

WRKG ←5LOPE (K, r) +ΔEi (K,
I) (6) WRICG 4- WRI! :G
+ 5i (K, I) (7) Si++ (
L I )←WRIEG +ΔAMi(K , I
) (s)LOG/LIN 4-WRRG
+ΔAMi(K, I) (9)ΔLEi++(K
, I)←LOG/IJN -Lm! :i(K,I)
θ0)LEi+, (K, engineering)←1. OG/LIN
(11) First, by equation (6), 5LOP
E (K, I) is read from the slope register 56, dB difference data ΔX1 (K,
Store at 0. Next, (as in formula 4, the contents of the working register 6o and the contents 81 of the envelope register 57
(K, I) are read out, added, and stored in the working register 6o. Next, according to equation (8), the contents of the working register 6o and the tremolo modulation register 54 are calculated.
The contents ΔAMP (Ni) are read out and added to obtain a new envelope sample Si++ (K + I), which is stored in the envelope register 67 at address (K, I).

Also, in equation (9), 19, the same answer is given by the logarithm-linear converter 68
write to the input latch of Next, according to equation (10), the output of the logarithm-linear converter 58 and the output of the envelope sample register 69 are read, and the difference ΔLICi+, (K,
I) in the differential envelope data register 62.
Write in the address. Next, according to equation (11), the output of the logarithm-linear converter 68 is LICi++ (K + engineering)
is written to address (K, I) of the envelope sample register 59.

In the above explanation and formulas (6) to (11), (K, I
) points to one of the 8×20=160 word registers. i is a positive integer and is a sample number that increases sequentially from 1 after detecting the key ON.

In order to execute the above calculation procedure, the address codes D1 to D4. -111' included command signal WR4~7.1
0. Read command signal? 5G1~6,7mu, 7B (6
) to (11) should be output in the order shown.

Expressions (6) to (11) are first converted to ~1 by E'(,■-
1 to 2 degrees, then x=2.・・・・・・
, 8 as 31. Go, - order, and return to the beginning, so that i can be advanced one by one. The differential envelope data register 62 consists of 20 word registers, knees 1-20. Therefore, once the new 20 Δ”i++(K, I) of k = 1 to 2o are found, then
This new ΔLIC1++ (L) is transferred to registers at corresponding 20 addresses inside the differential envelope data register 63. The speed of this transfer must match the reading speed of the differential envelope data register 63, that is, the updating speed of the address code D6. Further, this speed corresponds to the cycle at which the envelope data LEi,j is finally output. The address codem D6 of the differential envelope data register 63 always changes cyclically with a cycle of 160, and ΔIJ (K, I) is output one after another according to (K, I) determined by the address codem D5.

The shift gates 64', l, l, l are ΔLICi(K, I
) by a predetermined number of bits to obtain δi(K, engineering)'
r: Output and accumulated by the adder/subtractor 65 and register 66.

FIG. 9 shows an example of data in the parameter ROM 7 used in the embodiment shown in FIG. Address 0 consists of a MODE code that indicates the basic characteristics of the sound, such as percussive or normal envelope, and a harmonic control code that specifies the maximum number of 20 envelopes I-1 to I-20 to output. Address 1
is the previously mentioned release address. Addresses 2-21 are 2
This is a table of data specifying which envelope data is used by each time slot corresponding to 0 envelope signals. Addresses 22 to 41 are 20 pieces of slope data. Address 42 has the point interval PI and point number PNT of the rising portion. 43-62,
63-82. ......, 2 each for addresses 103 to 122
This is PM group dB difference data of 0 each. 12
These are the PI and PN at address 323. 124-143,1
44-163.164-183. ......, 204
~223 are 20 dB difference data each. From then on, the arrangement is the same. A plurality of sets of parameters with such a configuration are prepared. A set of soranzopan is provided to correspond to a particular bandit of a particular tone.

33-7 When the address code, data, control signal octave data, and key 0NOFF data are supplied from the CPU 5 (FIG. 1) to the address controller 50 in FIG. Then, the start address of the area containing the parameter set corresponding to the note octave in the specified tone color area in the parameter ROM is found.

(This start address may be given directly from the CPU 3.) This start address is supplied via the parameter ROM head address path D, and the data 1R
It is read from the DB and stored in the internal register of the address controller 50. Advance the addresses one after another,
Import data from addresses 0 to 21. Next, the slope data is read from addresses 22 to 41 and stored in the slope data register 66. Next, the PI and PN at address 42 are stored in a predetermined register in the address controller 5o.

Next, the dB difference data ΔIE1(K,
I)'f: dB difference Stored in register 66. Since the data 34-27 have been read in above, calculations of equations (6) to (11) can be performed according to the procedure described above. mode, harmonic limit code,
Since the release address, time slot/envelope number table, PI, PH, etc. are necessary for each channel, registers for storing them are provided inside the address controller.

In FIG. 9, the harmonic limit code M is a number from 1 to 20, and specifies that zero is output as an envelope sample that exceeds this number M and is less than or equal to 20. For this, (M+1
) to 20, by applying a large negative number as ΔEi, a large negative number is set as ΔLEi, and by keeping the shift mouse small, δi is set to a large number of 1'1. By doing this, the adder/subtractor 6
The cumulative value at 6 is made a negative number. On the other hand, in general, envelope samples may typically be zero or positive values. therefore,
When the calculation result of the adder/subtractor 66 is negative, a control line 68 is provided so as to detect this n and forcibly output zero. By doing this, unnecessary envelope samples can be reduced to zero.

36. In FIG. 9, the time slot/envelope number table is expressed as I
When substituting other data Δ"i (K+I') (1'\X) with different values, a correspondence table between I and I' is provided.

If we keep it like this, ΔEi (K, I) does not need to have all of I-1 to 20, but Knee 1 to 10.
For X-11 to 20, prepare Knee 1 to 1.
It is possible to select an appropriate one from 0 or one with a similar shape. For this purpose, in the calculation of knees 11-20, ΔEi (K, I) corresponding to knees 1-1°
It is sufficient to perform an address conversion operation such as outputting the address stored in the address. This kind of address translation is
This can be achieved by operations similar to those of relative addresses and indirect addresses on microcomputers and minicomputers.

The data supplied to the tremolo modulation register 1 meta 54 in FIG.
All you have to do is read out what is stored in .

As described above, by using the lean-pull arithmetic unit of the microprocessor structure shown in FIG. 8, a predetermined operation can be performed in one log using a group of registers connected to a pass line, an adder/subtractor, etc.

The procedure of equations (6) to (11) is one example, and it is possible to omit some data or change the procedure.
Therefore, various embodiments can be constructed.

Address controller 60. Timing pulse generator 61. Sequencer 62. Since the instruction decoder 63 is already known in various microprocessors, its details will be omitted.

In the above explanation, when the key remains in the ON state, a certain envelope sample is continued to be output before the release address RAD, but when it reaches RAD-1, it is skipped to an even earlier address after that. For example, as explained in FIG. 3(b), the address operation may be performed by repeating steps S6 to S15. Also, 86~
Since S15 is repeated, it may be possible to jump to an appropriate address between 86 and g+5. Such address manipulation can be realized by adding or subtracting a random code output from a pseudo-random sequence generator to or from an address.

As a type of release process, musical instruments require damping or high-speed muting. When such a request occurs, by setting the dB difference data to a large negative value, rapid attenuation can be achieved through accumulation. For this purpose, it is sufficient to create a procedure for writing a predetermined value as ΔEi.

FIG. 10 is a diagram showing the timing of the embodiment of FIG. 8. Fig. 10 (m) shows a sample arrangement of a sine wave waveform, and the sample period of one sine wave waveform is 20.
It is μs. FIG. 10(B) is an enlarged view of 2071s, in which there are 8×20=160 time slots and 160 samples. Each sample is processed in 125 ns increments. channel 1
(CHl) has 20 samples. CH2N2
The same is true. On the other hand, FIG. 10(C') is the timing at which the envelope sample ΔlIC4,j for the difference of 38 pages is calculated in synchronization with (M). Channel time slots OH8 in units of 16011 Bf are provided from 1 to 8 〇0H8
1, the calculation of ΔLICI(1,I) of channel 1 is performed, and the calculations of the corresponding channels are performed in the following order. 160X8=12807r8 (1,28m5)
The ΔLEi calculation for each channel is repeated 9 times.

FIG. 10(D) shows each channel time slot CH8.
This shows the inside of CH31 as an example. CH31 has processing time slots 1 to 1 in units of 5 μs. PTS ranges from 1 to 32. P
TS(I), in channel 1 for I=1 to 20,
Calculate difference envelope samples ΔLICi (K, I) corresponding to 20 spectra (sinusoidal waveforms). And P
In the first 26 μs of TS21, it is calculated that 20
The ΔLICI(K, I) values are transferred to the differential envelope register 63 (FIG. 8) in 125 ns increments as shown in FIG. 10(F). The timing of this transfer is CH31
~8 is a hole. For example, in CH35, the processing is executed in the latter half of PST24. Figure (K) is an enlarged view of the contents of each processing time slot PT81 to PT20. It is divided into 6 parts: PT81-201d, instruction time slot, and ITS1-60. Its length is 5 sons. In this instruction time slot ITS, the above (6) to (
11) The command in formula is executed.

Between PT81 and PT200, in the embodiment of FIG. 8, calculations centering on the adder/subtractor 61 are performed.

Between PTS21 and 32, ΔAMi(K
, I)+5LOPIC(K,I),ΔEi(K,I)
Data bus D is used to write new data centered on
This is done via B'.

In the shape of the envelope shown in Figure 3, in the case of a percussive type, if the attenuation is an exponential function, ΔE can be a constant value regardless of i in the attenuation process.
fiS found that it is sufficient to have a type of ΔE as a representative value in the attenuation process, allowing for significant data compression.

As for the conversion characteristics of the logarithmic-linear converter 35 in FIG. It's okay.

As described above, the envelope samples are stored as digital data, and interpolation calculations are performed based on the data, so the data can be smoothly continuous based on sparse envelope samples. Envelope signal data is obtained.

[Brief explanation of the drawing]

Figure 1 is a block diagram of an electronic musical instrument adopting the present invention;
FIG. 3 is a block diagram showing the basic configuration of the invention, FIG. 3 is a diagram showing the envelope signal waveform handled by the envelope signal generator of the invention, and FIG. Tsuku diagram, No. 6
6 is a diagram showing an example of the format of data used in the present invention, FIG. 7 is a diagram showing an address calculation register,
FIG. 8 is a block diagram of another embodiment of the present invention, FIG. 9 is a diagram showing an example of its data format, and FIG. 10 is a diagram showing its timing chart. 7...n"] Memory stack 20...Sample calculator, 23...Interpolation n1 calculator. Name of agent -+":r!11: Nakao Toshio and 1 other person JP-A-58-20029G (14)

Claims (1)

[Scope of Claims] (1) A digital storage device that stores envelope signals of musical tones, a sample calculator that sequentially reads envelope signals from the storage device and generates envelope samples, and the envelope sample an interpolation calculator that performs interpolation calculation between adjacent ones of the envelope signal generator. (2. In the statement of claim 1, the storage device stores slope data corresponding to the slope in at least one of the rising and falling sections of the envelope signal, and the sample arithmetic unit stores slope data corresponding to the slope data in at least one of the rising and falling sections of the envelope signal. An envelope signal generator capable of generating a steep envelope signal by adding a specified slope value to the envelope samples in the rising and falling sections. (3) Claim 1. (4) The description of claim 1, in which the envelope sample generation period is made variable and the interpolation calculation interval is made variable in accordance with the raw 2-basis generation period. An envelope signal generating device in which reading of digital data stored in a memory device is made to jump to an address in the release process when the key is OFF. An envelope signal generating device characterized in that the address of the data changes randomly when the key 6N continues to be pressed for a long time when reading out the digital data stored in the envelope signal generator. 2. The envelope signal generating device according to item 1, wherein the sample arithmetic unit and the interpolation arithmetic unit are time-division multiplexed to generate a plurality of envelope signals.