JPH02181797A - Musical tone signal synthesizer - Google Patents

Abstract

PURPOSE:To control many frequency components with simple constitution by converting the address values of input phase address signals at every section by the functions set discretely for each of the respective phase sections and making access to a waveform table. CONSTITUTION:An address converting part 72 of a 2nd musical tone signal generating circuit 14 divides the phase within one period to plural sections and respectively converts the address values of the output phase address signals of an adder 68 for each of the respective sections according to the functions set discretely for each of the sections. The waveform table linear 71 in which the waveform data of the prescribed waveform functions are stored in linear expression is accessed by the output of this address converting part 72. The prescribed waveform functions, for example, sine wave functions stored in the waveform table 71 and the waveform data of the waveform functions different therefrom are eventually outputted from the waveform data 71 in response with the phase address signals in this way. The musical tone signals including the many frequency components are thus synthesized by the modulation computation with the relatively simple constitution.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a musical tone signal synthesis device that synthesizes musical tone signals using modulation operations such as frequency modulation operations and amplitude modulation operations, and in particular, relates to a musical tone signal synthesis device that synthesizes musical tone signals using modulation operations such as frequency modulation operations and amplitude modulation operations, and particularly relates to a musical tone signal synthesis device that synthesizes musical tone signals using modulation operations such as frequency modulation operations and amplitude modulation operations. This invention relates to being able to control a large number of frequency components.

[Conventional technology]

Techniques for synthesizing musical tone signals with a desired overtone composition by frequency modulation calculations in the audible frequency band have been known for a long time, but in order to synthesize musical tones with a satisfactory timbre that has sufficient overtone components, a simple one-term method is required. Frequency modulation calculations using expressions are insufficient, and frequency modulation calculations using multiple or polynomial expressions have to be performed. As a result, the configuration of the arithmetic circuit becomes complicated and large, and in a system in which each arithmetic term is computed in a time-sharing manner, the control clock has to be increased in speed, which tends to increase costs.

On the other hand, as a method of synthesizing musical tones containing many harmonic components through relatively simple calculations, a method has been considered in which a waveform with many frequency components is used as a modulating wave or a modulated wave. Since it was limited to what was stored in the waveform memory, there was a limit to the tones that could be synthesized.

In order to solve the above-mentioned problems, the patent application No. 58-1
In No. 90869, waveform data is stored in a logarithmic representation in a waveform table used for generating a modulated wave or a modulated wave function, and the logarithmic representation of waveform data read from this table is multiplied by a coefficient. It has been shown that a complex waveform function can be obtained when logarithmically expressed waveform data, which is the result of multiplication, is linearly transformed. According to this, it is possible to easily convert a modulating wave or a modulated wave function into a complex one different from that stored in a waveform table, so a musical tone signal containing many frequency components can be easily converted with a relatively simple configuration. It can be synthesized by modulation calculation.

[Problem to be solved by the invention]

However, the technology shown in the above-mentioned prior application can be applied when waveform data is stored in logarithmic representation in a waveform table, but cannot be applied when waveform data is stored in linear representation in a waveform table. There was a problem. Furthermore, when waveform data is stored in logarithmic representation in a waveform table, a logarithmic/linear conversion circuit must be provided at a subsequent stage.

This invention has been made in view of the above points, and is used for modulation calculations when using a waveform table that stores linearly expressed waveform data as a waveform table used for generating a modulated wave or a modulated wave function. By making it possible to convert the modulated wave or modulated wave function into a complex one different from that stored in the waveform table with a relatively simple configuration, it is possible to convert many frequency components with a relatively simple configuration. It is an object of the present invention to provide a musical tone signal synthesis device capable of synthesizing musical tone signals including the following by modulation calculation.

[Means to accomplish the task]

A musical tone signal synthesis device according to the present invention includes a waveform table storing waveform data of a predetermined waveform function in a linear representation, and a phase address signal supply means for supplying a phase address signal for a modulated wave signal or a modulated wave signal. , address converting means for dividing the phase within one period into a plurality of intervals and converting the address value of the phase address signal for each interval according to a function individually set for each interval, the address converting means By accessing the waveform table using the output of the waveform table, waveform data of a waveform function different from the predetermined waveform function is outputted from the waveform table in response to the phase address signal.

[For production]

In the address conversion means, the address value of the input phase address signal is converted for each interval by a function that is individually set for each interval, so the input phase address signal has non-linear characteristics when viewed over one period. (In other words, non-linear conversion characteristics are realized as a whole by the combination of conversion functions for each phase interval). Since the waveform table is accessed by the converted address signal, the relationship between the input phase address signal and the address signal that actually accesses the waveform table becomes nonlinear, and as a result, it differs from the predetermined waveform function stored in the waveform table. Waveform data of the waveform function will be output from the waveform table in response to the phase address signal.

For example, even if a monotonous sine wave function is stored in the waveform table, by appropriately setting the address conversion function for each phase interval, waveform data with an approximate number of sin'' waves can be obtained from the waveform table. can do.

Further, it is possible to appropriately set the address conversion function for each phase section so that other appropriate waveform functions can be approximately obtained.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(Explanation of the overall configuration of the embodiment) In FIG. 1, a keyboard 10 is equipped with a plurality of keys for specifying the pitch of musical tones to be generated,
1 detects key presses and key releases on the keyboard 10, and provides a signal corresponding to the detected key presses and key releases to the sound generation assignment circuit 12. The sound generation assignment circuit 12 is for allocating the sound generation of a musical sound corresponding to a pressed key to one of a plurality of musical sound generation channels, and generates a key code indicating the key assigned to that channel at the time division timing corresponding to each channel. It outputs a key-on signal KON indicating whether or not the suppression of KC and its key continues, and a key-on pulse KONP corresponding to the rise of the key-on signal KON. - As an example, the number of musical tone generation channels is 8 channels.

The key code KC output from the sound generation assignment circuit 12 is given to a first musical tone signal generating circuit 13 and a second musical tone signal generating circuit 14.

The first musical tone signal generation circuit 13 generates a musical tone signal having a pitch determined by a given key code KC, and outputs the musical tone signal at a first sampling frequency fs synchronized with this pitch, This is a pitch-synchronized musical tone signal generation circuit.

The number of musical tone generation channels in the first musical tone signal generation circuit 13 is eight as described above, and digital musical tone signals are generated in accordance with the key code KC assigned to each channel.

- As an example, the musical tone signal generation method in the first musical tone signal generation circuit 13 includes a storage means in which waveform data of a plurality of musical waveforms corresponding to various tones are stored in advance, and the musical tone signal generation method corresponds to the selected tone. waveform data is read from this storage means, and a musical tone signal is generated based on the read waveform data.For convenience, this method is referred to as rPCM.
It is abbreviated as "Method".

The second musical tone signal generation circuit 14 generates a musical tone signal having a pitch determined by a given key code KC, and outputs the musical tone signal at a second sampling frequency fs2 asynchronous to this pitch. This is an asynchronous musical tone signal generation circuit.

The number of musical tone generation channels in this second musical tone signal generation circuit 14 is also 8, as described above, and digital musical tone signals are generated in accordance with the key code KC assigned to each channel.

- As an example, the musical tone signal synthesis method in the second musical tone signal generating circuit 14 is to generate musical tone signals by executing a frequency modulation type musical tone synthesis operation, and for convenience, this method is abbreviated as "rFM method". do.

The output musical tone signals of the first musical tone signal generating circuit 13 and the second musical tone signal generating circuit 14 are digitally added and synthesized by an adder 15, and the added output is converted into analog by a digital/analog converter 16, and then the sound system 17;

The timbre data generation circuit 18 outputs timbre data TC corresponding to the selected timbre.

This tone color data TC is applied to the first musical tone signal generating circuit 13 and the second musical tone signal generating circuit 14, respectively, and specifies the tone of the musical tone signal to be generated by each musical tone signal generating circuit 13, 14. Each musical tone signal generation circuit 13, 14 is nominally designated with a common tone by this tone data TC, but the tone may be slightly different depending on the musical tone signal synthesis method, and the time of the tone may be slightly different. The presence or absence of the change and its mode may be different as appropriate, and in any case, the sound quality of the generated sound may be different between the picture frame sound signal generation circuits 13 and 14 as appropriate.

The envelope generator 19 is connected to each musical tone signal generating circuit 13.
Envelope signal EVI used in 14.

It generates EV2. This envelope signal E
VI and EV2 contain envelope signals for various functions, such as an envelope signal for setting the volume level of the musical tone signal output from each musical tone signal generation circuit 13 and 14, and an envelope signal for setting temporally variable control of the tone color, etc. is included. In addition.

The envelope signals for setting the volume levels of the musical tone signals outputted from each musical tone signal generating circuit 13 and 14 are ultimately generated by each musical tone signal generating circuit 13 in the adder 15.
．． It functions as a coefficient for controlling the addition ratio of the 14 output musical tone signals, and also functions as a coefficient that changes over time in order to change the addition ratio over time.

The timing signal generator 20 generates various timing signals for controlling time division processing and other various operations.

The first musical tone signal generation circuit 13 and the second musical tone signal generation circuit 14 generate musical tone signals having a pitch corresponding to a common specified pitch according to the key code KC for each channel given from the sound generation allocation circuit 12. is generated for each channel. Of course, an appropriate pitch shift, pitch, or scale shift may be applied between the first musical tone signal generating circuit 13 and the second musical tone signal generating circuit 14 as necessary.

For example, each of the musical tone signal generating circuits 13 and 14 may independently perform controls such as tuning, transposition, vibrato, glide, and pitch control.

As an example, when adding and synthesizing the output musical tone signals of the two-system tone signal generation circuits 13 and 14, if they are combined and synthesized at an appropriate addition rate over the entire sound generation period from the start of sound generation to the end, it is possible to achieve a common pitch and a common tone signal. It is possible to obtain a duet effect in which two tones of different tones (although the actual pitch and tone quality can be slightly different as appropriate) are generated simultaneously. That is,
The maximum number of sounds is eight, which corresponds to the number of channels in each musical tone signal generation circuit 13, 14, and by simultaneously producing two series of these tones, a multiplayer effect can be obtained.

As another example, the output musical tone signals of the two-system tone signal generation circuits 13 and 14 may be switched and distributed while being cross-faded as appropriate depending on the sound generation stage such as the rising part and the sustaining part of the sound, and these signals may be combined. They may also be synthesized, in which case it is possible to perform optimal musical tone synthesis according to the stage of sound production.

The first musical tone signal generating circuit 13 is provided with a note clock generating circuit 21 (FIG. 3) for pitch synchronization, which generates a note clock pulse NCK having a frequency corresponding to the pitch of the musical tone to be generated. Occur. If a musical tone signal is generated in accordance with the generation timing of this note clock pulse NCK, the effective sampling frequency of the musical tone signal and its pitch are harmonized, and furthermore, note clock pulses NCK of all pitches are the basis of the system. Pitch synchronization is achieved by setting the sampling frequency fs1 to match the standard sampling frequency fs1.

By the way, in this embodiment, the first musical tone signal generation circuit 1
3, musical tone signals for each channel are generated in a time-division manner, and the note clock pulse NCK for the tone assigned to each channel must be generated in a time-division manner for each channel. Furthermore, in order to improve the precision of pitch synchronization, it is desirable that the frequency of the note clock pulse NCK is also relatively high. Therefore, the generation of the node clock pulse NCK and the pitch synchronization processing in the first musical tone signal generation circuit 13 are required to operate at relatively high-speed time division timing.

On the other hand, the sound generation allocation circuit 12 and the pitch-asynchronous second musical tone signal generation circuit 14 are not required to operate at such high-speed time division timing, but rather the time division timing should be relatively slow due to the circuit configuration or musical tone signal generation circuit 14. This is preferable in terms of generation arithmetic processing.

Therefore, in this embodiment, the necessary circuits are operated at two time-division operation speeds: high speed and low speed. In other words, the circuit parts that do not require high-speed time division processing in the sound generation allocation circuit 12, the pitch-asynchronous second musical tone signal generation circuit 14, and the first musical tone signal generation circuit 13 perform time division processing for each channel at low-speed time division timing. The circuit portion of the first musical tone signal generating circuit 13 that requires high-speed time-division processing performs time-division processing of each channel at high-speed time-division timing. Therefore, the outputs KC, KON, and KONP of the one-tone allocating circuit 12 are output at slow time division timing. However, in the first musical tone signal generation circuit 13, there are circuit parts that require high-speed time division processing, so in order to match this, there is a method for converting the time division speed of the signal from low to high speed, and conversely, from high to low speed. Means for converting the tone signal into the musical tone signal generating circuit 13 is provided inside the musical tone signal generating circuit 13.

Next, detailed examples of each circuit in FIG. 1 will be explained.

(Explanation of time division timing) First, an example of low speed and high speed time division timing will be described with reference to FIG. 2.

High-speed time division timing is 1 to master clock pulse.
The period is formed as one time slot. Assuming that the number of time-division musical tone generation channels is 8, the time slots of the first to eighth channels in the high-speed time-division timing, that is, the high-speed channel timings are as shown in the column Hch in FIG. Therefore, the sampling period of one note at high-speed time division timing is eight times as long as the master clock pulse.

The low-speed time division timing is master Kurotsuta pulse~8
It is formed with one period of the clock pulse φL having twice the period as one time slot. The time slots of the first to eighth channels in the low-speed time division timing, that is, the low-speed channel timings are shown in the Lch column of FIG. 2. Therefore, the sampling period of one note at the low-speed time division timing is 8 times the clock pulse φL (64 times the master clock pulse ~).

If the frequency to the master clock pulse is 3.2 MHz, the sampling frequency of one note at the high-speed time division timing Hch (this is the first sampling frequency fs1
(corresponding to the second sampling frequency fs2) is 400kHz, and the sampling frequency of one note at the low-speed time division timing Lch (corresponding to the second sampling frequency fs2) is 50kHz.
It is Hz. In this way, the first sampling frequency f
The relationship between s□ and the second sampling frequency fs is set to be an integral multiple.

In FIG. 2, a channel synchronization pulse CH is used when converting the time division speed of a signal from low speed to high speed or vice versa. This pulse CH is a total of 8 pulses generated in correspondence with the high-speed time division timing of each channel 1 to 8 only once during one cycle of the low-speed channel timing to 64 (64 cycles to the master clock pulse). Consists of pulses. For example, one pulse is generated at the high-speed time division timing of channel 1, one pulse is generated at the high-speed time division timing of channel 2 9φ□ (9 cycles to the master clock pulse) after that, and then one pulse is generated at the high-speed time division timing of channel 2. 1 pulse is generated at high-speed time division timing, and thereafter each channel 4, 5, 6, 7.8
One pulse is generated at the high-speed time division timing of channel 8, and after one pulse is generated at the high-speed time division timing of channel 8, it returns to the high-speed time division timing of channel 1 after that 1 (one cycle to the master clock pulse). 1 pulse is generated.

(Explanation of P number) In order to perform pitch-synchronized musical tone signal formation in the first musical tone signal generation circuit 13, for example, a "P number" is used.
The information is used. The "P number" is a number indicating the number of sample points in one period of a musical sound waveform having a frequency corresponding to each pitch.

Since it is possible to time-divisionally generate multiple tones of arbitrary pitches, the basic sampling frequency in the first musical tone signal generation circuit 13, that is, the first sampling frequency fs
, is common to all pitches, and has a period eight times that of the master clock pulse (frequency of 400 kHz), as described above. On the other hand, since the basic sampling frequency is common, the P number of each pitch shows a different value depending on the pitch frequency. Let fn be the frequency of the pitch, and let fs be the common sampling frequency mentioned above.
Then, the P number corresponding to that pitch can be determined as follows, for example.

P number=fs, ÷fn”・(1)(
Description of Note Clock Pulse) In the note clock generation circuit 21 (FIG. 3), the note clock pulse NCK is obtained by dividing the common sampling frequency fs1 established based on the master clock pulse according to the P number. . As is clear from the above, the P number is the number of cycles of the common sampling frequency fs in one cycle waveform, that is, the number of sample points,
On the other hand, the effective number of sample points per period of musical waveform that can be generated by the first musical tone signal generation circuit 13 is set to N (for example, N=
64), then the frequency division number for dividing the common sampling frequency fs is frequency division number = P number ÷ N, (2), then the frequency division output is N pulses per period of musical tone. can be obtained, thereby establishing all N effective sample points. When the common sampling frequency fsi is divided by the frequency division number determined in this way, from equations (1) and (2) above, fs1 ÷ frequency division number = (fn X P number) ÷ (P number 10 N) = fnXN =fe0. -(3), and the effective sampling frequency fe can be established by changing the sampling point address using this frequency-divided output. The effective sampling frequency fa thus established is in harmony with the pitch frequency fn, and pitch synchronization is achieved. The note clock pulse NCK generated from the note clock generation circuit 21 is as described in (3) above.
This is a frequency-divided output signal, that is, a signal having an effective sampling frequency fe as shown in the equation.

By the way, the number of divisions determined by the above equation (2) is not necessarily an integer and often includes a decimal number.Therefore, the frequency division operation in the node crotter generation circuit 21 is performed using two numbers close to the number of divisions determined by the equation (2). The frequency is appropriately divided by an integer, and the average result is the same as that obtained by dividing the frequency by the frequency division number determined by equation (2).

(Detailed example of the first musical tone signal generation circuit 13) FIG.
This figure shows a detailed example of the musical tone signal generation circuit 13 in which the P number memory 22 stores P numbers for each pitch in advance. Low speed time division timing L from the sound generation allocation circuit 12
The key code KC of each channel given by ch is input into the P number memory 22, and the P number is read out corresponding to the pitch of this key code KC. The read P number is a signal of the same low-speed time division timing Lch.

The low/high speed converter 23 converts the time division timing of the P number read from the P number memory 22 at high speed. This low/high speed conversion unit 23 includes a selector 24 which inputs the output of the P number memory 22 to the "1" input, and an 8-stage shift register 2 corresponding to the number of channels 8.
5, and the output of the shift register 25 is circulated through the "0" input of the selector 24.

A channel synchronization pulse CH (see Figure 2) is input as a selection control signal to the selector 24, and this pulse is set to "1".
``1'' input is selected when the value is 0'', ``0'' input is selected. Shift register 25 is shift controlled by master clock pulses.

The P number read out from the memory 22 when channel 1 has a low-speed timing is selected by the selector 24 and taken into the shift register 25 when the channel synchronization pulse CH becomes "1" during the high-speed channel 1 timing. . Similarly, when the P number read at the timing of other slow channels 2 to 8 becomes 1'1''' at the timing of the corresponding high speed channels 2 to 8, the selector 24 selected, shift register 2
5. The P number taken into the shift register 25 is stored in the r of the selector 24 until the next time when the pulse CH becomes 11" at the high speed timing of that channel.
It is cyclically held in the shift register 25 via the OJ input. In this way, the eight stages of the shift register 25 contain P numbers corresponding to the pitches of the keys assigned to channels 1 to 8, which are shifted in accordance with the master clock pulse and at a period eight times that of the master clock pulse (that is, the common It is repeatedly output (with a period equal to the sampling frequency fs).

Therefore, the timing of the P number of each channel output from the shift register 25 is a high-speed time division timing as shown in the Hch column of FIG.

The P number data of each channel converted into high-speed time division timing is input to the note clock generation circuit 21. The note clock generation circuit 21 performs the division operation as described above according to the input P number, and sends the note clock pulse NCK having a frequency corresponding to the pitch of the musical tone assigned to each channel to the high-speed time division timing Hc.
This occurs in a time-divisional manner according to h.

Note that in the above explanation, it was assumed that the P number was stored in the memory 22 in correspondence with each pitch.
Of course, the present invention is not limited to this, and only the P numbers corresponding to each of the 12 note names C-B in the standard octave may be stored in the memory 22, and the octave control may be performed within the note clock generation circuit 21. It is.

As a sound source in this first musical tone signal generation circuit 13,
A waveform memory 26 is used in which waveform data of a plurality of tone waveforms corresponding to various tones are stored in advance. - As an example, it is assumed that the entire waveform from the start of the sound to the end of the sound is stored in the waveform memory 26.

Since reading of the waveform memory 26 itself does not need to be performed at high-speed time division timing, the process of lowering the time division rate of the note clock pulse NCK generated from the note clock generation circuit 21 to a low speed is performed by the high/low speed converter 27. It will be held in

In the high/low speed converter 27, the note clock pulse N
CK is applied to gate 29 via OR circuit 28.

The gate 29 receives a key-on pulse KO given from the sound generation allocation circuit 12 (FIG. 1) according to low-speed time division timing.
It is controlled by a signal that is an inversion of NP, and is disabled only when the key is first pressed, and enabled at all other times.

The output of gate 29 is input to a 1-bit/8 stage shift register 30 and shifted in accordance with the master clock pulse. The output of shift register 3° is gate 31
, OR circuit 28. It is returned to the input side via gate 29. The gate 31 is enabled by a signal obtained by inverting the channel synchronization pulse CH with an inverter 32. On the other hand, the output of the shift register 30 is further applied to the latch circuit 33,
The signal is taken into the latch circuit 33 at the timing of the channel synchronization pulse CH.

With this configuration, the note clock pulse NCK of each channel is temporarily stored in the shift register 30 and circulated according to high-speed time division timing.

Then, by the channel synchronization pulse CH generated as shown in FIG. 2, the output of each channel of the shift register 30 is latched channel by channel into the latch circuit 33 at approximately the period of the low-speed time division timing. When the output of shift register 30 is latched into latch circuit 33, gate 31 closes, preventing the data from circulating and clearing the memory.

On the other hand, the data of the channel latched by the latch circuit 33 is also cleared when the channel synchronization pulse CH is generated next time. Therefore, when the note clock pulse NCK of a channel is "11", the data "1 jj
corresponds to the high-speed time division timing of that channel, and the pulse C starts when the channel synchronization pulse CH is generated.
It is held in the latch circuit 33 only for a period of nine or one cycle of the master clock pulse until H is generated next.

The phase address counter 34 includes an adder 35 inputting the output of the latch circuit 33, a gate 36, and an eight-stage shift register 37 whose shift is controlled by the low-speed clock pulse φL. The output of the shift register 37 is applied to an adder 35 and returned to the input side via a gate 36.

The signal obtained by inverting the key-on pulse KONP is the OR circuit 38
is applied to gate 36 via gate 36, thereby causing gate 3
6 is disabled at the beginning of a key press, and the old memory in the shift register 37 regarding the channel to which the key is assigned is cleared.

The output of the latch circuit 33 is applied to the adder 35 and added to the output of the shift register 37, and the result of the addition is stored in the shift register 37. This addition is performed at a period eight times as long as the low-speed clock pulse φL for one channel. On the other hand, the time width in which the data of the channel consisting of the latch circuit 33 is output is 9 or 1 to the master clock pulse.
Because of the period, the output of the latch circuit 33 is added only once to the output of the shift register 37 regarding the same channel. For example, the shift register 37 performs data capture and data shift operations in synchronization with the rising edge of the low-speed clock pulse φL < 41 Q 17 to 1'I I+). Thus, in the phase address counter 34, Each time a note clock pulse NCK is generated corresponding to a channel, the count value corresponding to that channel is incremented by one.

The output of phase address counter 34 is provided to adder 39 as a relative phase address signal.

The time division timing of the output of this phase address counter 34 is the low speed time division timing Lc shown in FIG.
It is h.

Tone color data TC generated corresponding to the selected tone color is given to a start address generation circuit 40 and an end address generation circuit 41, and the storage address area in the waveform memory 26 of the musical sound waveform corresponding to the tone color is stored in an absolute address. Start address value data and end address value data shown are output from each circuit 40, 41. The start address value data is applied from the start address generation circuit 40 to the adder 39 and added to the relative phase address signal output from the 1-phase address counter 34. The output of this adder 39 is applied to the address input of the waveform memory 26. The output of the adder 39 is also given to a comparator 42, where it is compared with the end address value data given from the end address generation circuit 41, and when the two match, an end pulse END is output. A signal obtained by inverting this end pulse END is applied to the gate 36 via the OR circuit 38, and the count contents of the corresponding channel in the phase address counter 34 are cleared.

In this way, the address value changes sequentially from the start address to the end address in response to the note clock pulse NCK, and in response, the waveform data of the entire waveform from the start of the sound to the end of sound generation is sequentially read out from the waveform memory 26.

The waveform data read from the waveform memory 26 is sent to the multiplier 4.
3 and is multiplied by an envelope signal EVI provided from envelope generator 19 (FIG. 1). The envelope-controlled digital musical tone signal thus output from the multiplier 43 is as follows.

This follows the low-speed time division timing Lch as shown in FIG.

The output of the multiplier 43 is input to a low/high speed conversion section 44 and converted into high speed time division timing Hch.

The low/high speed converter 44 includes a selector 45 and an 8-stage shift register 46 like the low/high speed converter 23 described above, and operates in the same way to change the time division timing of the musical tone signal to the high speed time division timing Hah. Convert to

The pitch synchronization circuit 47 resamples the musical waveform sample point amplitude data read from the waveform memory 26 in synchronization with its pitch (this is referred to as a pitch synchronization operation). This pitch synchronization operation is performed by the note clock pulse NCK generated from the note clock generation circuit 21. Therefore, the pitch synchronization operation in the pitch synchronization circuit 47 needs to be performed at the same high speed time division timing Hch as the note clock pulse NCK. For this purpose, the above-mentioned low/high speed converter 44 is provided, and converts the musical waveform sample point amplitude data signal read from the waveform memory 26 to the high speed time division timing H.
It is converted to ch.

The pitch synchronization circuit 47 has a selector 48 which inputs the output of the shift register 46 of the low/high speed converter 44 to the "1" input.
and an eight-stage shift register 49 which is shifted and controlled by a master clock pulse, and the output of the shift register 49 is returned to the input side of the shift register 49 via the "0" input of the selector 48.

A node clock pulse NCK generated from the note clock generation circuit 21 is applied to a control input of the selector 48 via a delay circuit 50. When the node clock pulse NCK given to the control input is "1", the selector 48 selects "1" from the shift register 46 of the low/high speed conversion section 44.
” selects the musical waveform sample point amplitude data given to the input, otherwise selects the output of the shift register 49 given to the “0” input, and holds the contents of the shift register 49 cyclically. The delay circuit 5o sets a time delay commensurate with the signal delay time on the other route to which the note clock pulse NCR is applied, that is, the route from the high/low speed converter 27 through the waveform memory 26 to the low/high speed converter 44. It is something to do.

Note clock pulse NCK is It in the time slot of the channel at high speed time division timing Hch
11), the tone waveform sample point amplitude data of that channel is selected by the selector 48 and stored in the shift register 49. In this way, the musical waveform sample point amplitude data of each channel output from the shift register 49 of the pitch synchronization circuit 47 changes in synchronization with the node clock pulse NCK of that channel.
Pitch synchronization is achieved.

The output of the pitch synchronization circuit 47, that is, the shift register 49
The output is given to an accumulator 51, and the accumulator 51 sums up the musical waveform sample point amplitude data of each channel for one sample point. The accumulator 51 includes an adder 52 that inputs the output signal of the shift register 49, and a register 53 that delays the output signal of the adder 52 by one bit time according to the master clock pulse.
, a gate 54 for inputting the output of this register 53 to the adder 52, and a latch circuit 55 for holding the output of the register 53. High speed time division timing H
The gate 54 is controlled by an inverter 56 inverting a clock pulse CHI (see FIG. 2) synchronized with the time slot of the first channel in the channel. Furthermore, the latch operation of the latch circuit 55 is controlled by this clock pulse CHI.

The musical waveform sample point amplitude data for one sample point of the first to eighth channels are sequentially accumulated according to the high-speed time division timing Hch, and when the data of all channels has been accumulated, the clock pulse CHI rises. , thereby latching the accumulated values of data of all channels in the latch circuit 55, closes the gate 54, and clears the accumulated values in the register 53.

The output of the latch circuit 55 is output as the output of the first musical tone signal generation circuit 13. In this way, the sampling frequency fsi of the output musical tone signal of the first musical tone signal generation circuit 13 becomes the sampling frequency of 400 kHz at the high-speed time division timing Hch, and is synchronized with the pitch of the musical tone signal.

(Detailed example of the second musical tone signal generation circuit No. 4) Figure 4 shows the second musical tone signal generation circuit.
This figure shows a detailed example of the musical tone signal generation circuit 14, in which an F number memory 60 stores F numbers for each pitch in advance. The key code KC of each channel given from the sound generation allocation circuit 12 (FIG. 1) at the low-speed time division timing Lch is input to the F number memory 6o, and the F number is read out corresponding to the pitch of this key code KC. The F number is numerical data proportional to the pitch frequency, and corresponds to a phase increment value per unit time.

The read F number is sent to the phase address accumulator 6.
1 is input. The phase address accumulator 61 is F
The number is repeatedly calculated at regular time intervals to generate a phase address signal corresponding to the phase angle ωt.

Phase address accumulator 61 includes an adder 62 into which the F number from memory 6O is input, an eight-stage shift register 63 whose shift is controlled by low-speed clock pulse φL, and a gate 64. The output of the shift register 63 is applied to the adder 62 via a gate 64 and returned to the input side. An inverted signal of the key-on pulse KONP is applied to gate 64, which disables it at the beginning of a key press and clears the old memory in shift register 63 for the channel to which the key is assigned.

The phase address signal ωt generated from the phase address accumulator 61 is given to the frequency modulation calculation section 65. The frequency modulation calculation unit 65 executes frequency modulation calculation for musical tone synthesis.

The frequency modulation calculation unit 65 uses one series of calculation circuits in a time-division manner under the control of the algorithm control unit 66 to execute frequency modulation calculation according to a predetermined calculation algorithm. In the illustrated embodiment, the simplest one-term frequency modulation calculation is performed in a time-division manner using two time slots. That is, while the time division timing of each channel in the second musical tone signal generation circuit 14 is the low speed time division timing Lch as shown in FIG. 2, a clock pulse having twice the frequency of the low speed clock pulse φL is used. The time slot of each channel at the low-speed time division timing Lch is divided into two by φL2 (see Figure 2), the first half of the time slot is used to generate a modulated wave signal, and the second half of the time slot is used to generate a modulated wave signal (carrier signal). ) is performed.

To explain the hardware configuration of the calculation circuit in the frequency modulation calculation unit 65, the shift circuit 67 transfers the phase address signal corresponding to the phase angle ωt to the phase address accumulator 6.
1, and by appropriately shifting this by an amount corresponding to the coefficient k, the angular frequency ω is multiplied by . Specifically, the frequency coefficient data kc of the carrier wave and the frequency coefficient data km of the modulated wave are output from the algorithm control unit 66 at appropriate timing, and the shift amount is controlled accordingly. In this way, the output of the shift circuit 67 is the instantaneous phase angle kcωt of the carrier wave signal or the instantaneous phase angle kmωt of the modulated wave signal.
φ indicates t.

An adder 68 to which the output of the shift circuit 67 is input is for performing phase modulation. When performing phase modulation, a modulated wave signal is given from a delay circuit 69 via a gate 7o, and a signal corresponding to the above-mentioned phase angle is provided. is added to the phase address signal. When phase modulation is not performed, no modulated wave signal is given, and the phase address signal corresponding to the above-mentioned phase angle passes through as is.

The output of the adder 68 corresponds to a phase address signal for reading out the waveform table 71, but in this embodiment, an address converter 72 is provided between the adder 68 and the waveform table 71.

The waveform table 71 stores waveform data of a predetermined waveform function, for example, a sine wave function, in a linear representation.

The address converter 72 divides the phase within one cycle into a plurality of sections, and converts the address value of the phase address signal for each section according to a function individually set for each section.

The waveform table 71 is
By accessing the waveform table 71, waveform data of a waveform function different from a predetermined waveform function stored in the waveform table 71, such as a sine wave function, is outputted from the waveform table 71 in response to the phase address signal. In this embodiment, as a different waveform function, a function that approximates the "sun" wave function is realized as an example.The details of this address conversion section 72 will be described later.

The output signal of the waveform table 71 is given to a multiplier 73,
It is multiplied by an envelope signal EV2 provided from an envelope generator 19 (FIG. 1).

As this envelope signal EV2, as will be described later, an envelope signal corresponding to a modulation index is given in the first half time slot, and an envelope signal corresponding to an amplitude coefficient is given in the second half time slot. The output of the multiplier 73 is sent to the delay circuit 69 as a clock pulse φL2.
(See FIG. 2), and is delayed by one period, that is, half the time of one channel time slot at the low-speed time division timing Lch, and is applied to the adder 68 via the gate 70. Further, the output of the multiplier 73 is provided to latch circuits 75 and 76 via an adder 74. Latch circuit 7
The output of 6 is given to an adder 74.

The latch circuit 75 is for holding the frequency modulation calculation result for one channel, and is for holding the frequency modulation calculation result for one channel.
A latch operation is performed at the end of the time slot of each channel in the channel.

A detailed example of the address translation section 72 is shown in FIG.

Address conversion section 72 includes an address conversion circuit 77 for performing an address conversion operation, and a selector 78 for selecting either a converted address signal or an unconverted phase address signal. The address conversion circuit 77 includes a phase interval determination circuit 79 that divides the phase within one cycle into a plurality of intervals and determines which phase interval the address value belongs to from the value of the input phase address signal, and The phase interval determination circuit 79 selects the address conversion function corresponding to the phase interval determined by the phase interval determination circuit 79, and converts the input phase address signal according to the selected address conversion function. It also includes an address conversion function calculation circuit 80 that performs calculations to convert address values.

An example of an address conversion function prepared in the address conversion function calculation circuit 80 is shown in FIG.

In this example, the phase range from 0 to π is divided into six phase intervals 0 to π
/8. π/8 to π/4. π/4~π/2゜π/2~3π
/4, 3π/4 to 7π/8.7π/8 to π, and the following address conversion function is used for each phase section. In FIG. 6 and below, the independent variable X is the phase value of the phase address signal input from the adder 68, and the dependent variable y is the phase value of the converted address signal output from the address conversion function calculation circuit 80. . In addition, the inequality represents a determination condition in the phase interval determination circuit 79.

■When 0≦x π/8, y=(1/2)x ■When π/8≦X<π/4, y=x-1/16 ■When π/4≦x = (5/4) x -1/8■π/2
≦x (when 3π/4, y = (5/4) x -1/ 8■3π/
When 4≦x<7π/8, y=x+1/16 ■When 7π/8≦x×π, y − (1/2) x + 1/2In addition, π
In the phase range of ~2π, six phase intervals π~π+π/8. π10π/8 to π+π/4. π+π/4
~π+π/2. π+π/2 to π+3π/4. π+3π/
It is divided into 4~π+7π/8°π+7π/8~2π, and the address conversion function exactly the same as above is used for each phase section.

Since each of the above address conversion functions is a linear function, the configuration of the address conversion function calculation circuit 80 can be extremely simplified. However, the address conversion function corresponding to each phase interval in the address conversion function calculation circuit 80 is not limited to a linear function, but may be a quadratic function or another type.

The selector 78 is controlled by a selection control signal given from the algorithm control unit 66, selects either the unconverted phase address signal or the address signal converted by the address conversion circuit 77, and selects the waveform table 71.
Enter. This allows waveform table 71 to be selectively accessed by either the untranslated phase address signal or the transformed address signal.

Assuming that the phase of the unconverted phase address signal is ωt, if a sine wave function is stored in the waveform table 71, when the waveform table 71 is accessed by the unconverted phase address signal, the sine wave function sinωt is obtained. (see Figure 7a). On the other hand, when the waveform table 71 is accessed by an address signal converted using the address conversion function as in the above example (that is, FIG. 6), a waveform function that approximates the number of wave intervals of sin"ωt" is obtained ( (See Figure 7).

In this way, by using the waveform table 71 that stores waveform data of a linear representation of a sine wave function, there are two types of waveform functions: a sine wave function (sinωt) as stored, and a waveform function that approximates a different 5in2 wave function (sin2ωt). waveform functions can be selectively generated.

As is well known, when the waveforms of the first half period and the second half period are symmetrical, such as a sine wave function.

It is not necessary to store the 1-period wave engraving portion in the waveform table 71, and it is sufficient to store only the 172-period waveform or the 1/4-period waveform in the waveform table 71.

In this case, control is performed to switch the reading direction of the waveform table 71 between positive and negative depending on the phase range, and to invert the positive and negative signs of the read waveform data, but this point will be explained as it is a well-known technology. and illustrations are omitted.

Of course, the address conversion function prepared by the address conversion function calculation circuit 80 has the above-mentioned sin" wave interval number (sin"ω
The present invention is not limited to one that can realize a waveform function that approximates t), but may also be one that can approximately realize other waveform functions.

Further, the address conversion function prepared by the address conversion function calculation circuit 80 is not limited to l[ that can approximately realize one type of waveform function, but can be a plurality of sets that can approximately realize multiple types of waveform functions. The configuration may be such that one set among them can be selected.

Further, the address conversion function calculation circuit 80 is not limited to a calculation circuit, but may also use a storage circuit such as a function table.

Further, the waveform function stored in the waveform table 71 is not limited to a sine wave function, but may be a cosine wave function or any other arbitrary waveform function. In this case, the characteristics of the address conversion function in the address conversion function calculation circuit 80 are determined in consideration of the waveforms stored in the waveform table 71 and the desired waveform function to be realized.

Of course, the method of dividing the phase intervals is not limited to the above-mentioned example, and may be done in any manner as required.

Next, an example of the calculation algorithm in the frequency modulation calculation section 65 that uses two time slots per channel will be described. There are at least the following eight possible calculation algorithms, and the algorithm control section 66 selects one algorithm according to the tone data TC, and sends various control signals and calculation parameters to the frequency modulation calculation section 65 to realize the algorithm. to each circuit within.

E(t) 5in(kcωt +Em(t) sin(
kmut)) = IE (t) 5in(kcωt +
Em(t) sin”(kmut))−2E(t
) 5in2(kcωt + Ex(t) 5in(k
+++ωt ))-3E (t) 5in2(kcu
t+Em(t)sin”(kmut))−4E
(t) 5in(kcωt)+Em(t) sin
(kmut) −5E (t) 5in(kcωt
)+Em(t) 5in2(k++ωt)−6E
(t) sin”(kcu t) 10Em(t) si
n(km t )−7E (t) sin”(kcω
t)+Em(t)sin2(kmut)=-8E
(t) is an envelope signal that sets the amplitude envelope, and Em(t) is an envelope signal that sets the modulation index, which is a function of one hour ahead and changes over time. These envelope signals E(t) and E+++(1) are
It is included in the envelope signal EV2 for the second musical tone signal generation circuit 14, and the envelope signal Eα(1) for modulation index is given in the first half of the time slot of one channel, and the envelope signal Eα(1) for setting the amplitude envelope is given in the second half. An envelope signal E (t) is given.

Generally, in the first half of the time slot of one channel, the process of generating the modulation wave function (the second
In the second half, a carrier function is generated and a modulation calculation is performed (the first term in the above equation, that is, the term multiplied by the coefficient E (t)) is performed. operation) is performed.

As an example, the calculation operation of the second equation will be explained. 1
In the first half of the time slot of the channel, the modulated wave frequency coefficient km is sent to the shift circuit 67, the control signal for selecting the converted address signal is sent to the address converter 72,
E@(t) is sent to the multiplier 73 as the envelope signal Ev2.
, respectively, and approximately Em(t) sin”(k
A modulated wave function signal having a characteristic (mc+>t) is outputted via the waveform table 71 and the multiplier 73. This modulated wave function signal is delayed by a delay circuit 69 and given to the gate 70 in the latter time slot.In the latter time slot, the carrier wave frequency coefficient k
c is applied to the shift circuit 67, a control signal for selecting the unconverted phase address signal is applied to the address converter 72, a control signal for enabling the gate 70 is applied to the gate 70, and the envelope signal EV2 is multiplied by E(t). They are each given to a container 73. As a result, the adder 68 adds the modulated wave function signal Em(t) s to the carrier phase angle data kcωt.
in'' (kmωt) is added and phase modulation is performed.

The resulting phase modulated phase address signal is
The signal passes through the address converter 72 without being converted and accesses the waveform table 71. The readout output signal of the waveform table 71 is multiplied by the amplitude envelope signal E(t) to obtain musical tone signal sample point amplitude data which is the result of the frequency modulation calculation shown in the second equation above.

This passes through adder 74 and is applied to latch circuit 75. A latch control pulse is applied to the latch circuit 75 at an appropriate timing at the end of the second half time slot, and the tone signal sample point amplitude data, which is the result of the frequency modulation calculation shown in the second equation above, is latched into the latch circuit 75.

The first to fourth equations are actually frequency modulation calculation equations, and the fifth to eighth equations are addition and synthesis equations for two waveform signals. When performing such an addition/synthesis formula, a latch control pulse is applied to the latch circuit 76 at an appropriate timing in the first half of the time slot of one channel.
The waveform sample data (Em(t)sin
kmω, etc.) is latched into the latch circuit 76. Then, in the second half of the time slot of channel 1, gate 7
0, that is, without performing phase modulation, the waveform sample point amplitude data (E
(t) 5 inkcω, etc.) and the waveform sample point amplitude data from the latch circuit 76 (E m(t) sinkmω
etc.) are added by an adder 74. This addition result is latched into the latch circuit 75 at an appropriate timing at the end of the second half time slot.

In addition, when performing the addition and combination formulas such as the above-mentioned formulas 5 to 8, the gate 70 may be enabled, that is, phase modulation may be performed in the latter half of the time slot of one channel, and in this case, The above formulas 1 to 4
A musical tone signal can be synthesized by further adding a modulated wave signal to a musical tone signal having a frequency modulation calculation formula such as the following expression.

The output of the latch circuit 75 is applied to an accumulator 81, and the accumulator 81 sums up the musical waveform sample point amplitude data of each channel for one sample point. The accumulator 81 includes an adder 82 that inputs the output signal of the latch circuit 75, a register 83 that delays the output signal of the adder 82 by one bit time according to the low-speed clock pulse φL, and inputs the output of this register 83 to the adder 82. and a latch circuit 85 for holding the output of the register 83. The gate 84 is controlled by a signal obtained by inverting a clock pulse φ (see FIG. 2), which is synchronized with the time slot of the first channel at the low-speed time division timing Lch, by an inverter 86. Furthermore, this clock pulse φ causes the latch circuit 8 to
The latch operation of No. 5 is controlled.

The musical waveform sample point amplitude data for one sample point of the first to eighth channels, which are sequentially given according to the low-speed time division timing Lch, are accumulated in sequence, and when the data of all channels have been accumulated, the clock pulse φ1 rises. , thereby latching the accumulated values of data of all channels into the latch circuit 85, and closing the gate 84 to clear the accumulated values in the register 83.

The output of the latch circuit 85 is output as the output of the second musical tone signal generation circuit 14. In this way, the sampling frequency fs of the output musical tone signal of the second musical tone signal generating circuit 14 becomes 50 kHz at the low speed time division timing Lch.

Note that special pitch synchronization processing is performed in this second musical tone signal generation circuit 14, and the pitch of its output musical tone signal and the sampling frequency fs are not synchronized.

(Digital addition and synthesis) Returning to FIG. 1, as mentioned above, in the adder 15, the first
The output musical tone signal of the musical tone signal generating circuit 13 and the output musical tone signal of the second musical tone signal generating circuit 14 are added and synthesized. Here, the sampling frequency fs of the output musical tone signal of the first musical tone signal generation circuit 13 is 400 kHz, and the sampling frequency f of the output musical tone signal of the second musical tone signal generation circuit 14 is 400 kHz.
s is 50 kHz, and both are integral multiples.

Therefore, since the sampling frequencies of both musical tone signals to be added are synchronized, it is possible to add both musical tone signals at harmonious timing without any problem.

(Envelope generator 19) An example of the envelope generator 19 is shown in FIG.

In FIG. 8, the envelope generator 19 generates a first envelope signal EVI for the musical tone signal generated by the first musical tone signal generating circuit 13 and a second envelope signal EVI for the musical tone signal generated by the second musical tone signal generating circuit 14.
A second envelope signal E for the musical tone signal generated in
Envelope generation circuit 9 that generates V2 by time division multiplexing
0 and the envelope signal EVI generated by time division multiplexing.
, Latch circuits 91, 9 for distributing EV2 separately.
It is equipped with 2°93.

The envelope generation circuit 90 generates a first envelope signal EV for eight channels for the first musical tone signal generation circuit 13.
t
) and E m(t)) are generated in a total of 24 channels in a time-division manner. The 24-channel time-division operation timing in envelope generation circuit 90 is established by clock pulse φL3 (see FIG. 2) having a frequency three times that of low-speed clock pulse φL. By this clock pulse φL, the low-speed time division timing Lch
A time division timing Ech (see FIG. 2) for forming an envelope is established by dividing the time slot of each channel into three.

The envelope generation circuit 90 generates three different envelope signals EVI in three time slots per channel based on the key-on signal KON of each channel given from the sound generation allocation circuit 12 according to the low-speed time division timing Lch.

E (t) + E n(t) are generated, respectively. The shape, level, etc. of each envelope signal EVI, E(t), and Em(t) are determined by the tone color data TC.

For example, among three time slots per channel, the first envelope signal Ev1 is generated in the first time slot, and En+(t) of the second envelope signal EV2 is generated in the second time slot. Then, in the third time slot, the second envelope signal E
E(,t) of V2 is generated. Note that these envelope signals EV 1 , Em(t), E(t)
It is assumed that the data representation of is a linear representation.

The output of the envelope generation circuit 90 is a latch circuit 91.9.
given to 2. The latch circuit 91 latches the first envelope signal EVI for each channel using a strobe pulse L1 (see FIG. 2) generated in synchronization with the first time slot of the three divided time slots. The latch circuit 92 generates two second envelope signals Em( t), E
Latch (t). The output of latch circuit 92 is input to latch circuit 93. The latch circuit 93 receives a clock pulse φL having twice the frequency of the low-speed clock pulse φL,
Strobe pulse L3 (second pulse) synchronized with (see Figure 2)
(see figure), and shapes the time-division time slots of the two envelope signals Em(t) and E(t) for each channel, which are output in a time-division manner from the latch circuit 92, into equal intervals.

In this way, the latch circuit 91 outputs the first envelope signal EVI for each channel in a time-division manner according to the low-speed time-division timing Lch. The output EVI of the latch circuit 91 is then applied to the multiplier 43 (FIG. 3) in the first musical tone signal generation circuit 13 after performing appropriate timing adjustment as necessary. Further, from the latch circuit 93, two envelope signals E m(t
).

E(t) is output in a time-division manner. The outputs E m (t) and E (t) of the latch circuit 93 are then sent to the multiplier 73 (FIG. 4) in the second musical tone signal generation circuit 14 after performing appropriate timing adjustment as necessary. It is given as a second envelope signal EV2.

Waveform table 71 in second musical tone signal generation circuit 14
It is also possible to store the waveform data in logarithmic representation. However, in this case, the envelope signal EV2 must also be given in logarithmic representation. In this case, the hardware of the envelope generator 19 cannot be shared by the first and second envelope signals EVI, EV2, and these envelope signals EVI, EV2 cannot be generated in a time-sharing manner. Therefore, the hardware of the envelope generator 19 becomes large-sized.

However, if the waveform data is stored in linear representation in the waveform table 71 in the second musical tone signal generation circuit 14, the envelope signal EV2 may also be in linear representation, and as in the above embodiment, the envelope generator 19 of the first and second envelope signals EVI, E
These envelope signals EVI can be shared by V2.

EV2 can be generated in a time-division manner.

Therefore, the hardware of the envelope generator 19 can be downsized.

Further, even if the waveform data is stored in linear representation in the waveform table 71 in the second musical tone signal generation circuit 14, if the address conversion section 72 as shown in the above embodiment is provided, , a waveform function different from the waveform function stored in the waveform table 71 can be easily obtained with a simple configuration.

Note that the configuration of the envelope generator 19 is not limited to that shown in FIG. 8, and any other configuration may be adopted. For example, the first and second envelope signals EV1.
EV2 may be generated in parallel by separate hardware. Further, when the waveform table 71 in the second musical tone signal generation circuit 14 stores waveform data in logarithmic representation, the envelope signal EV2 may also be generated as data in logarithmic representation.

(Example of modification) The sound source system or musical sound signal generation system in the first and second musical tone signal generation circuits 13 and 14 is not limited to the above-mentioned one, and may be of any type. For example, the waveform stored in the waveform memory of the first musical tone signal generation circuit 13 is not limited to the entire waveform from the start of the sound to the end of sound generation, but may also be the waveform of a part of the start and sustain part of the sound. . Furthermore, the encoding format of data stored in the waveform memory is not limited to PCM (pulse code modulation) format, but also DPCM (differential PCM), A
DPCM (Adaptive Differential PCM), DM (Delta Modulation)
, ADM (adaptive delta modulation), etc., as appropriate. Further, the frequency modulation calculation algorithm in the second musical tone signal generation circuit 14 is not limited to the one shown in the above embodiment, and any algorithm may be used. Furthermore, the modulation calculation for musical tone synthesis in the second musical tone signal generation circuit 14 is as follows:
In addition to the frequency modulation calculation, any appropriate modulation calculation such as an amplitude modulation calculation or an amplitude modulation calculation using a time window function may be used.

Further, as the second musical tone signal generation circuit 14, a musical tone synthesis method other than the modulation calculation type may be used.

In addition, the number of sound generation channels and sampling frequency fs in the first and second musical tone signal generation circuits 13 and 14, f
Of course, the numerical values such as s2 are not limited to the numerical values shown in the above embodiment. Furthermore, each musical tone signal generation circuit 13, 14 may be of a single tone generation type.

Further, when the first and second musical tone signal generating circuits 13 and 14 simultaneously generate musical tone signals of a common pitch to obtain a duet effect, the timings at which the sound generation of the picture frame tone signals start need not be exactly the same; There may be an appropriate delay, and the sound generation delay time may be variably controlled.

Alternatively, the outputs of the first and second musical tone signal generating circuits 13 and 14 may not be digitally added, but may be generated through separate sound systems.

Further, the first musical tone signal generating circuit 13 may not be provided, and only the modulation calculation type musical tone signal generating circuit 14 may be provided.

〔Effect of the invention〕

As described above, according to the present invention, in the modulation calculation type musical tone signal synthesis device, the phase within one period is divided into a plurality of sections, and the address value of the phase address signal is determined according to a function individually set for each section. Since the waveform table is accessed using the converted address signal after each interval is converted, the modulating wave function or modulated wave function in the modulation calculation for musical tone synthesis can be compared with the waveform function originally stored in the waveform table. can be easily converted into a different complex one, and this has the excellent effect of making it possible to perform high-quality modulation calculations for musical tone synthesis that can control many frequency components with a relatively simple configuration. play.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing the overall configuration of an embodiment of an electronic musical instrument to which the present invention is applied; FIG. 2 is a timing chart showing an example of various clock pulses and various operation timings in the embodiment; FIG. 3 4 is a block diagram showing a detailed example of the first musical tone signal generation circuit in the same embodiment, FIG. 4 is a block diagram showing a detailed example of the second musical tone signal generation circuit (modulation calculation type) in the same embodiment, and FIG. The figure is a block diagram showing an example of the address translation section in FIG. 4, FIG. 6 is a graph showing an example of the characteristics of the address translation function in the same address translation section, and FIGS. 7(a) and (b) are the blocks in FIG. This shows an example of the waveform output from the waveform table. (a) is a waveform diagram when the address is not converted by the address converter, and (b) is a waveform diagram when the address is converted. Figure 8 is the waveform diagram shown in Figure 1. FIG. 2 is a block diagram showing an example of an envelope generator in FIG. 10...Keyboard, 11...Key press detection circuit, 12...
Sound generation assignment circuit, 13... first musical tone signal generation circuit,
14... Second musical tone signal generation circuit, 15... Adder, 16... Digital/analog converter, 19...
Envelope generator, 61... Phase address accumulator, 65... Frequency modulation calculation section, 71... Waveform table, 72... Address conversion section, 78... Selector, 79... Phase interval determination circuit , 80...Address conversion function calculation circuit, patent applicant Yamaha Corporation

Claims (5)

[Claims] (1) A musical tone signal synthesizer that synthesizes a musical tone signal based on a predetermined modulation calculation using a modulated wave signal and a modulated wave signal, which includes a waveform table storing waveform data of a predetermined waveform function in a linear representation, and a modulated wave. a phase address signal supply means for supplying a phase address signal for a signal or a modulated wave signal; address converting means for converting address values for each interval, and by accessing the waveform table using the output of the address converting means, waveform data of a waveform function different from the predetermined waveform function can be converted to the phase address. A musical tone signal synthesis device configured to output from the waveform table in response to a signal. (2) The address conversion means converts the address value of the phase address signal by using the phase address signal as an independent variable and calculating a function individually set for each section. 1. The musical tone signal synthesis device according to 1. (3) The musical tone signal synthesis device according to claim 2, wherein the functions individually set for each section are each composed of a linear function. (4) The musical tone signal synthesis apparatus according to claim 1, further comprising means for selecting which of the address signal converted by the address conversion means and the unconverted phase address signal should be used to access the waveform table. (5) The musical tone signal synthesis device according to claim 1, wherein the waveform table stores waveform data of a sine wave function.