JPS58197851A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to avoid the sppearance of stepwise differences on the surface of an insulation film by a method wherein a metallic film is formed selectively on a polycrystalline Si film only, with the film as a core, inside a wiring pattern groove formed in the insulator on a substrate. CONSTITUTION:An insulation film 2 is etched with a resist 4 as a mask, and thus the wiring pattern groove 7 is formed. After complete removal of the resist 4, the polycrystalline Si film 8 containing an impurity such as phosphorus is formed over the entire surface, and further resist or polyimide resin 9 is coated over the entire surface. Besides, etching is performed over the entire surface under the condition that the etching speed for the resist or polyimide resin 9 becomes approximately equal to the etching speed for the polycrystalline Si film 8, and then the etching is stopped at the point that the etching is finished at the region except for the wiring pattern groove 7. The resist or polyimide resin 9a in the wiring pattern groove 7 is removed. Finally, with the polycrystalline Si film 8a remaining in the wiring pattern groove 7 as the core, the metallic film 3 is formed selectively on said polycrystalline Si film 8a by a CVD method due to hydrogen reduction of a metal hallide.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a multilayer metal arrangement 1tl with high yield and reliability.

A conventional method for forming an entire island multi-level interconnection, for example, a method for forming a two-layer interconnection, is shown in FIG. In the figure, 1 is the substrate, 2 is the insulating film, 3 is the metal film, 3 is the 1st metal wire,
4a is a partial resist serving as a mask from a resist 4 (not shown), 5 is a metal interlayer insulating film, and 6 is a second layer metal film serving as a 21st gold maple wiring.

Below, the conventional method for forming metal multilayer wiring is explained along with drawings.
Illustrate.

First, the gold R film 3 is formed on the entire surface of the insulation @2 formed on the substrate 1. Next, a resist 4 (not shown) is applied onto the metal film 3, a wiring pattern is patterned, and a portion 4a of the resist 4 that will become a mask is formed as shown in FIG.
Leave as shown.

Next, the 1-gold 14 film 3 is etched by masking off the partial resist 4a, and the partial resist 41 is removed to form an IF#II metal pattern 93m as shown in FIG. At this time, #I11th metal wiring 3& forms a step corresponding to its film thickness.

Furthermore, a PSG film and a 5i
(The metal interlayer insulating film 5 is formed using 5isN411 or the like in the h film. As a result, the wrinkled metal interlayer insulation [[What is the step that appears in 5 is the step of the underlying first layer metal wiring 3a?
'! 'It will become stronger or even bigger.

Then, a metal film 6 serving as a 2N1 metal wiring is formed on the metal interlayer insulation lI5, and a 2If11 metal wiring 6m (not shown) is formed by pattern nipping and etching.

In the conventional method as described above, the metal layer is completely destroyed! 2N1 (not shown) formed on the step @ surface due to the step 5
Memetal arrangement II! There was a phenomenon that the I [thickness of 6a became thinner, and the yield and reliability of the #2 NII metal pattern of 96 m decreased.

An object of the present invention is to eliminate these drawbacks by embedding metal wiring in an insulating film so that the surface pressure difference in the insulating film does not appear, and will be described in detail below.

FIG. 2 shows one embodiment of the present invention.
The same reference numerals as those in the figures indicate the same or corresponding parts, and detailed explanation thereof will be omitted.

In the figure, 7 is a wiring groove formed by etching the insulating film 2, 8 is a polycrystalline silicon film containing impurities such as phosphorus formed on the insulating film 2, and 9 is the polycrystalline silicon film. It is a resost or polyimide resin formed on the film 8.

Next, one embodiment of the present invention will be described with reference to the drawings.

First, a lennost film 4 is placed on an insulating film 2 formed on a substrate 1.
to form a wiring/4' turn. That is, Fig. 2 (a
) As shown in K, the resist 4 is removed only from the area where wiring is to be formed. Firstly,
The insulating film 2 is etched using the resist 4 as a mask to form a wiring pattern #I7 as shown in FIG. 2(b).

After the resist 4 is completely removed, as shown in FIG. 2(e), polycrystalline silicon @ 8 containing impurities such as phosphorus is formed on the entire surface, and then a resist or polyimide resin 9 is formed.
Apply to the entire surface. As a result, the surface of the resist or deli-ion resin 90 becomes flat.

Further, the entire surface is etched using a glazing etching method or an ion etching method under which the etching speed of the resist or polyimide resin 9 and the etching speed of the polycrystalline silicon film 8 are equal to #1. The resist or #'iI lead resin 9 and polycrystalline silicon [
Etching is stopped when etching 118 is completed. As a result, as shown in FIG. 2(d), the resist or the I-lead resin 9a and the polycrystalline silicon film 8& are still left inside the wiring pattern #I7. The resist or polyimide resin 9a inside is removed. Next K.

Polycrystalline silicon film 8a remaining in the wiring/zeturn groove 7
CV based on the origin of water of gold nuggets and logs with as the core
A metal film 3 is selectively formed on #polycrystalline silicon I [8m] using method D, and the wiring pattern 7'&- is buried as shown in FIG. 2(e), and this is used as a metal wiring. Form.

Next, a metal interlayer insulating film 5 as shown in FIG. 2(f) is formed on this gold maple pattern Ik3.

Then, on the metal interlayer insulating film 5, a gold II4 film 6, which will become a second layer of metal wiring, is formed. The metal interlayer insulating film 5
Since the surface of the metal film 6 is flat, the thickness of the metal film 6 is constant. As a result, the film thickness of the second layer metal wiring 6& (not shown) formed by pattern nipping and etching becomes constant.As described above, the present invention aA has the following traps. It becomes possible to embed it in the insulating film, and as a result, it is possible to eliminate the step difference on the surface of the conventional gold lI4 film and reduce the film thickness to just one inch, making it possible to form highly reliable metal wiring at a high yield. It has a great effect.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional explanatory diagram of a semiconductor device showing a conventional method for forming multilayer metal wiring, and FIG. 2 is a cross-sectional diagram showing an embodiment of the present invention.
It is a figure equivalent figure. 1... Substrate, 2... Insulating film, 3.6... Metal film,
4...Resist, 5...Gold 14 interlayer insulating film, 7...
・Wiring pattern groove, 8.8m...polycrystalline silicon film,
9.9m...Resist or? Liimide resin. Figure 1 Figure 2 Figure 2

Claims (1)

[Claims] (In a method for manufacturing a semiconductor device in which an 11-karat gold maple multilayer wiring is formed, a step of performing mother turning (by punching/turning in order to form a metal pattern with a resist on an insulating film formed on a substrate); a step of etching the wiring nonaturn to form a wiring/9-turn pattern in the insulating film, and after removing the resist, forming a thin polycrystalline silicon film;
a step of forming a resist film, a step of coating the entire surface with resist or polyimide resin, and a step of applying the resist or Fi/lid resin and the polycrystalline silicon film inside the wiring 14 terminal #IO. a process of dry etching and etching at the same time so that only 1/f turn grooves remain; a process of removing the resist or -resist resin remaining inside the 1/f turn grooves; 1. A method of manufacturing a semiconductor device, comprising the step of using a polycrystalline silicon film as a core and selectively forming a metal film only on the film.