JPS58176974A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a MOS semiconductor element having stabilized gate dielectric strength by forming two-level or three-level silicon gate electrodes with different deposition methods. CONSTITUTION:A gate insulating film 2 consisting of a SiO2 film on a field insulating film 4 deposited over a semiconductor substrate 1, a polycrystalline silicon film 5 is deposited thereon by the vacuum deposition method, and moreover a polycrystalline silicon film is deposited thereon by the CVD method. Thereafter, such film is patterned by the photo processing and a gate electrode and gate insulating film 2 consisting of two-level polycrystalline silicon films 5, 6 are formed by the dry etching method. In succession, source and drain are formed by well known method and a MOS semiconductor element can be obtained. When such two-level polycrystalline silicon film is formed, since a polycrystalline silicon film 5 formed as the under layer is deposited, a gate dielectric strength is not deteriorated, and since the uppermost polycrystalline silicon film 6 is deposited by the CVD method, invasion of chemical solution is rejected through a dense film and thereby a gate insulating film can be kept stable.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technique of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a modification of a method for forming a silicon gate electrode of an MIS type semiconductor element.

(To) Conventional technology and problems Most of the memory circuits and logic circuits of IC, LSI, TO or VLSI are MIS type (old-time experts call it MO8JI)
Figure 1 shows the basic structure of such a MO8 type element.As is known, a gate insulator is provided on a semiconductor substrate 1. A gate electrode 8 is provided through the film 2, but as the device itself has become more dense and smaller, the gate insulating film has become thinner, on the order of several 100λ, and the gate electrode has become similarly thin. However, there are various problems caused by this in terms of quality.

Among these, the problem of gate dielectric breakdown voltage deterioration has been well studied from the beginning, and it is also known that, for example, a 1 μm gate electrode has a higher gate breakdown voltage than a silicon gate electrode. However, in order to achieve high integration such as LSI, if a gate cell fin process is used, the gate electrode must have heat resistance, and a multilayer wiring structure is required, so soft aluminum is used. It is a noisy sound, and 'recon game) tll is often used.

The present invention relates to a method for depositing the y recongate electrode Ii,
Polycrystalline silicon is usually formed by vapor deposition, sputtering, or chemical vapor deposition (CVD), but each of these methods has both advantages and disadvantages. That is, CVD
Semiconductor device F with a silicon gate electrode deposited by a method
The breakdown voltage deteriorates significantly and is inferior to other gate electrodes formed by vapor deposition or sputtering. On the other hand, a film made of polycrystalline silicon deposited by vapor deposition is amorphous, close to an amorphous state, and porous. Therefore, during the manufacturing process, the hydrofluoric acid bath and other substances seep into the gate electrode, corrode the gate insulating film made of silicon dioxide (Sj-0,) directly below, and cause breakdown voltage degradation as well. The slave VHIW voltage vth is varied. Further, the sputtering method forms a film quality similar to that of the vapor deposition method.

(C) Object of the Invention The present invention solves these problems and proposes a method of manufacturing a MOS type semiconductor device that can stabilize the gate dielectric breakdown voltage.

(1) Structure of the Invention The object is to form a polycrystalline silicon film on a gate insulating film by vapor deposition or sputtering, and then deposit a polycrystalline silicon film thereon by CVD. This can be achieved by a method of manufacturing a gate electrode as well.

(f13) Embodiments of the Invention Figures 2 through 4 are cross-sectional views of the process steps of an example by Akira Honmoto. First, as shown in FIG. 2, after a field insulating film 4 is formed on a semiconductor substrate t2ii-m selection layer 17, a gate insulating film 2 made of a 700 Å thick film is formed.

Next, as shown in FIG. 3, a polycrystalline silicon film 5 with a thickness of 2000 Å is deposited on the upper surface by a vapor deposition method, and a polycrystalline silicon film 6 with a thickness of 2000 Å is further deposited on top of this by a CVD method. . These polycrystalline silicon films are, for example, conductive films doped with phosphorus or the like, and polycrystalline silicon containing phosphorus is first deposited in a vacuum deposition apparatus. Subsequently, it is placed in a CVD apparatus, and its surface is first slightly etched and cleaned, and then monosiphne (SiH4) containing phosphine is introduced, decomposed, and deposited.

Next, as shown in FIG. 4, a pattern is formed using a photo process to form a gate electrode and gate insulating film 2 made of two layers of polycrystalline V silicon 1115.6. This method uses a resist film mask (not shown) and performs dry etching using a mixed gas of carbon tetrafluoride (Freon) and oxygen.

Thereafter, the source and drain are formed by a known manufacturing method,
A MOS type semiconductor device is finished, but if such a two-layer polycrystalline silicon film is used, the lower layer polycrystalline silicon film 5 will be vapor-deposited and the rounded gate breakdown voltage will not deteriorate, and the upper layer polycrystalline silicon film 5 will not deteriorate. Since the crystalline silicon film 6 is deposited by the CVD method and is a dense film, it prevents penetration of chemicals** and keeps the gate insulating film stable during manufacturing. In addition, the vapor-phase grown nine-doped polycrystalline V silicon film (similarly to a doped vapor deposited film) has the effect of rounding, which has a high mobility of electrons and holes, and improves electrical conductivity.

In addition, FIG. 6 is a process diagram of another example, and shows a process diagram corresponding to FIG. 8 of the above example. and then (4
After forming the polycrystalline silicon film 6 by the D method, a polycrystalline V silicon film 7 is further formed thereon by the vapor deposition method. The dirt electrodes laminated in three layers in this manner also provide the above advantages.

Incidentally, in the above example, even if the polycrystalline silicon film is deposited by sputtering instead of the vapor deposition method, the same effect as the vapor deposition method can be obtained.

(B) Effects of the Invention As is clear from the above embodiments, the present invention improves gate dielectric breakdown voltage and achieves stable vth by using a method of laminating silicon gate electrodes in two or three layers using different deposition methods. It is a tool that significantly contributes to improving the quality of semiconductor devices.

[Brief explanation of the drawing]

Fig. 1 is a basic structural diagram of a MOS type semiconductor device, Figs. 2 to 4 are sequential cross-sectional views of an oil manufacturing process according to an embodiment of the present invention, and Fig. 5 is an intermediate step diagram of another embodiment. It is. In the figure,
1 is a semiconductor substrate, 2 is a gate insulating film, S is a gate electrode,
4 is a field insulating film. 5.1 shows a polycrystalline Y-recon film made by vapor deposition, and 6 shows a polycrystalline V9-recon film made by CVD. Figure 1 Figure 2

Claims (1)

[Claims] After forming the gate insulating film of the MIS type semiconductor device, a polycrystalline silicon film is formed on its surface by vapor deposition or sputtering, and then a polycrystalline silicon film is deposited on top of it by chemical vapor deposition. A method for manufacturing a semiconductor device, comprising the steps of forming a gate electrode.