JPH05243397A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] Regarding the method of forming a connection structure of a multi-layer wiring for connecting a plurality of conductive layers formed on an Si substrate through an oxide film and the Si substrate, to improve the reliability of a gate insulating film. Secure and guarantee the reliability of the device. [Structure] After forming a first oxide film (gate oxide film) 14 on a Si substrate 11, only a portion where a connection portion of a multilayer wiring is to be formed is made thicker than other portions. First poly-Si layer 1
5, the silicide layer 16, the second poly-Si layer 18, and the third poly-Si layer 20 are laminated with the second oxide film 17, the third oxide film 19, and the fourth oxide film 21 interposed therebetween. An opening 2 is formed by anisotropically etching the laminated conductive layer and insulating film using the first oxide film 14 as a stopper at the portion where the connection portion of the multilayer wiring is to be formed.
3 is formed. Fifth covering the side surface and the bottom of the opening 23
A poly-Si layer 24 is deposited and a predetermined number of conductive layers exposed on the side surfaces of the opening 23 and the Si substrate 11 exposed on the bottom of the opening 23 are connected to each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a connection structure of multi-layer wiring.

[0002]

2. Description of the Related Art Static type semiconductor memory devices (SR
AM) has a transistor connected in a flip-flop type, so that a MOS type driving transistor formed on a substrate and a TFT type transmitting transistor formed in an insulating film on the substrate are connected to each other. Need to do.
A conventional method for performing this interconnection will be described in the order of steps with reference to FIGS.

[Step 1, FIG. 6] L on the silicon substrate 31
A field oxide film 32 is formed by the OCOS method to partition the element formation region.

A gate oxide film 33 used for a MOS type driving transistor is formed in the element formation region. [Step 2, FIG. 7] The gate oxide film 33 is patterned into a predetermined shape to form a contact hole 34.

A first polysilicon layer 35 and a silicide layer 36 are deposited on the entire surface by a CVD method and then patterned to form a polycide gate electrode and a word line of MOSFET.

[Step 3, FIG. 8] A first oxide film 37 is deposited on the entire surface by the CVD method. A second polysilicon layer 38 is deposited on the entire surface by the CVD method and then patterned to form a lower gate electrode of the TFT.

A second oxide film 39 is deposited on the entire surface by the CVD method. A third polysilicon layer 40 is deposited on the entire surface by the CVD method and then patterned to form a TFT operation region and a power supply line.

A third oxide film 41 is deposited on the entire surface by the CVD method. A fourth polysilicon layer 42 is deposited on the entire surface by the CVD method and then patterned to form an upper gate electrode of the TFT.

[Step 4, FIG. 9] The fourth polysilicon layer 42, the third oxide film 41, and the third oxide layer 41, which are to form the interconnections.
The opening 43 is formed by removing the polysilicon layer 40, the second oxide film 39, the second polysilicon layer 38, and the first oxide film 37 by anisotropic etching.

The fourth polysilicon layer 42, the third polysilicon layer 40, and the second polysilicon layer 38 are exposed on the side walls of the opening 43, and the silicide layer 36 is exposed on the bottom.

[Step 5, FIG. 9, FIG. 10] A fifth polysilicon layer 5 is deposited by a CVD method so as to cover the side wall and the bottom of the opening 43, and the fourth poly layer exposed on the side wall of the opening 43 is deposited. The silicon layer 42, the third polysilicon layer 40, and the second polysilicon layer 38 are connected to the silicide layer 36 exposed at the bottom.

Through the above steps, the conventional multi-layer wiring connection structure is completed.

[0013]

When connecting a plurality of conductive layers formed on a silicon substrate 31 via an oxide film to the silicon substrate, conventionally, the gate oxide film 33 is patterned to form a contact hole 34. And the silicon substrate 31 and the first polysilicon layer 35 were directly contacted with each other.

As a result, there is a problem that the gate oxide film 33 undergoes a lithography process and an etching process as it is exposed and is contaminated. Also, the first
Since the pretreatment with hydrofluoric acid for removing the natural oxide film is performed before depositing the polysilicon layer 35, there is a problem that the gate oxide film 33 is deteriorated and reliability is lowered.

As described above, according to the conventional method, the deterioration of the gate oxide film cannot be avoided, and the reliability of the device is ensured when the gate oxide film becomes thinner and thinner due to the progress of higher integration of semiconductor devices. Can not.

It is an object of the present invention to solve the above problems and provide a method of manufacturing a semiconductor device capable of ensuring the reliability of a gate insulating film, and in particular, a method of forming a connection structure of multilayer wiring. To do.

[0017]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a plurality of conductive layers formed on a semiconductor substrate via an insulating film, and the semiconductor substrate. A method of forming a multi-layer wiring connection structure for connecting a multi-layer wiring structure to a semiconductor substrate, the method comprising: forming a first insulating film on a semiconductor substrate; A step of making the conductive layer thicker than other portions, a step of laminating a predetermined number of conductive layers having a predetermined shape with an insulating film interposed therebetween, and a step of forming a first insulating film on a portion where a connection portion of multilayer wiring is to be formed Using the stopper as a stopper, a step of anisotropically etching a conductive layer and an insulating film laminated in a predetermined number to form an opening, a step of removing the first insulating film remaining at the bottom of the opening, and an opening A conductive layer covering the side and bottom of the opening is deposited and exposed on the side of the opening. Constituting the semiconductor substrate exposed in the bottom portion of the predetermined number of the conductive layer and the opening so as to include a step of connecting each other.

[0018]

According to the present invention, after the first insulating film (gate insulating film) is formed on the semiconductor substrate, only the portion of the first insulating film where the connection portion of the multi-layer wiring is to be formed is the other portion. It is formed thicker than the other. The thickly formed first insulating film functions as a stopper when forming the opening.

Further, according to the present invention, a conductive layer having a predetermined shape is laminated on a semiconductor substrate through an insulating film by a predetermined number, and then a conductive layer is laminated on a portion where a connecting portion of the multilayer wiring is to be formed. The insulating film is anisotropically etched to form an opening (contact hole).

As described above, according to the present invention, unlike the conventional example, since the opening (contact hole) is not formed while the first insulating film (gate insulating film) is exposed,
The first insulating film (gate insulating film) is not contaminated.
Therefore, the reliability of the first insulating film (gate insulating film) does not deteriorate.

As a result, the degree of integration of semiconductor devices has advanced,
Even when the gate oxide film becomes thinner, the reliability of the device can be guaranteed.

[0022]

EXAMPLE An example of the present invention will be described in the order of steps with reference to FIGS. [Step 1, FIG. 1] A field oxide film 12 is formed on a silicon substrate 11 by a LOCOS method to define an element formation region.

A gate oxide film 13 used for a MOS type driving transistor is formed in the element formation region. [Step 2, FIG. 2] Gate oxide film 1 of the portion where the interconnection is to be formed by covering the portion where the interconnection is to be formed with a mask
3 is re-oxidized to form a thick first oxide film 14.

[Step 3, FIG. 3] A first polysilicon layer 15 and a silicide layer 16 such as WSi are deposited on the entire surface by a CVD method and then patterned to form a polycide gate electrode and a word line of MOSFET.

A second oxide film 17 is deposited on the entire surface by the CVD method. A second polysilicon layer 18 is deposited on the entire surface by the CVD method and then patterned to form a lower gate electrode of the TFT.

A third oxide film 19 is deposited on the entire surface by the CVD method. A third polysilicon layer 20 is deposited on the entire surface by the CVD method and then patterned to form a TFT operation region and a power supply line.

A fourth oxide film 21 is deposited on the entire surface by the CVD method. A fourth polysilicon layer 22 is deposited on the entire surface by the CVD method and then patterned to form an upper gate electrode of the TFT.

[Step 4, FIG. 4] The fourth polysilicon layer 22, the fourth oxide film 21, and the third portion of the portion where the interconnections are to be formed.
The opening 23 is formed by removing the polysilicon layer 20, the third oxide film 19, the second polysilicon layer 18, the second oxide film 17, the silicide layer 16 and the first polysilicon layer 15 by anisotropic etching. To do. At this time, the thickly formed first oxide film 14 is used as an etching stopper.

On the side wall of the opening 23, the fourth polysilicon layer 22, the third polysilicon layer 20, the second polysilicon layer 18, the silicide layer 16 and the first polysilicon layer 1 are formed.
The polycide layer 5 and 5 are exposed, and the silicon substrate 11 is exposed at the bottom.

[Step 5, FIG. 5] A fifth polysilicon layer 24 is deposited by a CVD method so as to cover the side wall and the bottom of the opening 23, and the fourth polysilicon layer 22 exposed on the side wall of the opening 23. , The third polysilicon layer 20, the second polysilicon layer 18, and the polycide layer composed of the silicide layer 16 and the first polysilicon layer 15, and the silicon substrate 11 exposed at the bottom are connected to each other.

Through the above steps, the multilayer wiring connection structure according to the present invention is completed.

[0032]

According to the present invention, the opening (contact hole) is left as it is while the first insulating film (gate insulating film) is exposed.
Therefore, the first insulating film (gate insulating film) is not contaminated. Therefore, the first insulating film (gate insulating film) is not deteriorated and the reliability is not lowered.

As a result, the degree of integration of semiconductor devices has increased,
Even when the gate oxide film becomes thinner, the reliability of the device can be guaranteed.

[Brief description of drawings]

FIG. 1 is a diagram showing a process 1 of an example of the present invention.

FIG. 2 is a diagram showing a process 2 of one example of the present invention.

FIG. 3 is a diagram showing a process 3 of one embodiment of the present invention.

FIG. 4 is a diagram showing a process 4 of an example of the present invention.

FIG. 5 is a diagram showing step 5 of an example of the present invention.

FIG. 6 is a diagram showing a process 1 of a conventional example.

FIG. 7 is a diagram showing step 2 of the conventional example.

FIG. 8 is a diagram showing step 3 of the conventional example.

FIG. 9 is a diagram showing step 4 of the conventional example.

FIG. 10 is a diagram showing step 5 of the conventional example.

[Explanation of reference numerals] 11 silicon substrate 12 field oxide film 13 gate oxide film 14 first oxide film 15 first polysilicon layer 16 silicide layer 17 second oxide film 18 second polysilicon layer 19 third oxide film 20 third poly Silicon layer 21 Fourth oxide film 22 Fourth polysilicon layer 23 Opening 24 Fifth polysilicon layer

Claims (1)

[Claims] 1. A method of forming a connection structure of multilayer wiring for connecting a plurality of conductive layers formed on a semiconductor substrate via an insulating film to the semiconductor substrate, the method comprising: After forming the insulating film, a step of thickening only a portion of the first insulating film where the connection portion of the multilayer wiring is to be formed as compared with other portions, and a conductive layer having a predetermined shape is formed through the insulating film. And the opening is formed by anisotropically etching a predetermined number of conductive layers and insulating films using the first insulating film as a stopper at the portion where the connection part of the multilayer wiring is to be formed. Forming a layer, removing the first insulating film remaining on the bottom of the opening, depositing a conductive layer covering the side and bottom of the opening, and depositing a predetermined number of conductive layers exposed on the side of the opening. Connecting the layer and the semiconductor substrate exposed at the bottom of the opening to each other The method of manufacturing a semiconductor device, which comprises a.