JPS5817677A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5817677A JPS5817677A JP11601181A JP11601181A JPS5817677A JP S5817677 A JPS5817677 A JP S5817677A JP 11601181 A JP11601181 A JP 11601181A JP 11601181 A JP11601181 A JP 11601181A JP S5817677 A JPS5817677 A JP S5817677A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- film
- semiconductor device
- silicon nitride
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Non-Volatile Memory (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本弗明ｉｊ、ＭＭＯ８不揮発メモリの製造方法に関する
。従来ＭＭＯ８；ｇ子の製造に関しては、シリコン酸化
膜を５０〜１００ム形底し、その上にシリコン窒化膜を
５００五程度形底し、このシリコン酸化膜とシリコン窒
化膜の界面捕獲単位に電荷をシラツブし、これＫよりし
きいｍｗ圧をシフトさせデータを配録する不揮発メモリ
ーとしている。ところが、Ｗ際のシリコン窒化膜には、
多く１準位が、膜内に広く分布するため、シリコン酸化
膜を奈ンネル効果で通過した、電荷（主に電子）は、シ
リコン酸化膜−シリコン窒化膜界面だけでなくこのシリ
コン窒化膜内の単位に多くトラップされる。このことＦ
ｉ、消、告時、つまりゲート電極とシリコン基板層間に
１電圧を印加して亀、ゲート電極近傍にトラップされて
いる電子は、基板へ逃げＫ＜＜なり、結果的に、消去特
性の悪い不揮発メモリーとなり１問題となっている。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing an MMO8 nonvolatile memory. Conventional MMO8: Regarding the production of g-conductors, a silicon oxide film is formed in a 50 to 100 mm shape, a silicon nitride film is formed on top of it in a 500 to 500 mm shape, and a charge is generated in the unit of capture at the interface between the silicon oxide film and the silicon nitride film. This is used as a non-volatile memory in which data is stored by shifting the threshold mw pressure from K. However, in the silicon nitride film next to W,
Since many 1 levels are widely distributed within the film, the charges (mainly electrons) that have passed through the silicon oxide film due to the Nannell effect are not only at the silicon oxide film-silicon nitride film interface but also within the silicon nitride film. Many units are trapped. This thing F
At the time of erasure, that is, when a single voltage is applied between the gate electrode and the silicon substrate layer, the electrons trapped near the gate electrode escape to the substrate, resulting in poor erasure characteristics. This becomes a non-volatile memory, which poses a problem.
従来これらの欠点を、除く方法として、シリコン酸化膜
−シリコン窒化膜界面に、金属層とか。Conventionally, as a method to eliminate these drawbacks, a metal layer was formed at the silicon oxide film-silicon nitride film interface.
金属酸化物層を非常に薄くコーティングすることが試み
られて−るが、可動イオン等の混入がさ社られず、ゲー
ト電極へのリークが生じ易（なシ。Attempts have been made to coat the metal oxide layer very thinly, but this does not prevent the incorporation of mobile ions, which tends to cause leakage to the gate electrode.
信頼性に欠けるものであった。It lacked reliability.
そこで１本発明はｈｙネル効果によシ、侵入ししてきた
電荷を、効率工（シリコン酸化贋−シリコン窒化膜界面
に、捕獲し、しかも従来の方法に与られる。ゲート電極
へのリークなどの々いＭＷＯＳ不揮発メモリの製造方法
を提供するものである。Therefore, the present invention efficiently captures the invading charges by the HYNEL effect (at the silicon oxide/silicon nitride film interface), and also prevents them from leaking to the gate electrode, etc. The present invention provides a method for manufacturing a MWOS nonvolatile memory.
＆に、本発明の製造方法を、ＰチャネルＷＨＯ８！！子
を一例に、１〜１図に詳述する。夏型基板１０１にＰＨ
不純物としてボロンをト°−プしてソース・トレイ７１
０２を形厘し、シリコン酸化ＩＩ ＩＯ３をゲージ部の
み薄く形放した後、多結晶シリコｙ１０４を堆積するｈ
Ｃｗｔ１図（ａ） ）次にこの多結晶シリコン１０４を
、アルモニ了ｗｓ気で熱窒化し、シリコン窒化１［１０
５とする・この時、ｌＩ誘電率上るために、多結晶シリ
コン１０４に、！’、ボＭＶ等の不純物をドープすると
とも考えられる。又、この窒化に関して多結晶シ讐：１
：／１０４を１Ｏ−Ｚｏｏム程度一部残存させることも
一例として考えられる。（！１図（＆） ）最後に、ゲ
ージ電極としてアルミニウム１０６管形家してＭ］１０
ｇ素子は充放する。（第１図Ｃ６１）
以上の工うＫして作られた本発明のＭＮＯ８ＩＩＩ子の
特長を挙げると、
【１１ 熱窒化によるシリコン窒化膜であるので１火
陥、ピンホール等が少な匹。&, the manufacturing method of the present invention was applied to P-channel WHO8! ! This will be explained in detail in Figures 1 to 1, taking a child as an example. PH on summer type board 101
Source tray 71 is topped with boron as an impurity.
After molding 02 and releasing silicon oxide II IO3 into a thin shape only in the gauge part, polycrystalline silicon Y104 is deposited.
Figure 1 (a)) Next, this polycrystalline silicon 104 is thermally nitrided with aluminum gas to form silicon nitride 1[10
5・At this time, in order to increase the lI dielectric constant, polycrystalline silicon 104,! It is also considered that impurities such as ', BoMV, etc. are doped. Also, regarding this nitriding, polycrystalline ratio: 1
As an example, it is possible to leave a portion of :/104 in an amount of about 10-Zoom. (!1 Figure (&)) Finally, use an aluminum 106 tube shape as a gauge electrode.M]10
The g-element is charged and discharged. (Fig. 1 C61) The features of the MNO8III device of the present invention manufactured by the above process are as follows: [11] Since the silicon nitride film is formed by thermal nitridation, there are fewer cracks, pinholes, etc.
（２５多結晶シリコンに不純物ドープすることＫより誘
電率及び膜質をコントロールでき、最適をシリコン窒化
膜が、再現性１〈形Ｊできる。(25 By doping polycrystalline silicon with impurities, the dielectric constant and film quality can be controlled by K, and the optimum silicon nitride film can be formed with a reproducibility of 1.
【Ｊ 一部シリボン酸化膜界面に、多結晶シリコンを残
存させることに工す、電荷の界面近傍へ集中的にトラッ
プできる。[J By partially leaving polycrystalline silicon at the silicon oxide film interface, charges can be trapped near the interface in a concentrated manner.
これらの特徴は、従来の方法でみられ霞欠点を全て一掃
し、信頼性の高Ｖ％ Ｍ Ｍ ＯＢ素子を提供するもの
である。These features eliminate all haze defects found in conventional methods and provide a highly reliable V% M M OB device.
１１１図−１〜（ａ）が１本発明の実施例である。 以 上 出願人 株式会社諏訪精工舎 代理人 最 上 務 Figures 111-1 to (a) are examples of the present invention. that's all Applicant: Suwa Seikosha Co., Ltd. Representative's top duties
Claims (1)
ｅ−０−イｄ−−日−ｍａｏｓｄｕａｔｏｒ）素子に於
いて、シリコン酸化膜を形ゴ後、多結晶シリコン膜を形
匠し、＃多結晶シリコン膜を熱窒化してシリコン窒化膜
とすることを特徴とする半導体装置の製造方法。 （２１前記疹結晶シリコン膜の熱窒化に際し、ＷＩ多結
晶シリコ／ＩＩの全て、もしくは一部を熱窒化すること
を特命とする半導体装置の製造方法。[Claims] (11M M OB (bro-tag-Nitrid)
In the device, after forming the silicon oxide film, forming the polycrystalline silicon film, and thermally nitriding the polycrystalline silicon film to form a silicon nitride film. A method for manufacturing a semiconductor device, characterized by: (21) A method for manufacturing a semiconductor device in which, when thermally nitriding the crystalline silicon film, all or a part of the WI polycrystalline silicon/II is thermally nitrided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11601181A JPS5817677A (en) | 1981-07-24 | 1981-07-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11601181A JPS5817677A (en) | 1981-07-24 | 1981-07-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5817677A true JPS5817677A (en) | 1983-02-01 |
Family
ID=14676608
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11601181A Pending JPS5817677A (en) | 1981-07-24 | 1981-07-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5817677A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5913149A (en) * | 1992-12-31 | 1999-06-15 | Micron Technology, Inc. | Method for fabricating stacked layer silicon nitride for low leakage and high capacitance |
| JP2004508727A (en) * | 2000-09-05 | 2004-03-18 | ダルサ、コーポレーション | Image sensor and manufacturing method thereof |
-
1981
- 1981-07-24 JP JP11601181A patent/JPS5817677A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5913149A (en) * | 1992-12-31 | 1999-06-15 | Micron Technology, Inc. | Method for fabricating stacked layer silicon nitride for low leakage and high capacitance |
| JP2004508727A (en) * | 2000-09-05 | 2004-03-18 | ダルサ、コーポレーション | Image sensor and manufacturing method thereof |
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