JP2004221448A - Non-volatile semiconductor memory device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device capable of improving the charge holding characteristics of a silicon nitride film constituting a charge accumulation layer, and to provide a method for manufacturing the storage device. <P>SOLUTION: A data holding characteristic is improved by using a silicon nitride film of which Si-H coupling density is ≤1×10<SP>19</SP>cm<SP>-3</SP>as a charge accumulation layer 4 of a non-volatile memory such as an MNOS memory or an MONOS memory. In order to form the silicon nitride film, an LPCVD method using silicon tetrachloride (SiCl<SB>4</SB>) and ammonia (NH<SB>3</SB>) as material gas can be suitably used. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly to a nonvolatile semiconductor memory device represented by a flash memory or an EEPROM (Electrical Erasable-Programmable Read Only Memory) and a method of manufacturing the same.
[0002]
[Prior art]
The retention of information in an MNOS (Metal-Nitride-Oxide-Semiconductor) or MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) nonvolatile memory is performed by accumulating electric charges in a silicon nitride film.
[0003]
Conventionally, the silicon nitride film used for the charge storage layer of the nonvolatile memory is made of monosilane (SiH₄  ) Or dichlorosilane (SiH₂  Cl₂  ) And ammonia (NH₃  ) Was used as a source gas (see Patent Document 1). In addition, a silicon dioxide film formed by oxidizing a silicon nitride film, which is a charge storage layer, is used as a dielectric layer called a top dielectric layer on the charge storage layer.
[0004]
[Patent Document 1]
JP 2002-203917 A
[0005]
[Problems to be solved by the invention]
When a silicon nitride film is formed using dichlorosilane or monosilane as a raw material, 1 × 10²⁰cm^-3The above Si-H bonds are included. It is considered that the dangling bond of Si formed by the elimination of hydrogen (H) of the Si—H bond by a thermal process after the formation of the silicon nitride film forms a shallow level.
[0006]
The accumulated charges can be easily released from the silicon nitride film through a shallow level. Actually, the higher the Si—H bond density in silicon nitride immediately after film formation, the lower the retention characteristics of the MNOS memory or MONOS memory.
[0007]
Further, when an attempt is made to form a dielectric layer called a top dielectric layer by oxidizing a silicon nitride film as a charge storage layer, the oxidation step causes the formation of H groups from Si-H bonds in the silicon nitride film. Desorption is promoted. As a result, the retention characteristics of the memory deteriorate due to the formed shallow level. If the charge retention characteristics of the memory are degraded in this way, high-speed access cannot be achieved.
[0008]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of improving the charge retention characteristics of a silicon nitride layer forming a charge storage layer, and a method of manufacturing the same. It is in.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention comprises a first dielectric layer formed on an active region of a semiconductor substrate, and a silicon nitride formed on the first dielectric layer. A charge storage layer including a layer, a gate electrode formed on the charge storage layer, and two semiconductor regions formed on the semiconductor substrate on both sides of the gate electrode and serving as a source or a drain. Si—H bond density of the silicon layer is 1 × 10¹⁹cm^-3It is specified below.
[0010]
The semiconductor device further includes a second dielectric layer formed between the charge storage layer and the gate electrode.
[0011]
In the above-described nonvolatile semiconductor memory device of the present invention, the Si—H bond density of the silicon nitride layer serving as the charge storage layer is set to 1 × 10¹⁹cm^-3It is specified low as follows.
When the H group in the Si—H bond is eliminated, a shallow level is formed. When a shallow level is formed in the charge storage layer, the stored charges can be released from the charge storage layer through the shallow level.
In the present invention, the Si—H bond density of the silicon nitride layer itself serving as the charge storage layer is set to 1 × 10¹⁹cm^-3By setting it as low as the following, formation of a shallow level due to elimination of the H group is suppressed.
[0012]
Further, in order to achieve the above object, a method for manufacturing a nonvolatile semiconductor memory device according to the present invention comprises a step of forming a first dielectric layer on an active region of a semiconductor substrate; The Si—H bond density immediately after film formation is 1 × 10¹⁹cm^-3Forming a silicon nitride layer to form a charge storage layer as follows, forming a gate electrode on the charge storage layer, and forming a source or drain on the semiconductor substrate on both sides of the gate electrode. Forming two semiconductor regions to be formed.
[0013]
In the step of forming the charge storage layer, the silicon nitride layer is formed using silicon tetrachloride and ammonia as source gases.
[0014]
Forming a second dielectric layer on the charge storage layer after forming the charge storage layer and before forming the gate electrode, forming the gate electrode Forming the gate electrode on the second dielectric layer.
[0015]
In the step of forming the second dielectric layer, a silicon dioxide layer is formed by low pressure chemical vapor deposition using dichlorosilane or silicon tetrachloride and dinitrogen monoxide as raw materials.
[0016]
In the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, the Si—H bond density immediately after the film formation is 1 × 10¹⁹cm^-3A charge storage layer is formed by forming a silicon nitride layer as described below.
When the H group in the Si—H bond is eliminated, a shallow level is formed. When a shallow level is formed in the charge storage layer, the stored charges can be released from the charge storage layer through the shallow level.
According to the present invention, the Si—H bond density of the silicon nitride layer itself serving as the charge storage layer is 1 × 10¹⁹cm^-3By forming so as to be as low as below, formation of a shallow level due to elimination of the H group is suppressed.
Further, in the step of forming the second dielectric layer, a silicon dioxide layer is formed by low pressure chemical vapor deposition, and the film formation temperature is made lower than the formation method by oxidation, so that the accumulated electric charge is reduced. The formation of shallow levels that are easily emitted is suppressed.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings, taking a case where an n-channel type memory transistor is used as a storage element as an example. The p-channel memory transistor is realized by reversing the impurity conductivity type and the polarity of the applied voltage in the following description.
[0018]
First embodiment
FIG. 1 is a diagram illustrating a cross-sectional structure of the nonvolatile memory transistor according to the first embodiment.
[0019]
This memory transistor is formed, for example, on a semiconductor substrate such as a p-type silicon wafer, a p-well formed on the inner surface of the semiconductor substrate, or a p-type silicon layer having an SOI type substrate isolation structure (hereinafter simply referred to as substrate 1). . An element isolation insulating film 2 formed by, for example, LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation) is formed on the surface of the substrate 1 as necessary. The substrate surface portion where the element isolation insulating film 2 is not formed becomes an active region where an element including the memory transistor is formed.
[0020]
A first dielectric layer 3, a charge storage layer 4, a second dielectric layer 5, and a gate electrode 6 are stacked on the active region. The word line of the memory cell array is constituted by the gate electrode 6 itself or an upper wiring layer (not shown) connected to the gate electrode 6.
[0021]
The first dielectric layer 3 functions as a potential barrier, and has a thickness of, for example, about 1 nm to 12 nm.₂  Consisting of a film.
The charge storage layer 4 functions as a charge storage unit, and is formed of silicon nitride SiN_X  (X> 0). In this embodiment, the Si—H bond density in the silicon nitride film serving as the charge storage layer 4 is 1 × 10¹⁹cm^-3It is characterized by the points specified below.
The second dielectric layer 5 is made of, for example, a silicon dioxide film, and has a thickness of about 3 nm to 10 nm.
The gate electrode 6 is made of polycrystalline silicon doped with impurities at a high concentration, or polycrystalline silicon Si, and CoSi formed thereon._x  , WSi₂  , TiN, TaSi₂  , TiSi₂  , Ti, W, Cu, Al, Au and the like.
[0022]
Two source / drain regions 7 having a so-called LDD (Lightly Doped Drain) are formed apart from each other on the inner surface of the silicon active region on both sides of the gate laminated structure having such a configuration. One of the two source / drain regions 7 functions as a source and the other functions as a drain according to the voltage application direction during operation.
In addition, on both side surfaces of the gate laminated structure, an insulating layer 8 called a so-called sidewall insulating film is formed. The n-type impurity is introduced at a relatively low concentration and shallowly into the active region located immediately below the sidewall insulating film 8, so that the n-type⁻  An impurity region (LDD) 7a is formed. Further, by using the sidewall insulating film 8 as a self-alignment mask and introducing n-type impurities at a relatively high concentration and deeply on both sides thereof, the n-type impurity which forms the main part of the source / drain region 7 is formed.⁺  Impurity region 7b is formed.
Note that an active region portion between the two source / drain regions 7 becomes a channel forming region 9 of the memory transistor.
[0023]
Next, a method for manufacturing the above memory transistor will be described with reference to the drawings. Here, FIG. 2 to FIG. 4 are cross-sectional views in manufacturing the memory transistor according to the first embodiment.
As shown in FIG. 2A, an element isolation insulating film 2 is formed on a substrate 1 by a LOCOS method or an STI method. Thereafter, if necessary, impurity doping for adjusting the threshold voltage of the memory transistor is performed by, for example, an ion implantation method.
[0024]
Next, as shown in FIG. 2B, the surface of the substrate 1 heated from 800 ° C. to 1000 ° C.₂  Or N₂  By exposing to O, a silicon dioxide film of about 1 nm to 12 nm is formed to form the first dielectric layer 3. Subsequently, with the substrate temperature kept at 700 ° C. to 1000 ° C., the surface of the silicon dioxide₃  For several tens of minutes to nitride the surface of the silicon dioxide film. This high temperature nitriding treatment is for reducing the incubation time at the time of depositing the next silicon nitride film.
[0025]
Next, as shown in FIG. 2C, a charge storage layer 4 is formed on the first dielectric layer 3. In forming the charge storage layer 4, the substrate temperature is raised from about 600 ° C. to about 800 ° C., and silicon tetrachloride (tetrachlorosilane) SiCl₄  And ammonia NH₃  Is flowed under the condition that the total pressure in the chamber is several hundred Pa, and a silicon nitride film is formed in a thickness of about 2 nm to 30 nm by a CVD (Chemical Vapor Deposition) method. For example, the flow rate of silicon tetrachloride is set to 50 sccm, the flow rate of ammonia is set to 50 sccm, and the gas is supplied so that the pressure in the chamber becomes 100 Pa.
The Si—H bond density of the silicon nitride film constituting the charge storage layer 4 manufactured under the above conditions is 1 × 10¹⁹cm^-3It is as follows.
[0026]
Next, as shown in FIG. 3D, the substrate temperature is set to about 900 ° C. to 950 ° C., and the surface of the silicon nitride film forming the charge storage layer 4 is thermally oxidized to form the second dielectric layer. 5 is formed. In consideration of the reduction in the thickness of the silicon nitride film during the thermal oxidation, a silicon nitride film is deposited in advance in the step shown in FIG.
[0027]
Next, as shown in FIG. 3E, a gate electrode 6 having a thickness of about 50 nm to 200 nm is formed on the second dielectric layer 5. In the formation of the gate electrode 6, for example, polycrystalline silicon doped with a high concentration impurity is CVD-formed on the second dielectric layer 5. In the formation of this polycrystalline silicon, monosilane (SiH₄  ), Dichlorosilane (SiCl₂  H₂  ), Tetrachlorosilane (SiCl₄  ), Or a sputtering method using polycrystalline silicon as a target. Here, polycrystalline silicon is deposited by CVD at a substrate temperature of 650 ° C., and a low-resistance layer made of a metal, a high melting point metal, an alloy containing the metal silicide, or the like is formed on the polycrystalline silicon as necessary. I do. The material of the low resistance layer is CoSi_x  , WSi₂  , TiN, TaSi₂  , TiSi₂  , Ti, W, Cu, Al, Au and the like are used.
[0028]
Next, as shown in FIG. 4F, a pattern of a dielectric film having excellent dry etching resistance is formed as necessary, and anisotropic etching such as RIE is performed using the dielectric film or a resist as a mask. By performing (Reactive Ion Etching), the gate electrode 6, the second dielectric layer 5, and the charge storage layer 4 are patterned.
[0029]
Next, an n-type impurity is ion-implanted at a low concentration into the surface of the Si active region using the gate laminated film as a self-alignment mask and the first dielectric layer 3 as a through film, and n⁻  An impurity region (LDD region) 7a is formed. In this ion implantation, for example, arsenic ions (As⁺) Is 1-5 × 10^Thirteencm^-2Doping at a moderate density.
After that, the entire surface is SiO₂  A film is deposited to a thickness of about 100 nm to 200 nm, and this is etched back by anisotropic etching such as RIE. As a result, as shown in FIG. 4G, the sidewall insulating films 8 are formed on the side surfaces of the stacked films 6, 5, and 4 of the gate.
[0030]
In the subsequent steps, high-concentration n-type impurities are ion-implanted into the Si active region outside the sidewall insulating film 8,⁺  An impurity region 7b is formed. Thus, the source / drain regions 7 having the LDD structure are formed (FIG. 1). In this ion implantation, for example, As is self-aligned using the gate laminated film and the sidewall insulating film 8 as a mask.⁺  From 1 to 5 × 10^Fifteencm^-2Doping at a moderate density.
After that, an interlayer dielectric film and a wiring layer are formed to complete the memory transistor.
[0031]
Next, a first bias setting example for the operation of the memory transistor according to the first embodiment will be described.
At the time of writing, the two source / drain regions 7 are held at 0 V with reference to the potential of the substrate 1, and a positive voltage, for example, 10 V is applied to the gate electrode 6. At this time, electrons are accumulated in the channel formation region 9 to form an inversion layer, and a part of the electrons in the inversion layer are conducted through the first dielectric layer 3 by a tunnel effect, and the charge accumulation layer 4 is nitrided. The charge is trapped in the charge trap formed in the silicon film.
[0032]
At the time of reading, 0 V is applied to one of the source / drain regions 7 based on the potential of the substrate 1 and 1.5 V is applied to the other, and the number of trapped electrons in the charge storage layer 4 affects the threshold voltage. A voltage in a range that does not change until it comes out, for example, 2.5 V, is applied to the gate electrode 6. Under this bias condition, the conductivity of the channel changes significantly depending on the presence or absence of trapped electrons in the charge storage layer 4 or the amount of trapped electrons. That is, when electrons are sufficiently injected into the charge storage layer 4, the stored electrons relatively increase the potential of the channel and increase the electron density in the channel, as compared with the case where electrons are not sufficiently injected into the charge storage layer 4. The conductivity between the source and drain is small to reduce Conversely, when electrons are not sufficiently injected into the charge storage layer 4, the potential of the channel is relatively low, and the conductivity between the source and the drain increases. This difference in channel conductivity is effectively converted to a change in channel current or drain voltage. The change in the current amount or the drain voltage of the channel is amplified by a detection circuit such as a sense amplifier and read out as stored information to the outside.
In the first bias setting example, writing is performed on the entire surface of the channel, so that reading is possible even when the voltage application directions of the source and the drain are reversed.
[0033]
At the time of erasing, 0 V is applied to both of the two source / drain regions 7 based on the potential of the substrate 1, and a negative voltage, for example, −10 V is applied to the gate electrode 6. At this time, the electrons held in the charge storage layer 4 tunnel through the first dielectric layer 3 and are forcibly extracted to the channel formation region 9. As a result, the memory transistor is returned to the state before writing (erasing state) in which the amount of captured electrons in the charge storage layer 4 is sufficiently low.
[0034]
Next, a second bias setting example for the operation of the memory transistor according to the first embodiment will be described.
At the time of writing, 0 V is applied to one of the two source / drain regions 7 and 5 V to the other, and a positive voltage, for example, 10 V, is applied to the gate electrode 6 based on the potential of the substrate 1. At this time, electrons are accumulated in the channel forming region 9 to form an inversion layer. In the inversion layer, electrons supplied from the source are accelerated by an electric field between the source and the drain, and a high kinetic energy is generated at the end of the drain. It becomes hot electrons. If some of the hot electrons have an energy higher than the potential barrier height defined by the first dielectric layer 3, those electrons will cross the potential barrier of the first dielectric layer 3 by a scattering process and accumulate charge. The charge is trapped in the charge trap formed in the silicon nitride film that is the layer 4.
[0035]
Reading is performed in the same manner as in the first bias setting example. However, in the second bias setting example, electric charges are accumulated on the drain side to which 5 V is applied at the time of writing. Therefore, in reading, it is necessary to apply a voltage between the source and the drain such that the electric charge accumulation side becomes the source. .
At the time of erasing, FN tunneling is used as in the first bias setting example, or band-to-band tunneling is used. In the latter method, 5 V is applied to one or both of the source / drain regions 7 based on the substrate potential, and the source / drain regions 7 to which 5 V is not applied are kept at 0 V, and -5 V is applied to the gate electrode 6. The surface of the source / drain region 7 to which 5 V is applied is depleted, and a high electric field is generated in the depletion layer, so that a band-to-band tunnel current is generated. Holes caused by the band-to-band tunnel current are accelerated by an electric field to obtain high energy. The high energy holes are attracted to the gate voltage and injected into the charge traps in the silicon nitride film forming the charge storage layer 4. As a result, the charges of the stored electrons in the charge storage layer are canceled by the injected holes, and the memory transistor is returned to an erased state, that is, a state in which the threshold voltage is low.
[0036]
Next, a third bias setting example for the operation of the memory transistor according to the first embodiment will be described. The basics of the bias setting are the same as those in the second bias setting example. In the third bias setting example, an operation of storing two bits in one memory transistor will be described.
At the time of writing the first information, 0 V is applied to one of the two source / drain regions 7 and 5 V to the other, and a positive voltage, for example, 10 V, is applied to the gate electrode 6 based on the potential of the substrate 1. At this time, electrons are accumulated in the channel forming region 9 to form an inversion layer. In the inversion layer, electrons supplied from the source are accelerated by an electric field between the source and the drain, and a high kinetic energy is generated at the end of the drain. It becomes hot electrons. If some of the hot electrons have an energy higher than the potential barrier height defined by the first dielectric layer 3, those electrons will cross the potential barrier of the first dielectric layer 3 by a scattering process and accumulate charge. The charge is trapped in the charge trap formed in the silicon nitride film forming the layer 4.
At the time of writing the second information, the voltages of the two source / drain regions 7 are reversed from those at the time of writing the first information. At the time of writing the first information, channel hot electrons are injected from the side of the source / drain region 7 to which 5 V is applied, and electrons are captured in a part of the charge storage layer 4 centered on the other end. I have. On the other hand, in the writing of the second information, binary information (second information) is written into one end of the charge storage layer 4 independently of the first information. 0 V is applied to the other side of the region 7 and 5 V is applied to one side. Electrons supplied from the other source / drain region 7 to which 0 V is applied are turned into hot electrons on the side of the one source / drain region 7 to which 5 V is applied, and injected into a part of one side of the charge storage layer. In the third operation example, the amount of injected electrons and the gate length of the memory transistor are determined so that the two pieces of 2-bit information do not overlap each other.
[0037]
In the reading of the 2-bit information, the voltage application direction between the source and the drain is determined so that the source / drain region 7 closer to the side where the information to be read is written becomes the source.
When reading the first information, 0 V is applied to the other source / drain region 7 close to the first information, and 1.5 V is applied to one source / drain region 7. A voltage in a range that does not change the number of trapped electrons until the threshold voltage is affected, for example, 2.5 V, is applied to the gate electrode 6. Under this bias condition, the conductivity of the channel changes remarkably in accordance with the presence or absence of trapped electrons or the amount of trapped electrons existing at the source side end in the charge storage layer 4. That is, when electrons are sufficiently injected into the end of the charge storage layer 4 on the source side, the stored electrons are not sufficiently injected into the end on the source side of the charge storage layer 4 compared to when the electrons are sufficiently injected into the end of the channel. The conductivity between the source and the drain is small because the potential of the portion is relatively increased to reduce the electron density in the channel. At this time, in the vicinity of the drain side, the potential for electrons is lowered by the drain voltage regardless of the presence or absence of electrons at the end of the charge storage layer 4 on the drain side. In addition, since the drain end is in a pinch-off state at the time of this reading, the presence or absence of electrons at the end on the drain side of the charge storage layer 4 has less influence on the conductivity of the channel. That is, since the threshold voltage of the transistor reflects the amount of trapped electrons on the source side with a lower electric field, the first information is read out by the detection circuit under this bias condition.
On the other hand, when reading the second information, 0 V is applied to one source / drain region 7 near the second information, 1.5 V is applied to the other source / drain region 7, and Apply 2.5V. Under this bias condition, a low electric field is applied to one of the source / drain regions 7, so that the second information is read according to the same principle as when reading the first information.
[0038]
At the time of erasing, FN tunneling is used as in the first bias setting example, or band-to-band tunneling is used as in the second bias setting example.
[0039]
Next, the effects of the nonvolatile semiconductor memory device of the present embodiment and the method of manufacturing the same will be described with reference to the drawings.
[0040]
FIG. 5 is a diagram for explaining the data retention characteristics of the nonvolatile memory according to the present embodiment. The horizontal axis in FIG. 5 indicates time (s), and the vertical axis indicates threshold voltage (V) during data writing. FIG. 5 shows the time dependence of the threshold voltage when data is held at 85 ° C.
[0041]
In FIG. 5, a graph CV1 shows the data retention characteristic of the nonvolatile memory according to the present embodiment. As described above, the silicon nitride film serving as the charge storage layer 4 is made of silicon tetrachloride (SiCl₄  ) And ammonia (NH₃  ) As a source gas. The silicon nitride film serving as the charge storage layer 4 has an Si—H bond of 1 × 10¹⁹cm^-3It is contained only at the following densities.
In FIG. 5, a graph CV2 shows the data retention characteristic of the nonvolatile memory of the comparative example, in which the silicon nitride film serving as the charge storage layer 4 is made of dichlorosilane (SiH₂  Cl₂  ) And ammonia (NH₃  ) As a source gas. This silicon nitride film has an Si—H bond of 1 × 10²⁰cm^-3It is included at the above density. In both cases, a silicon oxide film having a thickness of 1.8 nm is used as the first dielectric layer 3, a silicon nitride film serving as the charge storage layer 4 is set to have a thickness of 20 nm, and a second dielectric layer 5 is used. A silicon oxide film having a thickness of 3.5 nm was used.
[0042]
As shown in FIG. 5, silicon tetrachloride (SiCl₄  ) And ammonia (NH₃  It can be seen that the non-volatile memory having the charge storage layer made of the silicon nitride film manufactured using (1) as the source gas has a threshold window of 1.5 V or more at Y10 ten years later. In the figure, V0 indicates the threshold voltage of the channel, and V1 indicates the threshold voltage at the time of data erasure. The threshold window is calculated as the difference between the voltage at the time of data writing and the threshold voltage at the time of data erasing.
[0043]
In contrast, silicon tetrachloride (SiCl₄  ) And ammonia (NH₃  The non-volatile memory of the comparative example having the charge storage layer made of the silicon nitride film manufactured using) as the source gas has a threshold window of only about 0.5 V at time Y10 ten years later. The above threshold window has not been obtained.
[0044]
FIG. 6 is a diagram showing the relationship between the Si—H bond density of a silicon nitride film serving as a charge storage layer and data retention characteristics. The horizontal axis in FIG. 6 is the Si—H bond density (cm³), And the vertical axis indicates the threshold window. FIG. 6 shows a measured value of the threshold window when data is held at 85 ° C. for 10 years.
[0045]
In the measurement of the threshold window shown in FIG. 6, a 1.8 nm silicon oxide film is used as the first dielectric layer 3, a 20 nm silicon nitride film is used as the charge storage layer 4, and the second dielectric layer 5 is used. A silicon oxide film having a thickness of 3.5 nm was used.
[0046]
In FIG. 6, the measured value W1 is a value obtained by measuring silicon tetrachloride (SiCl₄  ) And ammonia (NH₃  3) shows a Si—H bond density and a threshold window of a charge storage layer made of a silicon nitride film manufactured using ()) as a source gas.
Also, in FIG. 6, the measured value W2 is the value of dichlorosilane (SiH₂  Cl₂  ) And ammonia (NH₃  3) shows a Si—H bond density and a threshold window of a charge storage layer made of a silicon nitride film manufactured using ()) as a source gas.
[0047]
As shown in FIG. 6, silicon tetrachloride (SiCl₄  ) And ammonia (NH₃  The charge storage layer 4 made of a silicon nitride film manufactured using ()) as a source gas has a Si—H bond density of 1 × 10¹⁹cm^-3It is as follows. In addition, dichlorosilane (SiH₂  Cl₂  ) And ammonia (NH₃  The charge storage layer made of a silicon nitride film manufactured using ()) as a source gas has a Si—H bond density of 1 × 10²⁰cm^-3That is all.
Thus, silicon tetrachloride (SiCl₄  ) And ammonia (NH₃  ) Is used as a source gas, the Si—H bond density in the silicon nitride film is 1 × 10¹⁹cm^-3The lesser number is less than silicon tetrachloride (SiCl₄  ) Itself does not have a Si-H bond. Conversely, dichlorosilane (SiH₂  Cl₂  ) And ammonia (NH₃  ) Is used as a source gas, the Si—H bond density in the silicon nitride film is 1 × 10²⁰cm^-3The reason for the above is that dichlorosilane (SiH₂  Cl₂  ) Itself contains Si-H bonds.
[0048]
Then, the Si—H bond density in the silicon nitride film is 1 × 10¹⁹cm^-3It can be seen that the threshold window of the nonvolatile memory having the following charge storage layer is maintained at about 2.0 V even after 10 years. On the other hand, the Si—H bond density in the silicon nitride film is 1 × 10²⁰cm^-3It can be seen that the threshold window of the nonvolatile memory having the above-described charge storage layer has been reduced to 1.0 V or less after 10 years.
[0049]
In a non-volatile memory, a threshold window needs to be 1.5 V or more in order to achieve high-speed access of about 200 ns or less. In order to realize this, the Si—H bond density must be 1 × 10¹⁹cm^-3It turns out that it is necessary to do the following. The reason why the lower limit of the Si—H bond density is not specified is that a silicon nitride film having such a Si—H bond density cannot be manufactured.
[0050]
As described above, as the charge storage layer 4 of the nonvolatile memory such as the MNOS memory or the MONOS memory, the Si—H bond density is 1 × 10¹⁹cm^-3By using the following silicon nitride film, data retention characteristics can be improved. In order to form this silicon nitride film, silicon tetrachloride (SiCl₄  ) And ammonia (NH₃  ) Can be suitably used as a source gas.
[0051]
Second embodiment
The cross-sectional structure of the nonvolatile memory transistor according to the present embodiment is substantially the same as that of the first embodiment shown in FIG. 1, but differs in the method of forming the second dielectric layer 5.
In the present embodiment, in the step of forming the second dielectric layer 5 shown in FIG.₂  Cl₂  ) And nitrous oxide (N₂  A second dielectric layer 5 is formed by forming a silicon dioxide film at 750 ° C. by LPCVD using O) as a source gas. Alternatively, silicon tetrachloride (SiCl₄  ) And nitrous oxide (N₂  A second dielectric layer 5 is formed by forming a silicon dioxide film at 750 ° C. by LPCVD using O) as a source gas. The other steps are substantially the same as those of the first embodiment, and thus redundant description will be omitted.
[0052]
FIG. 7 is a diagram for explaining data retention characteristics of the nonvolatile memory according to the present embodiment. The horizontal axis of FIG. 7 indicates time (s), and the vertical axis indicates threshold voltage (V) at the time of data writing. FIG. 7 shows the time dependency of the threshold voltage when data is held at 85 ° C.
[0053]
In FIG. 7, a graph CV3 shows the data retention characteristic of the nonvolatile memory according to the second embodiment, in which dichlorosilane (SiH₂  Cl₂  ) And nitrous oxide (N₂  A silicon dioxide film formed at 750 ° C. by LPCVD using O) as a source gas is used.
In FIG. 5, a graph CV4 shows the data retention characteristic of the nonvolatile memory according to the first embodiment, which is formed by oxidizing a silicon nitride film as the charge storage layer 4 as the second dielectric layer 5 at 950 ° C. In this case, a silicon dioxide film is used.
In both cases, a silicon oxide film having a thickness of 2.4 nm is used as the first dielectric layer 3, a silicon nitride film serving as the charge storage layer 4 is set to have a thickness of 9 nm, and the second dielectric layer 5 is used as the second dielectric layer 5. A silicon oxide film having a thickness of 4 nm was used.
[0054]
As shown in FIG. 7, the nonvolatile memory having the second dielectric layer 5 made of a silicon dioxide film formed at a low temperature by an LPCVD method is made of a silicon dioxide film formed at a high temperature by a thermal oxidation method. Compared with the non-volatile memory having the second dielectric layer 5, the slope of the decrease in the threshold voltage until the time point Y10 ten years later is smaller, and it can be said that the data retention characteristics are excellent.
[0055]
As described above, when the second dielectric layer 5 is to be formed by thermally oxidizing the underlying silicon nitride film, the oxidization process causes desorption of the H group from the Si—H bond in the silicon nitride film. It is supposed that the retention characteristics of the memory are degraded by the shallow level formed in the silicon nitride film serving as the charge storage layer 4 as a result.
On the other hand, by forming the second dielectric layer 5 by using the LPCVD method, the temperature can be reduced as compared with the thermal oxidation method. The elimination of the H group of the H bond can be suppressed, and the data retention characteristics can be improved.
[0056]
As described above, when the nonvolatile memory is manufactured using the silicon nitride film described in the first embodiment as the charge storage layer 4, the second dielectric layer 5 is formed by the LPCVD method having a lower temperature than the thermal oxidation method. By forming a film using, the data retention characteristics can be further improved.
[0057]
The present invention is not limited to the above-described first and second embodiments, and various modifications based on the technical idea of the present invention are possible.
For example, the Si—H bond density immediately after the formation of the silicon nitride film serving as the charge storage layer 4 is 1 × 10¹⁹cm^-3If the silicon nitride film can be formed as described below, the source gas can be changed from that of the above-described embodiment.
[0058]
The first dielectric layer 3 and the second dielectric layer 5 are not limited to silicon dioxide, for example, silicon nitride SiN_X  , Silicon oxynitride SiN_X  O_y  , Aluminum oxide Al₂O₃  , Tantalum oxide Ta₂  O₅  , Zirconium oxide ZrO₂  , Hafnium oxide HfO₂  May be formed from any of the above materials.
[0059]
Although a large number of memory transistors shown in FIG. 1 are arranged in a matrix to form a memory cell array, the cell system is not limited. In the NOR type, any of a system in which a source line is separated and a virtual ground cell system in which a source line and a bit line are shared between cells in a word direction can be adopted. Further, any of the so-called AND type, HiCR type, and DINOR type, which are a kind of NOR type, may be used. Furthermore, the adoption of a NAND type is also possible.
In addition, various changes can be made without departing from the spirit of the present invention.
[0060]
【The invention's effect】
According to the nonvolatile semiconductor memory device and the method of manufacturing the same of the present invention, it is possible to improve the charge retention characteristics of the conventional silicon nitride film forming the charge storage layer.
[Brief description of the drawings]
FIG. 1 is a sectional view of a nonvolatile memory transistor according to first and second embodiments.
FIG. 2 is a cross-sectional view until a charge storage layer is formed in the manufacture of the memory transistor according to the first and second embodiments.
FIG. 3 is a sectional view until a gate electrode is formed in the manufacture of the memory transistor according to the first and second embodiments.
FIG. 4 is a cross-sectional view up to formation of a sidewall insulating film in the manufacture of the memory transistor according to the first and second embodiments.
FIG. 5 is a diagram for explaining data retention characteristics of the nonvolatile memory according to the first embodiment.
FIG. 6 is a diagram showing a relationship between a Si—H bond density of a silicon nitride film serving as a charge storage layer and data retention characteristics.
FIG. 7 is a diagram for explaining data retention characteristics of a nonvolatile memory according to a second embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Element isolation insulating film, 3 ... First dielectric layer, 4 ... Charge storage layer, 5 ... Second dielectric layer, 6 ... Gate electrode, 7 ... Source / drain region, 8 ... Side Wall insulating film, 9: channel formation region.

Claims (6)

A first dielectric layer formed on an active region of the semiconductor substrate;
A charge storage layer formed on the first dielectric layer and including a silicon nitride layer;
A gate electrode formed on the charge storage layer;
Having two semiconductor regions formed on the semiconductor substrate on both sides of the gate electrode and serving as a source or a drain,
A nonvolatile semiconductor memory device in which the Si—H bond density of the silicon nitride layer is specified to be 1 × 10 ¹⁹ cm ⁻³ or less. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising a second dielectric layer formed between said charge storage layer and said gate electrode. Forming a first dielectric layer on an active region of a semiconductor substrate;
Forming a charge storage layer by forming a silicon nitride layer on the first dielectric layer such that the Si—H bond density immediately after the formation is 1 × 10 ¹⁹ cm ⁻³ or less;
Forming a gate electrode on the charge storage layer;
Forming two semiconductor regions serving as a source or a drain on the semiconductor substrate on both sides of the gate electrode. 4. The method according to claim 3, wherein, in the step of forming the charge storage layer, the silicon nitride layer is formed using silicon tetrachloride and ammonia as source gases. After the step of forming the charge storage layer, before the step of forming the gate electrode, the method further includes a step of forming a second dielectric layer on the charge storage layer,
4. The method according to claim 3, wherein, in the step of forming the gate electrode, the gate electrode is formed on the second dielectric layer. 6. The nonvolatile semiconductor memory according to claim 5, wherein in the step of forming the second dielectric layer, a silicon dioxide layer is formed by low pressure chemical vapor deposition using dichlorosilane or silicon tetrachloride and dinitrogen monoxide as raw materials. Device manufacturing method.

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