JPS5815351A - Error measuring circuit - Google Patents

Abstract

PURPOSE:To easily measure an error, by storing the same signal as an input signal to an ROM, and comparing and synchronizing the stored signal with the input signal, and resetting the ROM to a start address if any error is generated. CONSTITUTION:An ROM12 is operated with an output of a counter 11 and the content of memory of the ROM12 and an input signal are compared at a gate circuit 14a. An FF15 is operated with the output of the circuit 14a, and a counter 16 counting the output of the FF15 and an FF17 operated with the output of the counter 16 are provided. This counter 16 continuously compares and collates the memory content of the ROM12 and the input signal and takes synchronism. If any error is produced before the synchronism is taken, the ROM12 is reset to the start address and this operation is repeated until the synchronism is taken. Thus, error measurement of an arbitrary code can be performed by only replacing the ROMs.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to an error measurement circuit for measuring errors in a data transmission line.

(21 Prior Art An example of a conventional circuit is shown in FIG. 1. In the figure, 1 is a shift register, 2 is a decoder, 3J1 to 3c are gate circuits, 4 is a 7-lip 70-tube, 5 is a selector, and 68 to 6c are terminals. It is.

First, an input signal is transmitted from the terminal 6b through the selector 5 to the input of the shift register 10. The decoder 2 takes out the synchronization pattern 9 through the shift register 1t, sets 7 rip 70 and 14, and switches the input ga of the selector 50.

On the other hand, in the case of a 511-bit random code, the outputs from shift registers 105 and 9 are input to the selector 5 from the gate circuit 5a.

Next, the input from the terminal 6b and the output of the shift register 1 are compared in the gate circuit 3b, and then the gate circuit 3ct-
A beep)IEJ) signal is output from the output terminal 6C.

That is, the conventional circuit shown in FIG. 1 checks whether the input signal has a synchronous pattern, and when a synchronous pattern is found, starts measurement from there.

(31 Problems with the Prior Art) If a 6-bit random code other than 511 bits is required in the conventional circuit as shown in Figure 1, it is necessary to switch the input of the decoder 2 and the gate circuit 3a. , so,
There is one problem in that the composition will be made of multiple carpets.

(41 Purpose of the Invention This invention stores the same signal as the input signal in the t-ROM, compares this signal with the input signal, and if no error occurs, continues to compare and check to synchronize and synchronize. If an error occurs before synchronization is lost, the ROM is reset to the starting address and this operation is repeated until synchronization is achieved. This allows error measurements to be made.

(5) Embodiment of the Invention A circuit according to an embodiment of the invention is shown in FIG. 2, and examples of waveforms of each part of FIG. 2 are shown in FIG. In Figure 2, 11 is a counter, 12
is a ROM, 13 is a selector, 14a to 14hij gate circuit, 15Fi flip-flop, 16 is a counter, 1
7 is a 7 lip flop, and jam to 18c are terminals.

First, the bit random code is stored in the t-ROM 12. Then, the counter 11 is operated with a clock signal from the terminal 18a, and the contents of the ROM 12 are read out. 7 is the clock signal of the terminal 18a, and FIG. 3A is the output of the counter 11.

Further, FIG. 3 shows the output of the ROM 12, and FIG. 3 shows an example of the input signal to the terminal 18b.

An example of the storage contents of the ROM 12 is shown below.

0 bit = the first half of a 2047-bit random code.

1 bit = -1047 bits The second half of the random code.

2 bits = 511 bit random code, 5 bits = repeated periodic code.

The output of the ROM 12 passes through the sector 13 and enters the gate circuit 14a together with the input signal from the terminal 18b. The 5th figure power is the output of the gate circuit 14m, and when it is compared with the 5th figure and the 5th figure, it is "1" because it does not match.

If they match, it becomes "0" K.

The output of the gate circuit 14m enters a seven-lip flop 15. The third figure shows the output waveform of the flip 70 knob 15.

The gate circuit 14d receives the output of the flip-flop 15 and the clock signal from the terminal 18a inverted by the gate circuit 14h. FIG. 5G shows the output waveform of the gate circuit 14d.

The gate circuit 14e receives the inverted output of the third diagram and the clock signal from the terminal 18a inverted by the gate circuit 14h. The third diagram shows the output waveform of the gate circuit 14e.

The input signal from the terminal 18b and the read signal from the ROM 12 are compared by the gate circuit fit4a, and if they do not match, the output of the gate circuit 14e is "0" as shown in the third diagram, so the output of the counter 16 is "0". , input signal and ROM12
When the read signals match, the counter 16 starts counting. When the count set in the counter 16 is reached here.

The output of the counter 16 enters a 7-lip flop 17. Note that the counter 16 can be replaced by the counter 11, and the counter 16 can be omitted. Figure 3 shows the output of the slip 70 knob 17. In the case of FIG. 5, it can be seen from the third diagram that the counter 16 is set to 3 counts.

The gate circuit 14f receives the output of the gate circuit 14d and the output of the 7-lip 70-tub 17), and the flip-flop 17.
If the output becomes "1", measurement of erroneous sibits is started.

The gate circuit 14g has the output of the gate circuit 14d and the third
The inverted output shown in the figure is input, and the output of the gate circuit 14d is "1".
”, a reset signal is sent through the gate circuit 14bt.

FIG. 5C shows the waveform of the measurement terminal 18C. If an error 9 as shown by the dotted line in FIG. 3G occurs, that error will appear in FIG.

In this way, the circuit of FIG. 2 compares the signal stored in ROM 2 with the input signal, and if there is no difference between a certain bit of the input signal, it starts the WA measurement. If there is an error 9 between bits, K is set so as not to start error measurement. Then, simply by exchanging the ROMzl, code errors can be measured arbitrarily.

(6) Effects of the invention According to this invention, the ROM 12 can be replaced.

Error measurements of various codes can be performed without a switching circuit.

[Brief explanation of the drawing]

FIG. 1 is an example of a conventional circuit, FIG. 2 is an implementation circuit according to the present invention, and FIG. 3 is an example of waveforms of each part of FIG. 2. 1...Shift register, 2...Decoder, 3a to SC...Gate circuit, 4...
・Fritsu 170% 5...Selector, 6a
~6C...terminal. 11...Color/Re, 12...ROM,
1s...Selector, 14.1~14h...
...Gate circuit, 15...7 lip-flop,
16...Counter, 17...7 flip flop, 18a to 18c...Terminal. Agent Patent Attorney Kinji Omata Figure 1 Figure 2

Claims (1)

[Claims] 1. A first counter, and a ROM that operates on the output of the first counter. a gate circuit that compares the memory contents of this ROM and an input signal; a first 7-rip 70 block that operates with the output of this gate circuit; a second counter that counts the output of the first 7-rip flop 7; It is equipped with a second 7-lip 70-tub which operates on the output of the second counter. When the second counter continuously counts the match between the input signal and the memory contents of the ROM, a second 7-lip 70-tub is set and I! 4. An erroneous column determining circuit, characterized in that it starts measuring 4 lines, and resets a first counter and a second counter when the coincidences are counted continuously.