JPS58147234A - Mosfet switch circuit - Google Patents

Abstract

PURPOSE:To absorb variance in the process for manufacturing the on-resistance of MOSFETs, by providing a means for generating a bias voltage corresponding to the threshold voltage of the MOSFET in an MOS switch. CONSTITUTION:The input and output terminals of a C-MOS inverter 13 are connected through an N-channel MOSFET14 as the MOS switch and to the back gate electrode of the MOSFET14, a bias voltage from the bias generating circuit 24 consisting of a P-channel MOSFET21 and the N-channel MOSFET22 is supplied. This bias voltage is equal to the circuit threshold voltage of the C-MOS inverter.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a MOS rg'r switch circuit using MO8FBT for transmitting analog signals.

[Technical background of the invention and one point in between]

With the development of analog ICs such as integrated analog-to-digital conversion circuits, high performance magnetic pressure comparator circuits incorporated in these ICs are also required. There are three characteristics that are particularly required for this magnetic pressure comparator circuit: high-speed response, no offset, and high resolution. FIG. 2 is a configuration diagram of a conventional amplifier circuit used in an auto-zero sampled data type or auto-zero sampled data type pressure comparator circuit. This amplifier circuit consists of P channel MO8FF1T il and Nf'r
* Connect the input terminal and output terminal of the C-MOS inverter 13 consisting of
MOS FF using S FF1T12! The connection is made through a T-switch circuit 15, and a coupling capacitor 16 is further provided on the input end side of the C-MOS inverter 13. An input signal IN is supplied to the input end of the capacitor t16, and an output signal OUT is output from the C-MOS inverter 73. In addition, the above MOf9 FET switch circuit engineer 15
A signal S of ゛ is supplied to the gate electrode of the N-channel MOS PET 14 constituting the MOS FIT J 4 in order to switch control the MOS PIT J 4, and furthermore, this signal S is supplied to the back gate electrode of the MOS FIT 14. One voltage Vas of the power supply voltage VDD (positive polarity voltage) and the ground voltage v8B (reference magnetic pressure) supplied to the amplifier circuit is supplied. In an amplifier circuit having such a configuration, first, MOS FIT 14
The MO8FBT 14 is turned on by setting the control signal S supplied to the gate electrode of the MO8FBT to the VDD level.

When MOS Fli8T 14 is turned on, C-
The input/output terminal voltage of MOS inverter 13 is set to its circuit threshold voltage, thereby setting the operating point of C-MOB inverter Ijt.

Next, the MOS pg'r J 4 is turned off by setting the signal S to the Y8s level, and in this state, the input signal IN is amplified by the C, -MOS inverter 13.

Such an amplifier circuit has a simple circuit configuration and is suitable for integration, so it has a wide range of applications as a basic amplifier circuit unit. In addition, as an example of applying a voltage comparison circuit based on this principle to an analog-to-digital conversion circuit, for example, "Monoli-th
ic Expandable 6 Bit 2
0 MHz 0MO8/808 A/D Conv
erter” ANDRiW G, F.

DI NGWALL, IEEFi J, So
Day d-8tate Circuit, vol 5C-1
4, pp. 926-932.

See Dec. 1979J.

The analog-to-digital conversion circuit described in the above document requires high-speed conversion characteristics, and therefore the operating speed of the amplifier circuit shown in FIG. 1, which is one of the circuit parts with the slowest operating speed, becomes a problem. It's coming. That is, if the analog-to-digital conversion circuit is to have high-speed conversion characteristics, the MOSFET switch circuit 15 in the amplifier circuit is turned on and the C-MOS inverter 1B is switched on.
It is necessary to shorten the time it takes for the operating point to stabilize. However, in the conventional technology, the MO8FET switch circuit 15 simply uses the MOS PET 14 as a transfer gate, and therefore the ground voltage Vga is supplied to its back gate electrode. Therefore, when the voltage of the input signal IN increases, the MOS FET
The on-resistance of C-MO8 becomes higher, therefore, C-MO8
There is a drawback that it takes a long time until inverter JJ is set to the operating point. Furthermore, since the threshold voltage of MOS FgT varies due to the manufacturing process, in the conventional technology, if the threshold voltage varies toward a higher absolute value, the on-resistance of MO8FIT J4 also increases, and therefore, this In case C-MO8 inverter IB
The drawback is that it takes a long time to set the operating point.

By the way, other conventional techniques for eliminating the above drawbacks include:
MO19F that configures the MOS FET switch circuit
In order to lower the on-resistance of FjT 14, efforts are being made to increase its channel width. However, the MOB F constituting the MO8PIT switch circuit 15
In FtT J 4, leakage of the control signal S occurs between the gate electrode and the source electrode, and between the drain electrode and the drain side due to feed-through, which causes an offset voltage on both sides of the input and output terminals of the C-MOS inverter 13. However, if the channel width of MO8FIT14 is increased, the value of the parasitic capacitance will also increase, and as a result, the offset voltage will also increase. Therefore, M.O.S.
In the conventional technique of increasing the channel width of the FgT 14, the offset-less characteristic, which is one of the most important characteristics for a chopper type or auto-zero sampled data type voltage comparison circuit, is lost. Therefore, it is preferable that the channel axis, that is, the element size of the MO8FIT l 1 used for this Hinoki application is made as small as possible.

On the other hand, when the MO8Fg'r 14 is actually manufactured with the element size minimized, when the VDD level of the control signal 8 supplied to the gate electrode is 5V, the on-resistance is 10K ("
) Not 'L 100 K(') (=It is the energization that reaches it, and especially when the operating point voltage of the C-MOS inverter 13 is about 2.5V, the on-resistance becomes high, and 100K
It is not uncommon for them to reach close range. Therefore, if the element size of MO8PIT J4 is minimized, it will take a long time to set the operating point, making it impossible to realize high-speed operation. Furthermore, as mentioned above, MOS Fg
The threshold voltage of T varies by about ±0.3V due to the manufacturing process, and especially in the case of an N-channel MOSFET, if the threshold voltage varies in the higher direction, the on-resistance will further increase.Nf'r channel MO8FBT ( Q gate electrode J
:: 5. FIG. 4 is a characteristic diagram of input capacitance (voltage supplied to a source electrode or drain capacitor) versus on-resistance when a voltage of OV is supplied. In Figure 2, the on-resistance when the threshold voltage is Vth -1, OV and the input voltage is 2.5V is about 28KO, and when the input voltage is 2.5V, the one with the lower threshold voltage vth If the on-resistance shifts by 0.3v to the higher side, the on-resistance becomes 19KO, and if it shifts by 0.3v to the higher side, the on-resistance becomes 65KO. That is, it can be seen that when the threshold voltage varies by the same value, the rate of increase in the on-resistance is larger when the threshold voltage varies higher than when it varies lower.

[Purpose of the invention]

Therefore, the eyelid of this invention has low on-resistance and
An object of the present invention is to provide a MOS FET switch circuit that can always maintain an on-resistance at a substantially constant value even if the threshold voltage of the MOS FIT varies due to the manufacturing process.

[Summary of the invention]

In the MOS FET switch circuit according to the present invention, the MOS FET switch circuit has a value between the supplied power supply voltage and the ground voltage.
A bias voltage having a value corresponding to the threshold voltage of the MOB FET in the switch is supplied to the generating gate electrode.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a block diagram of a circuit according to an embodiment of the present invention, and parts corresponding to those of the conventional circuit shown in FIG. 1 are given the same reference numerals. In the figure, P-channel MO3FIT J J and N-channel MO8py, Tix constitute a C-MO8 inverter (inverting amplification means) 1, and an N-channel MO8rg'r (M08
A coupling capacitor J6 is provided on the input end side of the C-MOS inverter 1B. An input signal IN is supplied to the input terminal of the capacitor 16, and an output signal OUT is output from the C-MOS inverter 1B.

Also, the above N channel MO! A signal S for controlling the switch of this MO8F'ET 14 is supplied to the gate electrode of 9 PIT J 4. Furthermore, the sources of the P-channel MO8FETxJ and the N-channel MO8FgT 22 are connected between the application points of the voltage VDD% and the ground voltage Vsa applied to the C-MO8 inverter LJ.

The common connection point is a bias voltage output terminal 23, and a P-channel MO8FIiiiT is connected to this bias voltage output terminal 23.
The bias generation circuit 24 is configured by connecting both gate electrodes of the N-channel MOB FF1Tjj and the gate electrodes of the N-channel MOB FF1Tjj. Also, the bias voltage output terminal 23 of the bias generation circuit 24
is connected to the back gate electrode of the N-channel MO8FBT 14.

That is, the embodiment circuit shown in FIG.
Connect with channel MO8FET 14, this MO8FE
A bias voltage higher than the ground voltage Vss is always supplied from the bias generating circuit 24 to the pack gate crossing right of T14.

In the embodiment circuit having the above configuration, the bias generation circuit 24 has a circuit configuration such that the short axis is between the input and output terminals of a C-MOS inverter, so that the voltage at the bias voltage output terminal 23 is as follows (1 ) C-MO which can be expressed by the formula
8 is equal to the circuit threshold voltage V the as an inverter.

Here, Vthp: PTE'r*LEMO8FETxJ(7)L
Threshold voltage V thN: N channel MO8FF
XT 22 LTl threshold voltage and K p
, K N is the drain wax flow ID of P-channel MOf9PIT j 1 and N-channel MO8FIT j j
With a coefficient of 8, . In addition, here, Wp, WN: each channel of P channel MO8FgT j 1 and N channel MO8FEW J 2 - LG), LN: each channel length between P channels 08ki'BT21 and N channel MO8FgT Jj tox: thickness of gate insulating film aox: Permittivity μp of the gate insulating film, μN: Effective mobility of holes and electrons.

As is clear from the above formulas (1) to (3), C-MO8
As the circuit threshold voltage Vtbc as an inverter, that is, the voltage of the bias voltage output terminal 23 of the bias generation circuit 4, P channel MO8FBT21 and N channel MO8PgT, ? By setting the channel width and channel length of j, a voltage having a value between VDD and Vaa can be obtained. That is, the back gate electrode of the N-channel MO8FET 14 serving as the MO8 switch has Va.
A bias voltage greater than or equal to a is supplied, thereby causing this M
The apparent threshold voltage of O8FIiiiT 14 is lower than that of the conventional one, and therefore this MO8F
The on-resistance of FtT J 4 can be made sufficiently lower than that of the conventional one.

Incidentally, considering only the on-resistance, the voltage supplied to the back gate electrode of the MO8FBT JJ is preferably higher, and may be set to the value of vpD itself, but on the other hand, a problem arises in terms of current consumption. This is MO8
N-channel MO8FIT 1 used as a switch
No. 4 (A PN junction is structurally generated between the bank gate electrode and each of the source and drain electrodes, with the P conductive layer on the bank gate electrode side.
T 14 (7) t< Tsukke-) Electrode 1: V D
.

If this is supplied, a current will always flow from the pack gate electrode to the source or drain electrode, resulting in extremely large current consumption.

Therefore, the bias voltage supplied to the pack gate electrode of the N-channel MO8FRT 14 needs to be set to have a value between VDD and Via, taking current consumption into consideration.

moreover! When integrating the circuit shown in Fig. 43, the N-channel MO8 PET14, which is the MO8 switch, and the N-channel MO8FIT 77 in the bias generation circuit 1 are manufactured in the same process, so their respective threshold voltages are set to a predetermined value. It varies in the same direction with respect to the threshold voltage. So, for example, if the threshold voltage of MO8PET J4 varies toward the higher side, and as a result, its on-resistance becomes higher than a predetermined value, then MO8FFtT, ? !
The threshold value ' voltage also varies toward the higher side, and the bias voltage from the bias generation circuit 24 expressed by the above equation (1) becomes higher. Then, since the effective threshold voltage of MOSFET 14 is lowered, the on-resistance of MO8FIT 14 is lowered.

On the other hand, contrary to the above, if the threshold voltage of MO8FgT 14 varies toward the lower side and its on-resistance becomes lower than a predetermined value (although it is preferable for the amplifier circuit to have a lower on-resistance) , MO8FEiT 22
The threshold voltage also varies in the lower direction, and the bias voltage from the bias generation circuit 24 expressed by the above equation (1) becomes lower. Therefore, in this case, since the actual threshold voltage of MO8PET14 is increased, this MO8t
The on-resistance of i'g'r J 4 is increased.

That is, by supplying the Iasumi pressure from the bias generation circuit 24 to the pack gate electrode of the MO8FIT 14, the on-resistance of the MO8FIT J 4 can almost always be kept close to a constant value, and especially when the threshold value It is possible to prevent an increase in the on-resistance of MO8FIT 14 when the voltage becomes high.

FIG. 4 shows MO8FIT 14 in the above embodiment circuit.
2 is a sectional view showing a specific element structure of a portion of a bias generating circuit 14. FIG. In the figure, there are two ! on an Np semiconductor substrate 101. - Well regions Joz and ioz are formed, and in one of the well regions 102 is a source of MO8FIAT14.

A pair of N-type regions 104 and 105 which become drains, and this well region 102, that is, MO8Fi! A t-line region 106 is provided for making contact with the pack gate electrode of TM4. Furthermore, the other P well region 1
01 includes one M that constitutes the bias generation circuit 24.
O8FETJ,? A pair of N+ which becomes the source and drain of
Type territory area 10fl1011 and this town well area 103
A P+ type region 109 is provided for making contact with the substrate 101, and a pair of P type regions 110 and 111 are provided on the substrate 101 to serve as the source and drain of the other MO8PET 21 constituting the IAS generation circuit 24. Then, the pair of N-type regions 104, 105 and the force t
A gate electrode 112 of MO8FF1T 14 is provided, and a signal 8 is supplied to this gate electrode 112.

Moreover, MO8FET! A pair of gate electrodes 111 of 'j): fJ regions 110, 111 are connected to the top of the two sides.
Gate electrodes 114 of O8FIiiTJJ are provided, respectively, and both gate electrodes 113 and 114 are connected to the bias voltage output terminal 23.

Further, the N type region 101 and the Pg region 10 are connected to the output end 23, and the output end 2J is connected to the town.
Connected to mold area 106. Said! The type 1 region 111 is connected to the power supply voltage VDD application point C.

+ The N-type region 108 and the cap region 10G are connected to the ground voltage Van application point.

As in the case of the characteristic diagram shown in FIG. 2, FIG.
The ratio of channel width W to channel length W/L of N-channel MO8FIT 14, which is 8 switches, is set to 6/L on the mask.
7, and the gate electrode is set to 5. Supplying a voltage of Ov,
and P channel M-08FI in bias generation circuit 74
T! 10W/L on 6/42 on mask, N? Yanel MO8Pi! The bias voltage supplied to the back gate electrode of the MOS FBT 14 is set to 35/7 on the w and 'Lt'v screens of i'l' 22 and is approximately 1.2.
It is a characteristic diagram of input pressure vs. on-resistance in the case where it becomes V~1.5v. As is clear from FIG. 5, when the voltage is 2.5 V and the threshold voltage Vth of the MOS PET 14 is 0.7 V, 1. OV.

At 1.3■, Ω and 25KO respectively to 15KO918
The on-resistance value of These values are as described in 11 above.
In the case of the 1g2 diagram, 19KO928Ω is significantly reduced compared to 65XΩ, which means that even if the value voltage varies due to the manufacturing process, the variation in on-resistance is significantly improved compared to the conventional method. . Further, the value of the on-resistance in FIG. 5 is such that the bias voltage ranges from 1.2V to 1.2V.
In the case of 5V, the bias generation circuit is
, N channel MO8FgTJJ, by changing the element size settings of 27', for example 2.0v to 2.
, 5v. Then, by reciting this bias pressure, the above MO8rg'r 1
It is possible to further reduce the on-resistance of No. 4, and to further reduce the influence of variations in threshold voltage. However, as mentioned above, the value of this bias voltage is determined by considering the current consumption. should be determined.

6 to 8 show other embodiments of the present invention, and are configuration diagrams of other examples of the bias generating circuit 24. In FIG. In the one shown in FIG. 6, a constant current source circuit S1 is connected between the VDD application point and the bias voltage output terminal 2J, and a resistor 32 and the MO8PIT 14 are connected between the bias voltage output terminal 2i and the Was application point. Same channel or N channel MOS FITfT J & Dray V
, the sources are connected in series, and this MO8FITJJ
The gate electrode of the bias voltage output terminal 751:ffl is connected to the bias voltage output terminal 751:ffl. In the bias generation circuit having such a configuration, a bias voltage having a value between VDD and Vas is output depending on the output current I of the constant current source circuit 31, the resistance value R of the resistor 32, and the element dimensions of the 1J08FET. Ru. Also, assuming that the resistor S2 does not exist in this circuit, the threshold voltage of MOS FgT 33 is V thN88 , the bias voltage is vO, and the root, I
, Vthss , and the distance between V and r: A proportional equation of the order of magnitude holds true.

Goose Io (K (Vq-Vthai) ---------
--(4) K-biproportional constant The above formula is as follows: When the threshold value of M2S FjilT B 3 'magnetic pressure Vthas becomes ＾, the bias pressure vO also becomes flat; on the other hand, when vthsa becomes low, ■ This shows that 0 is also low. Gakatsu ℃.

Even if we use the bias voltage from this bias generation circuit,
Similarly to the bias generation circuit L4 in the circuit of FIG.
E! M for variations in threshold voltage due to manufacturing process
The on-resistance of the 2S FgT 14 can be kept close to a constant value. Note that the resistor 32 is a MOS PET
It is provided in order to obtain a bias' magnetic pressure vO by adding a constant voltage to the drain-source pressure of 3 J.

In the circuit shown in FIG. 7, a load resistor 41 is connected between the vDD application point and the bias voltage output terminal 23, and the MO8PET is connected between the bias voltage output terminal 23 and the VSS application point.
MOS of the same channel as 14, that is, N channel
The drain and source of i'g'r 42 are connected, and this MO8'E? ? , T42 are connected to the bias voltage output terminal 23. In the bias generation circuit having such a configuration, the load resistor 41
V according to the resistance value of and the confectionery dimensions of M08FFiT4J
A bias voltage having a value between DD and Was is output. In addition, in this circuit, the output bias voltage is Vo', and Vth4 is the threshold voltage of MO8FgT#2.
2, the following proportional equation holds between Vg' and Vth42.

Vo'1K-VthN42 mmm+aa*sm(
5) K': proportionality constant Equation (5) above expresses that the threshold voltage Vth42 of the MOS F3T42 and the bias voltage VO' are proportional. Even if it is used, the on-resistance of the MOS FIiiT 14 can be kept close to a constant value despite variations in threshold voltage due to the manufacturing process.

Incidentally, in both cases of the bias generation circuit shown in FIGS. 6 and 7, the output bias voltage changes depending on the threshold voltage of the N-channel MOS FfiTJJ or 42, but the MOS FFf
If the on-resistance of T14 needs to be simply lowered without considering variations in the threshold voltage, a bias generating circuit as shown in FIG. 8 can also be used.

That is, the circuit shown in FIG.
Two resistors 51 and 52 are connected in series between the B application point and a constant voltage divided according to the resistance ratio of the two resistors si and sir from the bias voltage output terminal 23 which is the series connection point. This is to obtain a bias voltage. Therefore, the bias pressure obtained in this circuit is 1 MO
By supplying the 8F8T14 to the pack gate electrode, the on-resistance of the MOS FIT 14 can be made sufficiently lower than that of the conventional one.

FIG. 9 is a configuration diagram of an applied example circuit of the present invention. This circuit consists of C-MOS inverters 61, 6 for signal inversion and amplification.
2.63 N-channel MOS F for short-circuiting the input and output terminals of each of these inverters to set the operating point
Amplifying circuit L U, 7 consisting of F1iT 64, 65°66 and coupling capacitors 671, 68, 69, respectively.
2.73 are connected in cascade to form an amplifier circuit with a high overall gain.

Also, among the above amplifier circuits, M in the first stage amplifier circuit 77
The bank gate electrode of the OS1HT64 is supplied with a bias voltage Vol from a bias generation circuit 74 configured by shorting the input and output terminals of a C-MOS inverter, and the bias voltage Vol is supplied to the bank gate electrode of the MOS FJiT 65 in the intermediate stage amplifier circuit r2. The gate electrode is supplied with the same bias voltage vo2 from the bias generation circuit 15 (configured by shorting the input and output terminals of a C-MOS inverter), and is further supplied with a MOS FIT 6g pack in the amplifier circuit 73 at the final stage. A bias voltage Vos from a bias generation circuit 76 configured by short-circuiting the input and output terminals of the same < c-yos inverter is supplied to the gate electrode. :I and each bias generation circuit r4.7
For example, if the am voltage VDD supplied to 5.16 is 5.0
In the case of (2), the above bias pressures Vol, Voz, Vow
T'L, T2. OV ~2.5V, 1.5V
~2. OV, 1.2 V ~ 1.5 V
Each bias generation circuit 7/4, 75 .
'The element size ratio within 1g is set. In addition, MOI9F
A control signal 8 is commonly supplied to the gate electrodes of the BTs 64, 65, and 66. In a circuit with such a configuration, the jl1 width circuit on the side closer to the input signal IN handles a signal with a smaller spiral pressure, so the MOS FE for setting the operating point is
It is necessary to increase the operating speed by decreasing the on-resistance value of T. Therefore, by supplying the highest bias voltage to the pack gate electrode of MOf9 FIT 64 in the first stage amplifier circuit Muyu, which is closest to the input signal IN, a voltage comparator circuit that is fast and has offset-less characteristics as a whole is constructed. This is a possible amplifier circuit.

Note that the present invention is not limited to the above embodiment; for example, in FIG. 3, the C-MOS inverter 13
The MOS switch that connects the input and output terminals of
I explained the case of OS FETJ 4, but
For this purpose, a P channel MO8PINT may be used. If a P channel MO8PINT is used, it is necessary to reverse the relationship between the power supply voltage VDD and the ground voltage VBB of each bias generating circuit. Furthermore, if the 808CMO8 process is used, an MO8 switch in which an N-channel MO8i;'g'r 8 J and a P-channel MO8pg'r8z are connected in parallel can be used as the MO8 switch, as shown in Fig. 1θ. In this case, if a C-MO8 inverter whose input terminals are short-circuited is used as the bias generating circuit, the configuration as shown in the figure will be obtained. That is,
The bias generation circuit 83 for applying bias pressure to the pack gate electrode of the N-channel MO8FITII J is as follows:
P channel MO8 between VDD application point and Va8 application point
The FIT 114 and the N-channel MO8FliT s 5 are connected in series, and both gate electrodes are connected to a common drain connection point. On the other hand, P channel M
The bias generation circuit 86 for applying a bias voltage to the back gate electrode of O8FITJIJ is an 88FET.
87 and N-channel MO8FgT 8 B are connected in series, and both gate electrodes are connected to a common drain connection point.

In each of the embodiments or application examples described above, the present invention was applied to a voltage comparison circuit of an analog-to-digital conversion circuit.
An example of application to a capacitor integration circuit (two examples will be explained).

FIG. 11 is a circuit diagram of a switched capacitor integration circuit according to the prior art. That is, this circuit has φ,
MO8Pl at the timing of! :T20) is turned on,
The input signal IN charges the capacitor 202, and then φ
MO8FIT at the timing of snow! Turn on 1 oz to discharge a volume of 2 oz. In other words, two MO8F
ET201.203 acts as a resistive element, and the signal passing through this resistive element is integrated by a circuit consisting of an answer @zgi and an operational amplifier 20. Its detailed operation is described in [J, T., Caves et al. 8ampJed
AfimlOg FiJtering, Uslng
8with Capacitors as
Re5istorIquiva Jerts, Igg
l J of 8oJid-8tata-C4r
See Cuits, Vol. 8C-12, No. 5° Dec., 1977, P592-P599J.

Two MO8s act as resistance elements in this integration circuit.
With FIT II 1 and 203, the resistance becomes a problem. That is, in general, when the on-resistance increases, it means a decrease in the capacitance ratio of the integrating circuit, and the characteristics deteriorate. Therefore, it is preferable that the element dimensions of the two MO8FITII1 and 203 are as large as possible, but as in the case of the voltage comparison circuit, the clock signal due to the parasitic capacitance between the gate and source and between the gate and drain peculiar to MO8Ii'BT is MO8FBT20 because there is a bad influence due to the feedthrough of
The dimensions of 1,20B have to be reduced. Therefore, the first
As shown in Figure 2, the above conventional switched! Applying the present invention to a capacitor divider circuit, a bias voltage Vgl obtained by a bias generation circuit 20g consisting of a channel MO8FBT 206 and an N-channel MO8pg'r 207 is supplied to the back gate electrode of the MO8FET 201,
Also, on the bank gate electrode of MOSFET 205, channel MO8FFfT 209 and N channel MO8
By supplying the bias voltage vg2 obtained from the bias generation circuit 211- consisting of FBtjtlO,
The on-resistance of O8FETs 201 and 205 is reduced, and the light is φ.

The charging and discharging of the charge is completed within the switching period of φ.

Furthermore, the element dimensions of the MO8FETs 201 and 205 can be minimized, and as a result, the influence of feedthrough can be minimized, and high integration can be achieved.

〔Effect of the invention〕

As described above, the present invention provides a MO8FIT switch circuit that has a low on-resistance and can always keep the on-resistance close to a constant value even if the threshold magnetic pressure of the MOSFET varies due to the manufacturing process. can do.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional amplifier circuit, Figure 2 is a MOS F
A characteristic diagram when ET is used as an MO8 switch, FIG. 3 is a configuration diagram of an embodiment of this invention, FIG. 4 is a sectional view specifically showing the element structure of a part of it, and FIG. 5 is a diagram showing the above implementation. Characteristic diagrams of MO8 switch in example circuit, Figures 46 to 8
9 is a block diagram of a bias generation circuit according to another embodiment of the present invention, FIG. 9 is a block diagram of an applied example of the present invention, and FIG. 10 is a block diagram of a modified example of the present invention. FIG. 11 is a block diagram of a conventional bias generating circuit. FIG. 12 is a block diagram of a switched 9-capacitor integrator circuit, which is an example of the application of the present invention to a switched capacitor integrator circuit. 11 , 21 t, 8 j , 84 , 87...@
ri f Yanenel O8FIT, 12, 14, 2: l, 3B
, 42°64.65, 66.81, 115.88...
N-channel MO8FET, 1B, 61, 62.63...
・C-MOS inverter, 16,61,611.69
86...Bias generation circuit, 3rd item...Constant current source circuit, 32.51.52...Resistor, 4th item...Load resistance. Applicant Representative Patent Attorney Takehiko Suzue No. 101! I Vo. Vrel Vref Figure 12 199

Claims (1)

[Scope of Claims] (1) A MOS switch consisting of at least one MOS FIT having a gate electrode and a pack gate electrode, and a MOS switch in the MO8 switch which has a value between the supplied power supply voltage and a reference voltage and has a value between the supplied power supply voltage and the reference voltage. Fj! bias generating means for generating a bias voltage having a value corresponding to the threshold voltage of T;
An MO8FBT switch circuit characterized in that it comprises means for supplying a pack gate electrode of an SFBT. (2) The bias generating means is an MO8FiilT on the same channel as the MOS FIT in the MOS switch.
MOS F according to claim 1 comprising
ET switch circuit. . 2. The MOS rg'r switch circuit according to claim 1, wherein the primary bias generation means is constructed by short-circuiting the input and output terminals of complementary MOS inverters consisting of MOS FITs of different channels. (4) The bias generating means is a constant current generating means inserted between the power supply voltage application point or the reference voltage application point and the bias voltage output terminal, and the gate electrode is connected to the bias voltage output terminal. and a MOSFET in the MOS switch inserted between the bias voltage output terminal and the reference voltage application point or the power supply voltage application point.
2. The MOS FET switch circuit according to claim 1, comprising: and a MOS PET of the same channel. (5) The bias generating means includes a load resistor inserted between the power supply voltage application point or the reference voltage application point and the bias voltage output terminal, and a gate electrode connected to the bias voltage output terminal, and the bias voltage Claim 1, wherein the MOS FjitT in the MOS switch inserted between the output end and the reference voltage application point or the power supply voltage application point is composed of a MOS FjitT of the same channel. MO8PET switch circuit. (6) The MOS FET switch circuit according to claim 181, wherein the 1ifJ e M O8 switch is composed of one single channel MOS FgT. (7) The MOS FET switch circuit according to claim 1, which is constituted by two MOS FETs of different channel types to which the first MO8 switch is connected in parallel.