JP4245102B2 - Threshold detection circuit, threshold adjustment circuit, and square circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a threshold detection circuit, a threshold adjustment circuit, and a square circuit.
[0002]
[Prior art]
Conventionally, a multiplication circuit that receives an analog signal and multiplies the input analog signal is known.
[0003]
FIG. 4 is a circuit diagram of a conventional multiplication circuit.
[0004]
4 includes an input terminal 411 to which an analog voltage vd on which a DC voltage Vd is superimposed is input, two NMOS transistors 412 and 413 each having one end commonly connected to the input terminal 411, and Input terminals 414 and 415 connected to the gates of the NMOS transistors 412 and 413 are provided. An analog voltage vg on which a DC voltage Vg is superimposed is input to the input terminal 414, and a DC voltage Vg is input to the input terminal 415.
[0005]
In addition, the multiplication circuit 400 includes current voltage conversion circuits 416 and 417 each having one input side connected to each other end of the NMOS transistors 412 and 413, and the other input side of each of the current voltage conversion circuits 416 and 417. And an input terminal 418 connected in common. The current-voltage conversion circuit 416 includes an operational amplification circuit 416a and a resistance element 416b, and the current-voltage conversion circuit 417 includes an operational amplification circuit 417a and a resistance element 417b. The DC voltage Vd is input to the input terminal 418.
[0006]
Further, the multiplication circuit 400 includes a subtraction circuit 419 whose input side is connected to the output side of the current-voltage conversion circuits 416 and 417, and an output terminal 420 connected to the output side of the subtraction circuit 419.
[0007]
In the multiplication circuit 400 configured as described above, when the analog voltage vg is a positive voltage value, the current I flowing in the saturation region of the NMOS transistors 412 and 413 is obtained.₁, I₂Is expressed as follows.
[0008]
I₁= Β₁{(Vg + vg-Vd-Vt₁) Vd + vd²/ 2}
I₂= Β₂{(Vg-Vd-Vt₂) Vd + vd²/ 2}
However, β₁, Β₂Is a constant determined by the process (channel width W, channel length L, carrier movement, etc.), Vt₁, Vt₂Is a threshold value of the NMOS transistors 412 and 413.
[0009]
Here, if the resistance elements 416b and 417b constituting the current-voltage conversion circuits 416 and 417 are 1Ω, the voltages v1 and v2 output from the current-voltage conversion circuits 416 and 417 are
v1 = Vd-I₁
v2 = Vd-I₂
It becomes. Therefore, the gain of the subtraction circuit 419 is set to 1, and β₁= Β₂, Vt₁= Vt₂Then, the voltage v0 of the output terminal 420 is
v0 = β₁vgvd
It becomes. In this way, the multiplication circuit 400 shown in FIG. 4 multiplies the input analog voltage vg and analog voltage vd. Here, when the values of the input analog voltage vg and analog voltage vd are the same, a square circuit is realized.
[0010]
Even when the analog voltage vg is a negative voltage value, the input analog voltage vg and the analog voltage vd are multiplied in the same manner as in the case where the analog voltage vg is a positive voltage value.
[0011]
However, it is difficult to manufacture the two NMOS transistors 412 and 413 constituting the multiplication circuit 400 with the same characteristics such as the transistor size and the threshold value indicating the channel width W, the channel length L, and the like. β₁= Β₂, Vt₁= Vt₂Therefore, there is a problem that it is difficult to perform multiplication with high accuracy.
[0012]
Japanese Patent Publication No. 63-46474 proposes a multiplication circuit that performs multiplication of an analog signal using one NMOS transistor.
[0013]
FIG. 5 is a circuit diagram of a multiplication circuit proposed in Japanese Patent Publication No. 63-46474.
[0014]
The same components as those of the multiplication circuit 400 shown in FIG.
[0015]
In the multiplication circuit 500 shown in FIG. 5, the input terminals 411 and 418, the NMOS transistor 412, the current-voltage conversion circuit 416, the subtraction circuit 419, and the output terminal 420 are connected in common to the gate of the NMOS transistor 412. In addition, switches 511 and 512 connected to an input terminal 414 to which an analog voltage vg on which a DC voltage Vg is superimposed are input are input to an input terminal 415 to which a DC voltage Vg is input.
[0016]
In addition, the multiplication circuit 500 has switches 513 and 514 each having one end commonly connected to the output side of the current-voltage conversion circuit 416, an input side connected to the other end of the switches 513 and 514, and an output side of the subtraction circuit 419. Sample hold circuits 515 and 516 connected to the input side are provided.
[0017]
In the multiplication circuit 500, first, the switches 511 and 512 are turned on and off by switch switching means (not shown), and the switches 513 and 514 are also turned on and off. Then, the current I / V conversion circuit 416 is connected to the current I via the NMOS transistor 412.₁, And the voltage v1 subjected to current-voltage conversion by the current-voltage conversion circuit 416 is output. This voltage v1 is held in the sample hold circuit 515 via the switch 513. Next, the switches 511 and 512 are switched to the off state and the on state, and the switches 513 and 514 are also switched to the off state and the on state, and the current I is converted to the current-voltage conversion circuit 416 via the NMOS transistor 412.₂The voltage v2 is output from the current-voltage conversion circuit 416. This voltage v2 is held in the sample hold circuit 516 via the switch 514. These voltages v1 and v2 are input to the subtraction circuit 419, and the voltage v0 (β is output from the subtraction circuit 419 to the output terminal 420 in the same manner as described with reference to FIG.₁vgvd) is output. Since this voltage v0 is obtained by using one NMOS transistor 412, a multiplication result can be obtained with higher accuracy than when two MOS transistors having different sizes and characteristics are used. .
[0018]
[Problems to be solved by the invention]
However, in the above-described multiplication circuit 500, in order to increase the accuracy of the multiplication result, it is necessary to ensure a wide non-saturation region of the NMOS transistor 412, and thus there is a problem that a high power supply voltage is required.
[0019]
In Japanese Patent Publication No. 4-50633, a depletion type MOS transistor is used in order to avoid the harmonic distortion caused by the enhancement type MOS transistor and the complication of the configuration accompanying the application of a bias voltage. Multiplication circuits have been proposed. However, this multiplication circuit has a problem that many steps are required for manufacturing a depletion type MOS transistor.
[0020]
Further, Japanese Patent Publication No. 1-59622 and Japanese Patent Publication No. 2-52307 propose a multiplication circuit using a capacitor element instead of a resistance element that requires a relatively large area and power consumption for integration. ing. However, in general, the capacitance accuracy of the capacitor element is low, and there is a problem that a special process is required to increase the capacitance accuracy of the capacitor element.
[0021]
Japanese Patent Publication No. 5-42033 and US Patent (Patent No. 4585961) propose a squaring circuit using a saturation region of a MOS transistor. However, in the techniques proposed in these publications, there is a problem that a relatively high power supply voltage is required because three MOS transistors are connected in series between the power supply voltage and the ground in the input stage. is there.
[0022]
In view of the circumstances described above, an object of the present invention is to provide a threshold detection circuit, a threshold adjustment circuit, and a squaring circuit suitable for a squaring circuit capable of obtaining a highly accurate multiplication result with a relatively low power supply voltage. To do.
[0023]
[Means for Solving the Problems]
The threshold detection circuit of the present invention that achieves the above object is
(1_1) A first constant current circuit for flowing a first current according to a predetermined reference voltage
(1_2) a second current that is connected in series to the first constant current circuit and causes a second current having a current value higher than the first current by an amount that can be allowed as a detection error in accordance with the reference voltage. Constant current circuit
(1_3) Provided with a first MOS transistor for detecting a threshold value, which is diode-connected in parallel to the first constant current circuit and flows a difference current between the second current and the first current. It is characterized by that.
[0024]
In addition, the threshold adjustment circuit of the present invention that achieves the above object is
(2_1) A first constant current circuit for flowing a first current according to a predetermined reference voltage
(2_2) a second current which is connected in series to the first constant current circuit and causes a second current having a current value higher than that of the first current by an allowable level as compared to the first current to flow according to the reference voltage. Constant current circuit
(2_3) A first MOS transistor that is diode-connected in parallel to the first constant current circuit and flows a difference current between the second current and the first current
(2_4) Substrate bias for adjusting the substrate bias voltage of the first MOS transistor so that the voltage of the node to which the first constant current circuit and the second constant current circuit are connected is equal to the reference voltage. A voltage adjustment circuit is provided.
[0025]
Furthermore, the squaring circuit of the present invention that achieves the above object is
(3_1) A first constant current circuit for flowing a first current according to a predetermined reference voltage
(3_2) a second current which is connected in series to the first constant current circuit and causes a second current having a current value higher than that of the first current by an allowable level as compared to the first current to flow according to the reference voltage. Constant current circuit
(3_3) A first MOS transistor which is diode-connected in parallel with the first constant current circuit and flows a current difference between the second current and the first current
(3_4) Substrate bias for adjusting the substrate bias voltage of the first MOS transistor so that the voltage of the node to which the first constant current circuit and the second constant current circuit are connected is equal to the reference voltage. Voltage adjustment circuit
(3_5) a second MOS that is adjusted to the same substrate bias voltage as the substrate bias voltage of the first MOS transistor by the substrate bias voltage adjusting circuit, in which an input voltage is input to the gate and a current corresponding to the input voltage is supplied. A transistor is provided.
[0026]
The present invention has been made paying attention to the current characteristics in the saturation region of a MOS transistor. For example, in the case of an NMOS transistor, the current I in the saturation region is
I = β / 2 (Vgs−Vt)²        ... (A)
Can be expressed as Where β is a constant determined by the process, Vgs is the gate-source voltage of the NMOS transistor, and Vt is the threshold value of the NMOS transistor. Here, when Vt is obtained by passing a minute current through the NMOS transistor and the obtained Vt is adjusted to 0, for example, the above-described equation (A) is
I∝Vgs²        ... (B)
It becomes. If such a current I is converted into a voltage, Vgs²A voltage proportional to is obtained.
[0027]
The threshold value detection circuit of the present invention is configured to flow a difference current between the second current and the first current as a level allowable as a detection error to the first MOS transistor. By making the current sufficiently small, the threshold value of the first MOS transistor can be obtained.
[0028]
Further, the threshold adjustment circuit of the present invention is configured so that the voltage of the node to which the first constant current circuit and the second constant current circuit are connected in the substrate bias voltage adjustment circuit is equal to the reference voltage. Since the substrate bias voltage of the first MOS transistor is adjusted, the threshold value of the first MOS transistor can be adjusted with the reference voltage.
[0029]
Furthermore, the square circuit of the present invention includes a second MOS transistor that is adjusted to the same substrate bias voltage as that of the first MOS transistor by the substrate bias voltage adjusting circuit, and is provided at the gate of the second MOS transistor. Since the input voltage is input and a current corresponding to the input voltage is passed, if the second MOS transistor is an NMOS transistor, for example, the current I in the saturation region of the NMOS transistor is:
I = β / 2 (Vin−Vref)²        ... (C)
Can be expressed as However, Vin is an input voltage that is input to the gate of the NMOS transistor and is substituted for the gate-source voltage Vgs in the above-described equation (A). Vref is a reference voltage in place of the threshold value Vt of the NMOS transistor in the above-described equation (A). Here, when Vref is adjusted to 0, for example, the above-described equation becomes
I∝Vin²
It becomes. If such a current I is converted into a voltage, a voltage proportional to the square of the input voltage Vin inputted can be obtained.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0031]
FIG. 1 is a circuit diagram of a threshold detection circuit according to the first embodiment of the present invention.
[0032]
The threshold detection circuit 110 shown in FIG. 1 includes a PMOS transistor 111 and an NMOS transistor 112 connected in series between the power supply voltage Vdd and the ground GND, and a predetermined reference voltage Vref connected to the gate of the NMOS transistor 112. An input terminal 116 for inputting is provided.
[0033]
The threshold detection circuit 110 has a gate connected to the input terminal 116 and a first current I corresponding to the reference voltage Vref input to the input terminal 116.₁NMOS transistor 113 (corresponding to the first constant current circuit referred to in the present invention) is provided.
[0034]
Further, the threshold detection circuit 110 is connected in series to the NMOS transistor 113 and is connected to the first current I according to the reference voltage Vref.₁The second current I has a current value that is higher than the level that can be tolerated as a detection error.₂PMOS transistor 114 (corresponding to the second constant current circuit referred to in the present invention) is provided. The gate of the PMOS transistor 114 is connected to the gate of the PMOS transistor 111 and the connection point between the PMOS transistor 111 and the NMOS transistor 112.
[0035]
The threshold detection circuit 110 has a second current I that is diode-connected in parallel with the NMOS transistor 113 and connected to the output terminal 117.₂And the first current I₁Difference current I from_dsNMOS transistor 115 (corresponding to the first MOS transistor according to the present invention) for detecting a threshold value is provided. Here, the transistor size ratio of the PMOS transistor 111, the NMOS transistors 112, 113, and 115 and the PMOS transistor 114 is 1: 1 + α (α is about 1 to 10%).
[0036]
A predetermined reference voltage Vref is input to the input terminal 116 of the threshold detection circuit 110 configured as described above. Then, the NMOS transistors 112 and 113 are turned on. Since the NMOS transistor 112 is turned on, the gate potentials of the PMOS transistors 111 and 114 are lowered, and the PMOS transistors 111 and 114 are turned on. The PMOS transistors 111 and 114 correspond to a size ratio of 1: 1 + α. Current flows. In other words, the PMOS transistor 111 has a current I commensurate with the size ratio 1 in the path of the power supply voltage Vdd → the PMOS transistor 111 → the NMOS transistor 112 → the ground GND._ThreeFlows. On the other hand, the PMOS transistor 114 has a current I flowing through the NMOS transistor 113 that is turned on by the reference voltage Vref input to the gate.₁And the current I flowing through the NMOS transistor 115 connected in parallel to the NMOS transistor 113_dsAnd current I commensurate with the size ratio (1 + α)₂Flows.
[0037]
Here, the current I flowing through the NMOS transistor 115 is connected to the output terminal 117._dsTherefore, the gate-source voltage Vgs in the saturation region of the NMOS transistor 115 is output. This voltage Vgs is
Vgs = Vt + (2I_ds/ Β)^1/2
It can be expressed as. However, β is a constant determined by the process, and Vt is a threshold value of the NMOS transistor 115. Where the current I_dsIs a sufficiently small current that is acceptable as a detection error, so the voltage Vgs is
Vgs≈Vt
It becomes. In this way, the threshold value Vt of the NMOS transistor 115 is detected. Next, a square circuit that squares and outputs an input analog voltage using the threshold value Vt will be described.
[0038]
FIG. 2 is a circuit diagram of the squaring circuit of the first embodiment of the present invention.
[0039]
In the squaring circuit 100 shown in FIG. 2, the voltage at the node where the threshold detection circuit 110 shown in FIG. 1 and the NMOS transistor 113 and the PMOS transistor 114 constituting the threshold detection circuit 110 are connected is a reference voltage. An operational amplifier 121 (corresponding to the substrate bias voltage adjusting circuit in the present invention) for adjusting the substrate bias voltage of the NMOS transistor 115 so as to be equal to Vref is provided. A threshold adjustment circuit 120 is configured by the threshold detection circuit 110 and the operational amplifier 121.
[0040]
The square circuit 100 also has an input terminal 131 to which an input voltage vin higher than the reference voltage Vref is input, and a gate connected to the input terminal 131 and a current according to the input voltage vin input to the gate. , An NMOS transistor 132 (second MOS transistor according to the present invention) adjusted to the same substrate bias voltage as that of the NMOS transistor 115 by the operational amplifier 121 is provided.
[0041]
Further, the squaring circuit 100 includes a PMOS transistor 133 disposed between the power supply voltage Vdd and the NMOS transistor 132, a gate connected to the gate of the PMOS transistor 133, and a connection point between the NMOS transistor 132 and the PMOS transistor 133. PMOS transistor 134, a resistance element 135 disposed between the PMOS transistor 134 and the ground GND, and an output terminal 136 connected to a connection point between the PMOS transistor 134 and the resistance element 135 are provided.
[0042]
The reference voltage Vref and the input voltage vin are input to the input terminals 116 and 131 of the squaring circuit 100 configured as described above. Then, the voltage (threshold value Vt) of the node where the NMOS transistor 113 and the PMOS transistor 114 are connected is input to the positive phase input of the operational amplifier 121, and the reference voltage Vref is input to the negative phase input. In the operational amplifier 121, an adjustment voltage is output from the operational amplifier 121 toward the back gate of the NMOS transistor 115 so that the voltage of the node becomes equal to the reference voltage Vref, and thereby the substrate bias voltage of the NMOS transistor 115 is adjusted. .
[0043]
Further, the input voltage vin is input to the gate of the NMOS transistor 132, and the adjustment voltage from the operational amplifier 121 is also input to the back gate of the NMOS transistor 132, whereby the NMOS transistor 132 is turned on. Then, the potential at the connection point between the PMOS transistor 133 and the NMOS transistor 132 is lowered, the PMOS transistor 133 is turned on, and a current flows through the path of the power supply voltage Vdd → the PMOS transistor 133 → the NMOS transistor 132 → the ground GND. Further, the PMOS transistor 134 is also turned on, and a current flows through the path of the power supply voltage Vdd → the PMOS transistor 134 → the resistance element 135 → the ground GND. Here, if the current flowing through the PMOS transistor 134 is I, the current I is
I = β / 2 (vin-Vref)²      ... (1)
It is expressed as Here, when the value R of the resistance element 135 is 2 / β, the voltage vo of the output terminal 136 is
v0 = (vin-Vref)²          ... (2)
It is expressed as Furthermore, if Vref = 0, equation (2) is
v0 = (vin)²                    ... (3)
It is expressed as In this way, a voltage v0 obtained by squaring the input voltage vin is obtained.
[0044]
As described above, in the squaring circuit 100 of the present embodiment, the operational amplifier 121 adjusts the substrate bias voltage of the NMOS transistor 115 so that the threshold value Vt in the saturation region of the NMOS transistor 115 becomes equal to the reference voltage Vref. The NMOS transistor 132 to which the input voltage vin is input is also adjusted to the substrate bias voltage to obtain the voltage v0 obtained by squaring the input voltage vin expressed by the above equation (3). A relatively low power supply voltage compared to the technology that expands the non-saturation region by applying a high power supply voltage to improve the accuracy of the result, or the technology in which three MOS transistors are connected in series between the power supply voltage and the ground in the input stage. Gives a highly accurate multiplication result.
[0045]
FIG. 3 is a circuit diagram of a squaring circuit according to the second embodiment of the present invention.
[0046]
In the above-described squaring circuit 100 of the first embodiment, the example using the threshold value Vt of the NMOS transistor has been described, but in the present embodiment, the example using the threshold value Vt of the PMOS transistor will be described. The threshold detection circuit 210 constituting the squaring circuit 200 shown in FIG. 3 is connected to the PMOS transistor 212 and the NMOS transistor 211 connected in series between the power supply voltage Vdd and the ground GND, and to the gate of the PMOS transistor 212. An input terminal 216 to which a predetermined reference voltage Vref is input is provided. The first current I corresponding to the reference voltage Vref input to the input terminal 216 is connected to the gate of the input terminal 216.₁PMOS transistor 213 (corresponding to the first constant current circuit referred to in the present invention) is provided. Further, the first current I is connected in series to the PMOS transistor 213 in accordance with the reference voltage Vref.₁The second current I has a current value that is higher than the level that can be tolerated as a detection error.₂NMOS transistor 214 (corresponding to the second constant current circuit referred to in the present invention) is provided. The gate of the NMOS transistor 214 is connected to the gate of the NMOS transistor 211 and the connection point between the PMOS transistor 212 and the NMOS transistor 211. The second current I is diode-connected in parallel with the PMOS transistor 213.₂And the first current I₁Difference current I from_sdPMOS transistor 215 for threshold detection (corresponding to the first MOS transistor in the present invention) is provided. Here, the transistor size ratio of the PMOS transistors 212, 213, 215, the NMOS transistor 211, and the NMOS transistor 214 is 1: 1 + α (α is about 1 to 10%).
[0047]
In the squaring circuit 200, the substrate bias voltage of the PMOS transistor 215 is adjusted so that the voltage at the node where the PMOS transistor 213 and the NMOS transistor 214 constituting the threshold detection circuit 210 are connected is equal to the reference voltage Vref. An operational amplifier 221 (corresponding to a substrate bias voltage adjusting circuit according to the present invention) is provided. Note that a threshold adjustment circuit 220 is constituted by the threshold detection circuit 210 and the operational amplifier 221.
[0048]
Furthermore, an input terminal 231 to which an input voltage vin lower than the reference voltage Vref is input, and a current corresponding to the input voltage vin input to the gate is supplied to the input terminal 231 through the square circuit 200. The PMOS transistor 232 (second MOS transistor according to the present invention) adjusted to the same substrate bias voltage as that of the PMOS transistor 215 by the operational amplifier 221 and the NMOS transistor arranged between the PMOS transistor 232 and the ground GND 233 is provided.
[0049]
The squaring circuit 200 includes an NMOS transistor 238 having a gate connected to the gate of the NMOS transistor 233 and connected to a connection point between the PMOS transistor 232 and the NMOS transistor 233, and between the NMOS transistor 238 and the power supply voltage Vdd. A PMOS transistor 237 is provided. Further, a PMOS transistor 234 having a gate connected to the gate of the PMOS transistor 237 and connected to a connection point between the PMOS transistor 237 and the NMOS transistor 238, a resistance element 235 disposed between the PMOS transistor 234 and the ground GND, An output terminal 236 connected to a connection point between the PMOS transistor 234 and the resistance element 235 is provided.
[0050]
The reference voltage Vref and the input voltage vin are input to the input terminals 216 and 231 of the squaring circuit 200 configured as described above. Then, the PMOS transistors 212 and 213 are turned on. Since the PMOS transistor 212 is turned on, the gate potentials of the NMOS transistors 211 and 214 rise, the NMOS transistors 211 and 214 are turned on, and the current I_ThreeFlows. On the other hand, the NMOS transistor 214 has a current I flowing through the PMOS transistor 213 turned on by the reference voltage Vref input to the gate.₁Current I flowing through the PMOS transistor 215 connected in parallel to the PMOS transistor 213_sdAnd the current I₂Flows. Where the current I_sdIs a sufficiently small current that can be tolerated as a detection error. Therefore, the threshold value Vt of the PMOS transistor 215 is detected in the same manner as the threshold value detection circuit 110 shown in FIG.
[0051]
This threshold value Vt is input to the positive phase input of the operational amplifier 221. The reference voltage Vref is input to the negative phase input of the operational amplifier 221. In the operational amplifier 221, an adjustment voltage is input from the operational amplifier 221 to the back gate of the PMOS transistor 215 so that the threshold value Vt becomes equal to the reference voltage Vref, thereby adjusting the substrate bias voltage of the PMOS transistor 215.
[0052]
The input voltage vin is input to the gate of the PMOS transistor 232, and the adjustment voltage from the operational amplifier 221 is input to the back gate of the PMOS transistor 232, whereby the PMOS transistor 232 is turned on. As a result, the potential at the connection point of the NMOS transistors 233 and 238 rises, and the NMOS transistors 233 and 238 are turned on. Accordingly, the PMOS transistors 237 and 234 are also turned on. → Current I flows through the path of resistance element 235 → ground GND. The voltage vo = (vin) based on the current I is applied to the output terminal 236 in the same manner as in the case of the squaring circuit 100 shown in FIG.²That is, a voltage v0 obtained by squaring the input voltage vin is output.
[0053]
As described above, in the squaring circuit 200 of the second embodiment, the operational amplifier 221 adjusts the substrate bias voltage of the PMOS transistor 215 so that the threshold value Vt in the saturation region of the PMOS transistor 215 becomes equal to the reference voltage Vref, and the input Since the PMOS transistor 232 to which the voltage vin is input is also adjusted to the substrate bias voltage to obtain the voltage v0 obtained by squaring the input voltage vin, a highly accurate multiplication result can be obtained with a relatively low power supply voltage. It is done.
[0054]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a threshold detection circuit, a threshold adjustment circuit, and a squaring circuit suitable for a squaring circuit that can obtain a highly accurate multiplication result with a relatively low power supply voltage. Can do.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a threshold detection circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram of a squaring circuit according to the first embodiment of the present invention.
FIG. 3 is a circuit diagram of a squaring circuit according to a second embodiment of the present invention.
FIG. 4 is a circuit diagram of a conventional multiplication circuit.
FIG. 5 is a circuit diagram of a multiplication circuit proposed in Japanese Patent Publication No. 63-46474.
[Explanation of symbols]
100,200 square circuit
110, 210 Threshold detection circuit
111, 114, 133, 134, 212, 213, 215, 232, 234, 237 PMOS transistor
112, 113, 115, 132, 211, 214, 233, 238 NMOS transistor
116, 131, 216, 231 Input terminal
117, 136, 236 output terminals
120,220 Threshold adjustment circuit
121,221 operational amplifier
135,235 Resistance element

Claims (3)

A first constant current circuit for flowing a first current according to a predetermined reference voltage;
A second constant current circuit connected in series to the first constant current circuit and supplying a second current having a current value higher than that of the first current by an allowable level as a detection error in accordance with the reference voltage. When,
A first MOS transistor for detecting a threshold value, which is diode-connected in parallel to the first constant current circuit and flows a difference current between the second current and the first current; A threshold detection circuit characterized by the above. A first constant current circuit for flowing a first current according to a predetermined reference voltage;
A second constant current circuit connected in series to the first constant current circuit and supplying a second current having a current value higher than that of the first current by an allowable level as a detection error in accordance with the reference voltage. When,
A first MOS transistor that is diode-connected in parallel to the first constant current circuit and that flows a difference current between the second current and the first current;
A substrate bias voltage adjustment circuit for adjusting a substrate bias voltage of the first MOS transistor so that a voltage of a node to which the first constant current circuit and the second constant current circuit are connected is equal to the reference voltage. And a threshold adjustment circuit. A first constant current circuit for flowing a first current according to a predetermined reference voltage;
A second constant current circuit connected in series to the first constant current circuit and supplying a second current having a current value higher than that of the first current by an allowable level as a detection error in accordance with the reference voltage. When,
A first MOS transistor that is diode-connected in parallel to the first constant current circuit and that flows a difference current between the second current and the first current;
A substrate bias voltage adjustment circuit for adjusting a substrate bias voltage of the first MOS transistor so that a voltage of a node to which the first constant current circuit and the second constant current circuit are connected is equal to the reference voltage. When,
An input voltage is input to the gate and a current corresponding to the input voltage flows, and the second MOS transistor adjusted to the same substrate bias voltage as the substrate bias voltage of the first MOS transistor by the substrate bias voltage adjustment circuit. A square circuit characterized by comprising.

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