JPS58139563A - Facsimile device - Google Patents

Abstract

PURPOSE:To reduce greatly the deterioration of a received picture quality owing to a defect of circuit characteristics, by transmitting and receiving a circuit state checking signal to check whether the correct reception is possible or not and then changing the transmission system. CONSTITUTION:A jumping over checking signal is used to check an error by which a jumping over signal is regarded as a picture signal; and a black ghost checking signal is used to check an error by which a picture disturbance checking signal and the picture signal are regarded as jumping over signals. When the result of decision is satisfactory with both of these checking signals, the pictures are transmitted bythe 1st picture transmitting method having a high speed. While the 2nd picture transmitting method which reduces the picture disturbance is used when the result of decision is unsatisfactory with the jumping over checking signal and satisfactory and rather satisfactory with the black ghost checking signal respectively. If the result of decision is unsatisfactory with the black ghost checking signal, the circuit is cut off by deciding the end of error for the facsimile transmitter and receiver before an original is transmitted.

Description

[Detailed description of the invention]

The present invention provides an analog facsimile apparatus that performs high-speed transmission using a redundancy suppression method, in which a redundancy suppression signal sent from a facsimile receiver is transmitted to the facsimile receiver side.
The present invention relates to a facsimile machine having a function of checking whether reception can be performed correctly. Traditionally, facsimile machines that check the line status and change the transmission speed or transmission method are T, 0OITT,
The Gl standard facsimile (digital method) defined by the 4 Recommendations is well known. In these devices, prior to high-speed image transmission, the automatic equalizer on the receiver side is adjusted to suit the line characteristics using a training signal and a training check signal, and the adjustment results are The transmission rate and transmission method are determined based on the determination. If the automatic equalizer cannot be completely adjusted, an error occurs and the line 'IIJ1 (line is cut off)' is designed. Such facsimile numbers inevitably cost more, so they are sold as so-called high-priced or high-end machines. On the other hand, the Gl facsimile (analog system) specified by the 0OITT T, 3 Recommendation is known as a low-cost, mid-range machine. However, the time when transmission is poor is 01
Since you need about three times as much as one phone, you end up paying only one phone fee. Therefore, facsimile machines, which are as expensive as GLL facsimiles and have transmission speeds comparable to high-end machines, are widely used as analog high-speed machines. An example of a conventional analog high-speed transmission system and how image deterioration occurs due to poor line characteristics will be described below. An outline of the first image transmission method configured to control the amount of image transmission according to the black and white information of the 1', tl+1 image will be explained. The transmitter transmits one line of u1 read from the scanner.
++ Divide the elementary signal string L bits into M blocks. The number of pixels in one block is N and the deviation is LM〆N. However, M and N are integers. Next, the pixels included in each block are checked, and if one block is composed entirely of white signals, the pixel signal is changed to an N-bit pixel signal, and an interlaced signal composed of n bits is modulated and sent out. , if the pixel signal of l block contains l1111 black pixels of l bits or more, the pixel signal -υ of N hits is sent out as it is by changing zh L. where N)n, and 11.
If 11 is an integer, the bit configuration is 1 so that N=aXn. Here, it is desirable that n ) ]. The reason is Hietsu Haku publication number:

[AM-PM- which has an important meaning in the Japanese method and is an analog transmission method
This is because in the VSII and AM-118B/J systems, the error rate is large, so when n=1, it is very difficult to obtain a normal received image during actual transmission. In addition, a synchronization signal of 4' from l bit is added to the 511 heads of each line. It is configured to be a common multiple of /-4jn. Therefore, t>n. 1
The signal pattern is n-hit long such that a zero amplitude of the image signal exists after successive signals with an amplitude larger than the maximum amplitude included in the IIII signal (hereinafter referred to as high-level signal), and the synchronization signal is After the high 1/Bell count of ni1 continues longer than the skipping signal, iI! Let + be a signal pattern of l bit length such that zero amplitude of the signal exists. With the above configuration, the transmitter sends out a synchronization signal consisting of the l bits at the beginning of each line, and then sends out an image in which an interlaced signal exists at the position of a white block in the pixel signal. Information signals are sequentially modulated and transmitted. At the receiver, the received signals that arrive sequentially are rear-ended to create a baseband signal, the amplitude of this baseband signal is measured, and the ri! 11 signals and synchronization/jumping signals. Next, the duration of the high level signal (the time until the cold level signal appears) is checked to distinguish between the synchronous signal and the skipping signal. Furthermore, the receiver is configured to distinguish between the interlaced signal and the image signal at the timing when the D-th bit signal is received counting from the time when the synchronization signal is detected. Next, the transmission signal of the first image transmission method will be explained in more detail using the drawings. FIG. 1 shows the structure of a transmitted signal. FIG. 1(a) shows a one-line image signal sequence, which is represented by two signals of white and black. One line is 256 bits, and one block is 64 bits. Therefore, one line is divided into four blocks. If only the third block contains a black signal, the transmission signal is sent out as a signal as shown in FIG. 1(b). That is, a synchronization signal is sent out prior to the start of sending out one line. Since the first block is an all-white block, a skip signal is sent. Since the second block is also a blank block, a skip signal is subsequently sent. Since the third block contains a black signal, both signals are sent out as they are, but only when the block in front of it is an interlaced signal, a guard band signal is inserted just before the picture signal. This guard band signal is a signal for preventing the ringing at the trailing end of the interlaced signal waveform having the amplitude of the voltage doubler from exerting a force on the starting end of the subsequent picture signal waveform. Following the guard band signal 7, both 64-bit signals of the third block are sequentially transmitted i11. Since the fourth block is an all-white block, an interlaced signal is sent, and the transmission for one line is eavesdropped. FIG. 2 shows the configuration of the above-mentioned synchronization signal, Jump No. 18, and guard band signal. In this embodiment, the synchronization signal first consists of 46 bits of high level No. 14, followed by 5 bits of black signal, and 5 bits of white signal, as shown in Fig. 2(,), for a total of 56 hits. Consists of. On the other hand, the interlaced signal is composed of a total of 8 bits (1, 1, 1, 2, 6 bits for the high level signal and 1 for every 2 bits for the black signal, as shown in the figure in 2L1(b). Also, the card band signal (
As shown in Figure 1 (c) of J11, the black signal is 3 bits,
The white signal consists of a total of 8 bits of 5 bits. In this example, 'lj is 774 for the delivery speed.
(Since it is l b ps, the high level duration time of the same 1 signal is 11.5943 μs, and the high level duration time of the interlaced signal is −775 μs. Next, the receiver side of the first image transmission method described above. The configuration and its operation will be explained below using specific examples.
do. Figure 3 is a diagram of the receiver. 10 is NOU
and an equalizer. The equalizer is a starter-stop device of the opposite bank type, and has the function of making a certain gap correction for the attenuation distortion and second group delay of the telephone line. N(IUo): The output of the equalizer 10 is output to the signal line 10a.
0 and 12 are automatic gain adjustment circuits (
(hereinafter referred to as AGO Doto). The facsimile IJ newsletter output from the transmitter reaches the receiver...1, it is attenuated by the transmission medium, frost, and the telephone line. This I/attenuation value differs each time a line is set up, but once the same line is connected, the attenuation amount remains constant until the communication ends and the line becomes line m+. Therefore, in order to perform facsimile communication, each time the line connection fails,
It is necessary for M to amplify the facsimile signal received by AG (i circuit) 2 to the current level.Signal 12♂
A (40) circuit 12 outputs a facsimile signal amplified to a constant level.A
o It is manually inputted as a reference signal when performing an operation. The AGO circuit 12 also has a signal 116 from the signal discrimination circuit 16.
A signal that determines the timing of the AGC operation is inputted via e. A, GO used in this example
The circuit 12 normally performs an operation called keyed-A GO, and when the input from the signal 1416e is between level 1 and the output peak value of the demodulated "Ql4" input from the II color code line 14a is When the input from the signal line 166 is at level "0" 171 white j1, the gain determined up to that point is maintained and operates as in a). 14 is an A M-P M'-V 8 B demodulator, which is a known circuit. The demodulator 14 extracts the gear from the manually inputted facsimile signal from the output 12a of the A00 timer 12, performs synchronous detection, and further rectifies the aftereffects, and outputs the received Haeseband signal to the signal line 14m. do. 16 is a signal discrimination circuit, which is an important block. As will be explained later with a detailed block diagram, the operation of this circuit is to distinguish a synchronization signal, an interlaced signal 1 picture signal t, and a guard signal from the received baseband signal input from the signal line 14m of the demodulator 14. The results are connected to the signal lines 16a, 16
Output to b, 16c, 16d. At the same time, a binary image ``5'' is created from the received baseband ``5'' from the signal line 14m and output to the 11 signal line 16f.Furthermore,
Synchronization (it is fully detected that Pl"r is arriving at "II", and the level "] is set on the signal line 16e during the synchronization signal's first period.
" is output. Therefore, the AGO path 12 performs the AGO operation only while the synchronization signal is on the f:lI line.'1. '＋
: Ru. Reference numeral 18 is a control circuit, which connects a signal line 188 to a double buffer memory 26, which will be described later in detail, every time it detects the Meishin Ito issue.
The CPU 4 controls the image data stored in the double buffer memory 26. Reference numeral 20 is a part of the printer, which reads out the song 1 signal data stored in the double buffer 26. (In response to No. F and No. 4 20m, this is a block that sequentially reads and records data via the data & I 26a. 22 is a block for reading and recording the data sequentially through the signal discrimination circuit 16 and the block 22 for operating the byte buffer 24. This is a timing clock generation circuit. There are two outputs, and a clock with a frequency equal to the bit timing clock of the i8 machine, that is, 7740H in the case of this embodiment, is output to the signal line 22b. clock, i.e. 62.5 x in this example
It outputs a frequency clock of nz. Reference numeral 24 denotes a byte buffer, which is composed of a serial invariant shift register. In this operation, the received two-part image signal is incremented from the signal line 16f of the blackmail discrimination circuit 16 according to the bit timing 22m, and the image take for 8 bits is outputted in parallel to the signal 124m. Reference numeral 26 is a double buffer memory capable of storing two lines of image data, and is composed of two 256-bit buffers. In FIG. 4, the signal discrimination circuit 16 is illustrated as a block diagram. 30. 32. 34 is a comparator, each of which has built-in reference voltages H2Z and vP. (The received baseband signal input from the IIJ line 148 is compared with the reference voltage VH+vZ+vP, and the result is output as a binary signal to the signal lines 30a, 32m, and 34a. VH＞
There is a relationship of VZ>VP. The comparator 30 detects the high level shown in FIG.
The appearance of ``1'' indicates the arrival of a high level signal, while the appearance of ``7'' indicates that the input signal is not high level. Further, the comparator 32 detects whether the black level or the black level shown in FIG.
1. When it is f, it indicates that a black point at the end of the interlaced signal has been detected. The comparator 34 detects black and white levels m, and the signal 34m has a level "1" as a white signal and a level "0" as a white signal.
A binary image signal with the black signal as the black signal is output. 36 is a counter and the signal line 30 & of the comparator 30
The number of timing clocks input from the signal line 22b is counted only while the input level from the signal line 22b is 1. That is, the duration of the high level is counted. In this embodiment, when the counter 36 remains at a high level for 384 μs or more, the signal line 36a changes from the level I'OJ to the level rlJ.
If the high level continues for 2048 μs or more, the signal line 36
It operates so that b changes from level "0" to level "1". Since the length 1 of the clock input from the signal line 22b is 16 μs, 384 μs is reliable! #22
This corresponds to counting 24 timing clocks of b, and 2048 μs is 128 times the timing clock 22b.
This corresponds to counting. As explained in the section about the transmission signal, the high level of the interlaced signal continues for 775 μB, and the high level of the synchronization signal lasts for 5943 μs, so the fact that the output of the signal line 36 & goes to level "1" means that it is an interlaced signal or a synchronization signal. signal line 3.
When the output of 6b becomes level "1", it indicates that a synchronization signal is being received. 38 is a multiplexer, and the comparator 32,
34 output l118i Select one of the signals of 32a and 34m and convert the inverted signal to signal &
138a. Here, which signal is selected is determined by the value of the output 16@ of the 7-lip flop 40, which will be described later. 40 is a 7-rib flop, which operates so as to be set when the input level from the signal @36b changes from "10" to "1", that is, to output the level rlJ to the signal +Ij 1fia. 42 is a 7-rib flop, which is set when the input level from the signal 136m changes from 10'' to 11''. In other words, the level "1" is set to the signal IJ42m on the signal line 42.
It operates to output level "0" to b. Therefore, when the output 166 of the flip-flop 40 is at level "1", it is known that the synchronous signal is being received, and the flip-flop 40
When the output 42m of No. 2 is at level "1", it can be seen that an interlaced signal or a synchronization signal is being received. The output 42b of the flip-flop 42 has an inverse relationship with the output 42a, and when 42b is "1", 42a and rOJ42b are "0".
421 becomes 11. 44 is a D flip-flop, which outputs a signal 1j4 when the input level from the signal line 3k changes from rOJ to 11''.
It is set and reset by the level of the input signal from 2a, that is, when the input from 42m is "1", the signal line 1
Output level "1" to 6b, input from 42a is 10
”, outputs 1-bell “0” to the signal line 16b. 46 is a D flip-flop, and the signal IviI38m
It is set or reset depending on whether the input signal level from the signal line 16e is "1" or "0" when the input level from the signal line 16e changes from "0" to "1". The result is sent to the signal line 16a.
Output to. The signal 116m is at level 1" 1 j when the 7 rib flop 46 is set, and is at level "O" when it is reset. A counter 48 counts the bit timing clock input from the signal 1122a. counter 4
The output of No. 8 is cleared by the reset pulse input from the signal line 60a and becomes rOJ. The counter 48 outputs level "1" to the signal line 48a every time it counts eight bit timing clocks. Therefore, the same byte timing clock as the byte timing clock of the transmitter is generated from the signal line 48m. 50 is an OR gate, 52 is an AND gate, and 54 is an OR gate. 56 is a delay circuit made up of four 7 lip-flops. This delay circuit 56 converts the data input from the signal IFj line 16b into a clock 1 manually inputted from the signal line 16c.
The signal is delayed by one minute and output to the 6d for B+A testing. 58 is a signal when the bit timing clock inputted from the signal line 22m changes from level rOJ to 11'', which is composed of D tights flip-flops, etc. 7! ! 1154
Latch the data input from J1 and send it +A 16e
Output to. 60 is a pulse generation circuit which is generated by a monomulti, etc., and when the output 16c of the flip-flop 58 rises from the level "0" to "1", it outputs a pulse with a width of about several μ8 to the signal line 60m. do. This pulse is a pulse for resetting the above-mentioned bite color. The output of the @ line ISB is output from the control shown in FIG. 3. The control circuit 18 receives the input i1j1 from the signal discrimination circuit 16.
Synchronization signal by 6m, 16b, 16c, 16d,
jumping signal. When the guard counter receives information for separating the one-picture signal, it outputs a clear pulse to the signal line 18b. This clear pulse causes counter 36, flip-flop 4 (+
, 42, 44, 46, and 58 are all configured to be cleared at IWJ. The configuration of the 1-signal discriminator circuit has been described with reference to FIG. 4, and can be summarized as follows. That is, a separate circuit 16 checks the Haeseband signal received manually from the signal line 14a, and distinguishes whether it is a synchronization signal, an interlaced signal, or a guard signal (9 white signal) by checking the duration of the high-level signal and the presence or absence of a black spot. and send the result to the signal l1I1116a,
Output to 16b, 16c, and 16d. When one signal discrimination is completed, the output 16c becomes tobel [
It goes from 0'' to 11''. At this time, the remaining output 16a
, 16b, and 16d have been determined. The four types of signals are distinguished by the algorithms shown in Table 1 below. Table 1 In the above table, "x" indicates that the level can be either [1] or [0]. Next, the operation of the receiving side configured as described above will be explained using the timing chart of FIG. FIG. 5(,) is a configuration diagram of a received signal. Figure 5 (bl
is the transmitting baseband signal on the transmitting side, and is also the baseband waveform to be received on the receiving side. First, when the synchronization signal starts to be received, the output level of the comparator 3017) becomes "1" as shown in FIG. 5(d), and it is determined that a high level has arrived. The high level continues to be tl&h, and the high level counter 36 continues to count llk time, and when it has counted 24 clocks, that is, about 384 μS, it reaches 7 rips as shown in (a) of FIG. 5(b). 70 Tsubu 42
is set, and the signal line 42m becomes level [1]. Then, when the clock is counted 128 times, fill
After about 2048 .mu.S, the 7 lip-flop 40 is set and the signal 1k16e becomes the level l-IJ, as shown in FIG. After this, this state continues until a black spot appears. Since the signal line 16e is at level "1" during this period, the above-mentioned AGO circuit 12 operates,
The level adjustment is performed so that the highest level of the received baseband signal becomes 5■ (see FIG. 5 (0)). Also, in this period, flli is the output 5 of the OR gate 50 in FIG.
Since 0a is level "0", AND gate 5
The output 52a of 2 becomes the level rOJ, and the 7 rib 70
Since the output of the knob 46 is also at the level rOJ, the flip-flop 58 remains in the reset state. Therefore, the output 16c of the 7-lip flop 58 is kept at level "0". Further, during this period, since the signal #116e is at level "1", the output of the comparator 34 or an inverted signal is selected and output as the output of the multi-breaker 38. Finally, as shown in (c) of FIG. 5(f), when the output 34a of the comparator 34 reaches the 1'+lJ level, the occurrence of a sunspot is detected. Therefore, at this timing, the output of the signal line 38a changes from the [0-level to the "1" level. 7) 1] Tube 44.46 is inserted into the cassette. As a result, the output 16& of the flip-flop 46 becomes the level Ill, and the output 54a of the OR gate 54 also becomes the level "1". Therefore, the next bit timing is 22m
When this occurs, the flip-flop 58 is set, as shown in FIG. 5(4), and the control circuit 18 is notified that the synchronizing signal has been detected. At this time, the signal h16a is at level "1" and the signal h16b is at level rlJ. Although not shown, the output 16d of the guard flag 56 is at level "0".
Therefore, synchronization is detected. Although the synchronization signal consists of a total of 56 bits, it is detected when the 48th bit is received. When detected, a clear pulse of the signal line 18b from the control circuit 18 causes the 7-lip 70-tuff 40.42.4 in the signal discrimination circuit to be activated.
4.46.58. The counter 36 is in a reset state. The signals, %l 16a, 16b, 16e, 16e are at level l-(+-1 and t'), the AGC circuit also stops operating, and the synchronization signal is detected while receiving the take of line 71. The amplification factor determined up to f ago is maintained.Next, when an 8-bit rIIJl signal is received,
The output 48a of the bite hack counter 48 is shown in FIG.
), the level becomes "1" as shown in (e), and at this time, the output 50a of the OR gate 50 is at the level "1", so the output 16c of the flip 70 knob 58 synchronizes with the next bit timing as shown in FIG. The level becomes "1" as shown in (to) of 1,). At this time, the signals 11j 16a, 16
Both signals b are at the level "0", but the output of the signal &116d is the value of the signal 1J116b at the timing shown in FIG.
Therefore, it is detected that a guard signal has been received. At this time, the control circuit 18 stores nothing in the double buffer memory 26. This card band signal is used to remove the ringing waveform at the rear end of the synchronizing signal or the engravings imparted to the subsequent image signal. Since the synchronization signal and interlaced signal are composed of high-level multiples and;
The linking will also be significant. The effect of this Guard Master Hibiki is extremely large. Subsequently, reception of the next signal is started. Figure 5 ((1)
A high level signal was detected in (G), and after the door 384%, if the S song continued at a high level, the 5th
When a black dot occurs as shown in the concavity of Figure 5 (el), the flip-flop 42 is set to the 7 state. As shown in FIG. 10 (i), the output 16b or 1.
/Bell 11'', therefore the output C of the OR gate 50
[Level 11], and at the next byte timing, when (L) in FIG. 5 (1) becomes level [1-1, ANDK)52. The level becomes January, so the free run flop 58 is set by the next bit timing clock 22a, and the signal line 16c becomes the level [month] at 0 in Figure 5 (7?). At this time, Yu Line 1
6a is level ro'16 b is level I'll 16
(Since 1 has a level of 0, it is determined that it is an skip signal. In this case, the control circuit 18 writes one block of white signal data, that is, 64-bit white signal data, to the tuple buffer 26. In the same procedure, the priest 1's jump 4g signal is detected in the second block, and then the card signal is detected at the bogo timing in the case (wa) 7 of Fig. 5 (1). The first iI!Ii low transmission method is the same as explained above, but when using this transmission method, if the line condition is weak and the reception is slow. 'lit;+lpl', (I = number 3 is an image signal error (Ishitoshi calls it "image error"), and a luxurious reverse transmission (RI machine) There is an error in which the image signal sent out is considered to be a skipping error (dankai, image → skipping error), and a jumping signal sent out by the sending 1 bar (1'i) is misjudged and the timing of the sunspot output is incorrect, making the jumping signal correct. Error that cannot be received with U1'', jump error; Black ghost error due to ringing when there is an image signal after Go, white spot due to linking is error 4t
occurs. The above-mentioned image disturbance will be explained by considering two factors representing the characteristics of the same line, namely attenuation distortion and group delay. Attenuation distortion is the amount of line attenuation that occurs in the voice band (3001-h to 3001-h).
．． This means that it is not constant for each frequency (4KHz). 1. This completes the explanation of image disturbance caused by attenuation distortion. Fig. 6(a) shows a typical characteristic A during decay, and Fig. 6(bl) shows a typical characteristic A during decay.
1, the horizontal fill in FIG. 6 is the frequency, and the vertical axis is the attenuation amount. As shown in FIG. 6, the attenuation tends to decrease by 1 as the frequency increases, and this is called the deenergization characteristic. The characteristic B of the 6th evil is,
This is a characteristic in which -C#, the attenuation slope increases as the frequency increases by 1'. This is called the under-equalization characteristic. Figure 7 (at~(dl, 8121(a)~(d)
), (a) reduces the signal block;
(b) trs, reduced table: shows a waveform without distortion, (CH-1
The attenuation distortion is the characteristic B shown in Fig. 6(b), and it is a case where the under-equalization characteristic is not satisfied.
This is a waveform that does not have the characteristic A kink degeneration characteristic shown in FIG. Figure 7 (C), (d), Figure 8 (C1, (d)
1 shows a received waveform (line 44 14a) when the line characteristics exhibit attenuation distortion. Here, assume that the frequency of the main component included in the interlaced signal is lower than the frequency of the main component included in the synchronization signal. In the case of the transient characteristic of FIG. 6 (al), as shown in FIG. As a result, if the current number 42a goes high/bell, the above-mentioned jump → image error will occur.In this case, the image will be displayed in block units (64 The image white shifts to the left side of the image 111 at .
When a signal with p in one block is received for 4 hours, an IQ ghost occurs on the white DM inlay due to linking (62
)-/ru. If the line characteristics have a large degree of insufficient poisoning, the duration time of the high level output to the signal line 3na increases, and even though the sending machine has sent out the rule 4t's, the high level 384μ type or more, 1"/small.

[
As a result, the other "I-i" line 42a goes to a high level, causing the image → interlacing error mentioned above to occur. In particular, an image signal having a pixel arrangement similar to the interlacing signal is likely to be misrecognized. In this case, the image Flock unit (64 cars) than normal position
Move to the right and record. It's a trench, the 4M Kaede jumps (
When transmitting the M signal, check whether there is a problem with the high level duration of the skipped signal on the receiver side, or if the peak value becomes very large, it may take a long time to fall and the sunspot detection timing may be delayed. An error occurs when the skipped signal cannot be received at the correct position. Next, the first image disturbance due to group joint distortion 11C- will be explained. Group delay distortion - 1 This means that the carrier of the signal propagating through the line differs depending on the frequency, and this is due to the fact that the relationship between frequency and phase is not linear (see Figure 9).
Figure 9(a) shows the characteristic C of underequalization, and Figure 9(b) K shows the characteristic of degeneration. Here, the horizontal axis represents frequency, and the vertical axis represents delay time (ms). Furthermore, the amount of delay is 210
It is expressed as the difference from 0Hz. The under-equalized line characteristic is one in which group delay is large at low frequencies and at high frequencies, and the de-energized line characteristic is one in which group delay is small at low frequencies and at frequencies that are equal to each other. In Figure 10 (al to (d)), (a) shows a waveform with four signal blocks, and (b) shows a waveform without group delay distortion.C)
9(a) shows the group delay distortion, and (d) shows the group delay distortion as shown in Figure 9(b). This is a waveform that exhibits the characteristics of 71\. Figure 10 (c) and (d) show the received waveform (signal 114a) when the concave path characteristic cures group delay distortion.
is illustrated. In the case of Kaiwatoku w1 of Kyoji Kadai, the sunspot detection timing is delayed (64), which causes an error in which the jump signal cannot be received at the correct position. In this case, two types of image disturbances occur depending on where in the signal train the error occurs. In Figures 11 C and 12,
The operation of the receiving side for these two types of image disturbance is illustrated as a timing chart. FIG. 11 shows a case where an error occurs in which an interlaced signal cannot be received in the correct position in the middle of a continuous interlaced signal sequence. If the timing of the fC sunspot occurrence is delayed as shown in (a) of Fig. 11 (C1), the
b, 42b are the levels IOJ, and the output 50a of the OR gate 50 is level "0", i.e. 1^"f h
16a is also at level 10, so the signal line 16c is
As in (e) and (b), it does not become level 11. (
In the state of h in e), the signal line 160° 16b is level 11-1. ■ and the interlacing signal ■ are regarded as one interlacing signal. In this case, the image shifts to the left of the screen in units of flocks (64 pixels) from the normal position. Figure 12 shows the interlacing signal at the correct position. This is a case where the image signal continues after an error that cannot be received occurs. Figure 12 (
As shown in (A) of C), when the timing of the sunspot generation is delayed, the signal lines 16b and 42b are at the level "0" in FIG. 4, and the output 50a of the OR gate 50 is at the level "0".
Since the signal line 16a is also level 10,
B. No. 1 Gen. 16C does not reach level 11 as shown in (e). In the state of (e) and (c),
If M 16c and 16b are level 11, signal signals 16a and 16d are level 10.
Therefore, the receiver recognizes the skipped signal in the state 6(e)) or the signal lines 16C and 16d are at level 1.
1" 1a Iwao 16a and 16b are level 10", so the receiver recognizes it as a card signal! -j-ru, that is, the first byte of the 11111 information code is regarded as the card signal. In this case, the image is shifted to the left of the image quotient at the middle of one byte (8 pixels) from the overtone position. In addition, at the time of de-energization, as shown at 66 in FIG. 10 (1c), due to the ringing at the WiJ end of the jump signal, a white void occurs in the black image 1. In the case of under-equalized line characteristics, the ringing that occurs at the rear end of the interlaced signal, as shown at 68 in Figure 10 (1c), causes
White nuke is released '1. do. In the above, we considered attenuation distortion and group delay distortion as factors that degrade line characteristics, but in the case of an actual line, attenuation hangs, phase hits, phase jitter, frequency deviations, instantaneous interruptions, etc. are also not considered, and these are the main factors. This deterioration factor (f 31.
It may be difficult to read the image. A conventional analog high-speed facsimile is equipped with a fixed transmitter in order to reduce the above-mentioned deterioration in received image quality. However, the same-line characteristics of a telephone vary each time a line is connected, and these fluctuations may range from, for example, the characteristic shown in FIG. 6 to the characteristic B1.
stomach). With conventional analog high-speed facsimiles, it has been impossible to completely prevent image quality deterioration due to line characteristics VC. With this kind of analog sieve speed transmission facsimile:
, In order to reduce costs, it is Iomitsu that does not have automatic equalization 4'& function. For this reason, when an lnI line with extremely poor characteristics is captured and transmitted, there is a drawback that the received image quality deteriorates to a level of rl+ due to a transmission error. The present invention is proposed for a facsimile machine having 17 digits after the analog high-speed transmission described above.
Even if you do not have t412, l'l is used before image transmission.
#! By checking the characteristics of the line and changing the transmission method 14 according to the results, deterioration in received image quality due to poor line characteristics can be greatly reduced compared to conventional analog high-speed machines. -lI of the scan line! II! Divide the sequence of pixels into blocks each consisting of N pixel signals, and control the amount of image transmission according to the black and white information of the pixel signals in each block. The first image transmission method, which performs image transmission, has the advantage of fast image transmission, but also has the disadvantage of easily distorting the image if the line condition is poor. Do not divide the image search sequence of scanning lines into blocks consisting of N pixel signals.In other words, image transmission of each scanning line is performed according to black and white information without controlling the image transmission amount.
There is a second image transmission method in which a signal consisting of + and l bits is sent out, and then all 1 pixels are modulated and sent out. This image transmission method has the disadvantage that image transmission is slow, but also has the advantage that image distortion is less likely to occur even in poor line conditions. Therefore, in the non-invention, if the line condition is such that image reading occurs in the first image transmission method, the transmission and reception of the line condition check signal causes the line condition to be bad and the image cannot be read in the first image transmission method. Recognize that this will occur, and
The original is transmitted using the image transmission method. This results in
The fact that image reading occurs is powerful. Also, the &-! Even in the case of image transmission method 2, if the line condition is such that image disturbance occurs (in such a case, even if the original is transmitted in mode 0, there will be a process where image disturbance occurs). , the facsimile transmission, and the receiver terminates with an error and disconnects the line.The line status differs each time the same setting is made, but once the line is connected, it is the same regardless of the line disconnection.Second Even in the image transmission method, if the line condition is such that only erroneous pages occur, no matter how much analog transmission is performed, image skew will always occur, as described in 17 above, so before transmitting the original, it is necessary to Error termination is very useful. As mentioned above, in this case, unless the line is disconnected, 1s1iIi
! The situation has not changed. To avoid the effects of such bad calls, send a fax, set the receiver to an error termination, disconnect the line, and ask them to call you again at 114%.
Switching to a different line characteristic is extremely ineffective4)
. Whirling, conventional redundant side suppression method (first image transmission method)
In an analog facsimile machine, when a certain line is connected, one line status check ( ,,1
The only way to realize that this redundancy suppression signal was not received correctly is by actually transmitting the manuscript and seeing the disturbances in the received image on the facsimile receiving board. There was a serious drawback that it couldn't be done. Therefore, in the invention, the redundancy suppression signal that can be sent by the facsimile transmission 46 failure is
At +F-1, <receive i+ is checked to see if it is successful or not. According to this J'l, when a certain line is ・1S8′斸烙//, the return letter is 'Ir4' +:f, and from yc, a facsimile IJ is sent'<&. It is now possible to check whether or not the transmitting redundancy suppression (in the No. 4 Kefacsimile receiver is correctly received at 11) is in a hemp state (C.) So, actually Il: A: After transmitting the fM, the received image is distorted as you look at the facsimile image (Y-11V). In addition, as mentioned above, based on the line status check signal, the redundancy level can be determined based on the line status check signal. As the suppression signal, the above-mentioned Hi-S IS No. 1 is used to check the error that the skip signal is regarded as an image failure. To check for errors (if number and image signal are regarded as skipping signals), black ghost is used as the number once a month, check these two, !No. 7 G' top! Fuchinic self-Jc . 1st, winning status check signal and 171 jump check 1
It uses No. Ha and Black Ghost Check Iha No. 7. Hereinafter, the present invention will be described in detail by showing Examples 1 and 11. In figure 2V413, check the circular letter/apric (7, Q,
You can transmit the J medium edition using the first image transmission method using the 1-post signal, or you can change the format of all +ff1i prime 8 editions that do not use the 1d issue. The power to transmit the original by the second image transmission method, or to transmit the original, is to send out a tough axis 17 times when the error ends and the line is disconnected (line disconnected). )
The configuration of check No. 1.4 is shown in the figure. The structure of Gnick's most popular 11i body is Mourning 1.
This is illustrated in Figure 3(a). In Fig. 13 (al), (a) is 2100 tlz, and the PLL on the side of Ai et al.
This is the key to adjusting the AGC circuit. Sync signal 1
6 means high level 1 as shown in Figure 13 (bl).
This is a signal in which the black signal continues for 46 bits, the black signal continues for 5 bits, and the white signal level continues for 5 bits. The same applies to the 6 synchronizing signals and 10 synchronizing signals in FIG. 13(,l). Figure 13 fa)
The jump check No. 15 is shown in FIG. 13(C), and the black ghost check signal is shown in FIG. 13(e). The 496 skipping signals in FIG. 13(C) are the 13th
As shown in Figure (1), this is a signal in which a high level signal continues for 6 bits followed by a black signal or 2 bits for 496 times. Implementation of the black ghost check signal shown in Figure 13(e) For example, as shown in Fig. 13(f), following an skipped signal (a signal in which the blank signal continues for 6 hits and 7, the black signal continues for 2 bits), Cart No. 48 (the black signal continues for 3 bits). (After that, the white signal level continues for 5 bits.) This is a signal in which the confidence + 332 bits and the black signal level continue for 32 bits continue 8 times. Figure 14 shows the line condition check used in the present invention. A byte buffer 76 transmits a 41,68-bit parallel signal input from a signal line 70a to a manually inputted clock signal from a signal line 84a. The byte buffer 76 operates by latching it with a pulse (byte clock) and sequentially outputting it one bit at a time to the signal line 76a using a bit timing clock manually inputted from the signal line 74a. It consists of a memory register, etc., and has an 8-bit LSB (fi
It is sent serially starting from the lowest hitter (lower hit). Reference numeral 78 is a variable cane amplifier, and the gain is adjusted depending on whether the signal value of the Shingetsu line 82a is 1 or 10. It operates so that the gain is -2 when the signal line 82a is at the level I'll, and the gain is 1 when the signal line 82a is at the level "0". The transmission signal amplified by the variable gain amplifier 78 is also output to the signal line 78a. 80 is an AM-)'M-V8B modulator. This part is a well-known block and will not be described in detail, but the signal line 78
．． The transmission signal manually inputted from I is inputted into the modulator 80 by J+1 so as not to generate pressure at the time of tone; /z 1.
l't' (low-pass filter) jh'
! A1~l-PM-VSB# tuned to limited f friends,
It is sent out to the line via the network control circuit N (2U (not shown). 74 is a timing pulse generation circuit that generates each turret timing pulse used in the transmission A8, and 2
Generates a timing pulse for Yuzu. For example, No. 41-74a contains a human timing pulse having a frequency of 7740 Hz. This pulse t is applied to the byte buffer 76 and the delay element 82. Since the transmission data is sent at this pulse timing, the sending speed is 7740 bps. On the signal +1j74b, a byte timing pulse, which is the frequency of the l'lII+i bit timing pulse divided by 8, appears, and this pulse has a pattern of ゛il=profit70. Control circuit 72°411p element 84V is applied/). Its frequency is 774V8 = 967.51-(z. 82 is a slow 4jiH element, which is composed of flip-flops, etc., and connects the signal input from the signal line 70b to the signal line 74a.
One cycle of the bit timing clock input from f+
To output to E bus F (2a) with a delay of
Create fLI1. Reference numeral 84 denotes a delay element, which outputs a timing pulse delayed by a certain period of time (for example, half the time of the bit timing clock of the timing pulse generation circuit 44) from the byte timing clock of the timing pulse generation circuit inputted from the output circuit 74b. , is output to section 84a. This abrasive pulse operates as a pulse for latching 8-bit data in the byte buffer 76. 70 is a pattern generator, an address setting circuit and 10
X 124 pit R, OM (++4ad On/
yMemory)%. In FIG. 15, the memory map of the pattern generator is blanked out. 0-123
10 bits of valley data are output in response to the address. The 10-bit information is sent to the confidence line 70c, and the 9th bit information counting from the lower bit is sent to the signal line 70+).
The 1st to 8th bit information counting from the lower bits is output to the signal line 70a. The key for the 8-bit data that is latched into the byte buffer 76 via the signal line 70a and then sent out sequentially by the bit timing clock is the signal line 70a.
It is determined by the signal output to 0b. The signal is input to the variable gain amplifier 78 via the delay element 82. To send a check signal to check the line status, first set the address pointer to 0, and every time you receive a byte timing pulse from the signal a 74b, the address data of the address pointer currently pointing to No. 46 1g 70a,
This is done by outputting to 70b and 70C. The address pointer is increased by receiving a pulse from the control circuit 72. That is, when one pulse occurs in the signal @72a, the address pointer is incremented by one. The address pointer is set to 0 in the initial state. The control circuit 72 includes the pattern generator 70 as described above.
This circuit controls the address pointer of . Here, as an example, an embodiment will be described in which sequence control is performed using a microprocessor. In the initial 4 Oozu, the pattern is 4-<:
The address pointer of y is set to O, and the internal register of 13 registers (1st row, 8th row) of the control circuit is set to 1. The main control of the control circuit 72 is to input the data of the address currently pointed to by the address pointer by manually closing the signal line 70c when a byte timing pulse is generated on the signal i 74b. Here, the data input from 70c is configured to correspond to the 10 bits output from llt(')M. Using the data from the 7°C, the clock data is also transmitted from the pattern generator 70 to the fixed byte timing clock.
, 70b, that is, whether or not to hold the address pointer. The control flow of the control circuit 72 is not fully illustrated in FIG. At 85 in FIG. 16, the contents of the register are initialized, that is, the contents of the register are set to 1. At 86, it is determined whether a pulse has occurred on the signal line 74b, that is, whether a byte timing clock has occurred. At 88, the contents of the B register are decremented by one. At 90, it is determined whether the contents of the B register are 0 or not. If the contents of H cash register are not O, 9
1, it is determined whether the content of the B register is 1, and if it is 1, a pulse is generated on the signal line 72a (92), that is, the address pointer is advanced by one. At 90! If the content of the 3 register is O, the signal line 70c
is input (94), that is, the data at the address currently pointed to by the address pointer is input. When this manually generated data is IFF')l (96), put 5 in the B register (10
6), when φFF'H (98), put 4 in B register (1
12), 33FH (100) is 496 at B cash register
(108). Also, when 13FH or φF8H (
102°]04) puts 1 in the B register (110) and generates a pulse on the signal line 72a (111), that is, advances the address pointer by one. If the data on the signal line 70c is not the above-mentioned 5 citrons, 4 is entered in the B register (112). Now that the address pointer is set to O-c1, we will explain how the synchronization signal is actually sent. First, the determination in step 86 is repeated at 1 when a pulse occurs in the signal i 74b. When a pulse is generated on the signal line 74b, the B register is decreased by one at 88, becomes 0, and becomes 90.
The verdict is yes. At 94, signal m 70C
When input, the data is IFF'H. At this time,
11'' is output from the pattern generator 7° to the signal line 70b, and the FF river (all 8 bits are high level) is output to the signal line 70a. Since the data is IFF't-t, the judgment in 96 is YES and 5 is set in the B register (106). When the second byte timing clock occurs, the contents of register 13 go to 4. When the third byte timing clock occurs, the contents go to 'dt13' in the B register. When the fourth byte timing clock occurs, the contents go to 'dt13' in the B register. The contents of go to 2, 5
When the second byte timing clock occurs, the contents of the B register become 1. (For the 2nd to 5th byte timing clock, 11" IJ is output to the signal line 70b and IFF is output to the signal line 70a.) At this time, the judgment at 91 is YES, and at 92, the address pointer is One by one, it becomes 1. When the byte timing clock occurs again, the contents of the B register become 0 and become 90.
The verdict is yes. When the signal line 70c is input at 94, the data is 13FH'''C.At this time, the pattern generator 70 outputs 1.l['1' to 70b and ['3F'HJ] to the signal line 70a. There is. Since the data is 13FH, the judgment at 102 is YES, and 1 is placed in the B register (110). At 111, the address pointer is advanced by one and becomes 2. Consider the signal sent when the address pointer changes from 0 to 11. I F F H data 5 times, then 13
FH data will be sent out once. In both cases, since the 9th bit counting from the most significant bit is 1, a high level signal is sent. Additionally, the 8-bit data is sequentially sent out from the LIB side by the byte buffer 76, so the high level signal is 46 bits, followed by the black level signal with 2 bits.
The bit will be sent out. This is shown in Figure 13 (b
), it corresponds to 1 digit of synchronization number 18'. Thereafter, all checks are sent to the line in the same way. A timing chart of the check signal sending circuit of FIG. 14 is shown in FIG. 17. FIG. 17 shows a timing chart in which two synchronization signals are sent. The signal appearing on the signal line 78aK of the variable gain amplifier 78 has a transmission base band waveform as shown in FIG. 17(a). 1. Since the address pointer is in the initial state, it is set to 0 (see Figure 17).
f) Reference 9° Here, the signal 1 is set by the byte timing clock (a) of the news publication line 74b shown in FIG. 17(C).
11j170ai/This is "FF11", signal 11170
"1" is output to b. That is, as shown in FIG. 17(d), the contents of the byte buffer (76) are F F H,
As shown in Fig. m17 (e), the gain control signal is at the "1" level. From this VC, as shown in FIG. 17(b), the "1" level is output in 8 bits to the transmission binary signal (signal line 76a), and the amplifier output (as shown in al) is Nk', +714ζ. (, (Bus 78a) is output with 8 bits of "high level". Key number 874)) Byte timing clocks (B), C→, (D), and (E) are also output. The operation is the same as the operation in clock (a). When the byte timing clock ((e)) of signal w 74b is generated, the address pointer changes from "0" to "1". Due to the timing clock, the signal line 70a V is output as [3FHJ, and the Shingetsu line 70bK is output as [1-1. That is, the 17th
, the content of the byte buffer (76) is 31!''H as shown in Figure (dl), and the gain control signal becomes the IOJ level as shown in Figure 17(e).As a result, j!417
Send as shown in figure (b) 1] Binary signal (signal line 76a)
For I' I J level or 6 bit I, it is rOJ
The level is output in 2 bits, and as shown in Figure 17(a) I/C, the amplifier output (signal line 78a) has a "high level".
is output as 6 bits, followed by 2 bits as 1-black level. Still, the byte timing clock (to) of i1 horoscope i%174b occurs [7, the address pointer is 11
．． From 1 to "2". For the byte timing clocks (g), (1), (m, (nu), ni) on the signal line 74b, the byte timing clocks (a), (b), (c), ni), ((1) ).For the byte timing clock (3) of the byte on the signal line 74b, the operation is the same as that for the byte timing clock (to).Thereafter, a check signal is sent to the line in the same way. Next, the operation of receiving the line status check signal used in the present invention will be explained using an example.The circuit for receiving the check (j5 is shown in FIG. , is almost a circular circuit as in Fig. 3.The difference is that the control circuit 18, printer 20, and buffer memory 26 in Fig. 3 are no longer present in 1)!l''4, and the control circuit 114. l) A. In Figure 19, CN'l"8Y (count sync) 1
, CNTPIX (Count Thinks) , CN'rG
RD (count car)), CNTSY (count sink)2゜Secure a 1-byte memory area for CHKPTR (check pointer), and secure a 2-byte memory area for CNTSKP (count skip)6
Then, count the synchronization signal (sync), double signal (bits), card signal (card), and skip signal (skip). Reference numeral 118 denotes the memory 13, which is constituted by FL A lvl of s x ioo bits and the like. FIG. 20 shows a memory map of memory B 118. 2019th
As shown, the memory addresses correspond to addresses φ to 99. The control circuit 114 receives the check signal sent by the transmitter, and sends the reception result of the skip check signal to Memo+7A.
The reception result of the black ghost check signal is stored in memory B. The control circuit 114 is similar to the control circuit 18 in FIG.
When the information for distinguishing between the synchronization key number, Hietsu number 41, card signal, and image signal is received by b, 16c, and 16d, a clear pulse is output to the signal line 114c.
). The counter 36° flip-flops 40, 42, 44, 46.58 are all cleared at the same time by this clear pulse. The control circuit 114 performs the following control on the memory A 116 and memory B 118. In the initial state, the control circuit 114 sets the contents of CNTSYI of the memo IJA 116 to -28 and CN
'I' P I
The contents of R are set to O, and the contents of 8×100 bits of memory H, 118 are set to FFH (all 8 bits are at high level). The control circuit 114 recognizes that any one of the synchronization signal, interlaced signal, card signal, and image signal has been received when the signal line 16C changes from level "0" to level E. (+-1 line l6c is level 11.)
, the control circuit 114 controls the signal lines 16a and 11
No. 1 m16b. Inputs 1 and 7 to signal line 110 of signal line 16d, synchronization signal is received (in this case, (4+□16a becomes level 1)) or jump 1i- signal is received (in this case, signal 11Q16a is Level I"OJ, (M number fN16b
(becomes level 11), or in this case, if you want to receive the cartoy number f, the 1g pair line 6a 2 double number Iwao 16b will be level 0 (1i: M H16a will be level 11), or the image signal Receive 1 bar L7 (in the case of Jin, signal line 1
6a, signal line 16b, and signal line 16d are at level ``0''). When a synchronization signal is received, CNT
Increase the content of SYl by 1 [,7, If you receive the skipping issue, increase the internal medicine of CNTSKp by 1, and if you receive the issue of card 1, CN T G I (,D) If the content is increased by 1 and image 4g+j is received, CN'l
“Increase the content of PIXO Uchitani.Here, CNTSYI,
CNTSKP, CNT (iR, D, CNTPIX) Increasing the contents of the temple by one is possible by
J CN1'sYl, CNTSKP, CN'l'GH,
IJ, CN'l'PIX Temple was built manually, and 1" shield and 1. The result obtained by outputting the result to E+, :゛solution ρ114;+) is used. 'lNi's Y]
is carried out while the internal value of is negative. CN i' S Y
If the number 1 is no longer negative, then the first bet is -11. When the counter wire 16c reaches level [1], the counter wire 16a is operated manually, and it recognizes only whether it is a signal other than ML or Y. Do.Sync 44
If the signal is received, the internal medicine of CN'I'SY2 is increased by one, and if all signals other than synchronous signal 16 are received, the data output to the signal line 24a is stored in the memory BK. The address stored in the memory 811B is C1-IKPTI.
(The internal medicine department of
After storing in memory B, 118, add one internal medicine to CI-IKPTR. The above is held while the contents of CNTSY2 are negative. At the point when CN i'' S Y 2 is no longer negative, the reception η of the check key horoscope is completed.
The figure shows 1. At 120 in FIG. 21(a), it is determined whether the signal line 16c is at level [1j, that is, whether one signal discrimination has been completed. At IIL 122 after one signal discrimination is completed, the signal line 16a becomes level 11.
'', that is, whether the synchronization signal has been received. If the signal fIM16a or the level fil, li'l is received, the content of CNTSYl is incremented by one (124). 126 to Oi-C, CNT8Y 1
If the content is negative, the reception of the jump check signal is completed and the signal is disconnected. Reception of jump check signal completed 1. *, then jump to the beginning of BL (12B) in Figure 21 and call for reception of the black ghost check signal. At 122 VC, the signal line 16a is at level 10'', that is, synchronization (if the signal is not received, the signal line 16b is at level 130)
It is determined whether the signal line 16b receives a level ``1'', that is, a jump signal (Th).If the signal line 16b receives a level ``1'', that is, jump signal No. 48 is received, increase each of CN'vSKP by one.
2) Return to 120 again. ] If the 30V input signal W16b is not receiving the level f-OJ, that is, the jump signal, t:j:, 134, pair 1 to 1i.
It is determined whether the signal 6d is at level 1'1'', that is, whether a card signal has been received. If the level [1] is reached, that is, the card signal is recognized H, the contents of CNTGFLD are increased by one (136), and the process returns to step 120. In step 134, if the signal line 16d receives a level l-0J, that is, an image signal, increase internal medicine in CNTPIX by one 138), ? ) and return to 120. The above is continued until 1, CNTSY1, is no longer negative as described above. CNTSYl ceases to be negative, that is, becomes zero, when 28 synchronization signals are received. The structure of the tick signal is as shown in Figure 13. 21
Following 00Hz, 16 synchronization signals are received. While receiving the jump check signal, receive 9 synchronization signals. Additionally, there are six synchronization signals between the jump check signal and the black ghost check signal. The contents of CNTSYI become zero when three synchronization numbers 48 between the jump check signal and the black ghost check signal are received. When the content of CN'l'SY1 becomes zero, it is placed at the beginning of FIG. 21(b). That is,
Jump check No. 411 was successfully received by the control shown in 21st ward huge a), and the received 4N result was stored in memory A. Stored in 116, black ghost check number a is the 21st
According to the control shown in FIG. 1 (1) (described below), the reception is received and the reception result is stored in the memo IJr;, 118. If the check signal is correctly received, CtVTSYl, CNT8KP, CNTGRD. All contents of CN'rPIX become zero. I received 28 +1jl signals, all of which were zero.
At the +y7 point, we received 1984 flying signals, 4 negative signals, and 0. Next, we will explain Fig. 21 (bl). 140i7 (L/l't, in" 3 line 16c in Fig. 21 (b) is level "1", that is, one round It is determined whether the discrimination has been completed. 1 Samurai (1 Samurai whose fi discrimination has been completed, 142
At this point, it is determined whether the signal line 16a is at level "1", that is, whether a synchronization signal has been received. When the signal line 16a is at level "1", that is, when the same gate signal is received, CN'['
Each of S Y 2 is increased by one (144). 146
In , it is determined that the content of CNTSY2 is negative, that is, whether or not the 9th round of check No. 4g is locked. Check 15
For those who have not yet completed the receiving of the number, the number is 140.
Return to If the number of Ukeiro is r photon on Checki (1
48) Now, determine the reception result of the Saguro ghost check signal. Specifically, the player counts the number of black dots in the 3 bytes of white information after the card signal to score a profit. +E-1-,,<If the number of black dots Fi is zero, the number of black dots Fi is zero. 142, if the signal line 16a is at level ]0'', that is, no synchronization signal is received,
At 150, the data output to the signal line 24a is stored in the memory B. The address to store in memory 8118 is shown in the contents of CHKPTFL. At step 152, the contents of CL (Kl"TR) are increased by one. With this, the reception of check No. 48 sent by Futsukatsuki is completed. Based on this reception result, the pixel 45 of the -scanning line is The first ++ to 11 divides the code sequence into blocks consisting of N pixel signals in advance, and controls the amount of image transmission according to black and white information of the pixel signals in the block to perform image transmission. Depending on the transmission method, the transmission of the manuscript is C.
r or - The pixel signal sequence of the scanning line is not divided into blocks of pixel signals, that is, the image transmission amount is not controlled according to black and white information, but all pixel numbers are modulated individually. Either to transmit the original using the second image transmission method that can send the original, or to disconnect the line (cut off the line) by treating the 7-axis IJ transmission/reception map as an error termination in order to transmit the original. It is determined. The criteria for these three stages are shown in Table 2 below.・First, for the jump check signal, make a two-bore judgment of ○ and ×, and for the black ghost check signal, make a judgment of 0. △,
Three types of judgments are made: x. In Table 2, don't
Care is (Ts-yet means x and both. Table 2 shows F-3, the 1'1 constant result of the FJ No. 1 of the black ghost check signal, and the 1'41 of the black ghost check signal. If is Q, the original is transmitted using the first image transmission method V (-.If the judgment result of the jump check key number is ×, the judgment result of the black ghost check signal is 0, and the black ghost check If the judgment result of the signal is △ (the judgment result of the jump check signal is don't care), transmit 1 Emperor using the second image transmission method. Judgment result of Black Ghost Check No. 8 If the result of the skip check 1 is "don't care", the facsimile transmitter/receiver will terminate the line due to an error and the line will be disconnected before transmitting the original message. This is a signal that mainly detects skip → image errors and errors in which the skip I= signal cannot be received at the correct position due to a delay in the black spot detection timing when a document is transmitted using the image transmission method.Jump check signal As mentioned above, two judgments are made (T and ×), and the +41 standard is described below.○
496 x 4 jumps [No. 1 is reproduced. That is,. × means that the interlaced signal of 496×4A is not reproduced. i.e. 1-), memory A, 116 CN'I
' 8 K It is important that the content in the PO is zero. The black ghost dynamic signal is a signal that mainly detects the occurrence of black ghosts in white 11.1141 due to linking when a 11D document is transmitted using the conventional first image transmission method. In the case of characteristic B, that is, the under-equalization characteristic,
Image → Jump error also occurs, but when this error occurs, it is always white oil 11M due to ringing! The black ghost inside will appear. Regarding the black ghost check signal, as described above, <0. Δ
, × are performed, and the criteria for the determination will be described below. FIG. 22 shows a portion of the black ghost check signal. As for the black go-to check signal, the border signal shown in FIG. 22 is transmitted eight times. Figure 22(a) is
This is the transmission baseband No. 4G on the transmitting side. Figure 22 (b
) and (C) are the receiving 8 baseband signals. Second
As shown in 21'Q(b)(a) and FIG. 22(C)(b), it is checked how many black dots are generated in the 3 bytes of white 1. $22 figure (bl is white information 3
This is a specific example where no sunspots occur on the part of the bite, 814
FIG. 22 (C) is a specific example in which a black dot appears in 3 bytes of white information as shown in (C). Since the black ghost check signal shown in FIG. 22 is sent eight times, it is checked how many black dots are generated in the self-extinguishing 113×8=24 bytes. The ○ in the judgment result regarding the black ghost check signal is self-portrait @ 3 × 8
= This is the case where no black dot occurs in 24 bytes. Δ is a case where a black dot of 16 dots or less occurs in a white image of 3×8=24 bytes. × means self-portrait 973 X 8=
This is a case where black dots of 17 or more dots occur in 24 bytes. From the above, the receiver receives the check signal sent by the transmitter Kaede, and either transmits the original using the first image transmission method or transmits the original using the second image transmission method. It is possible to recognize whether the facsimile transmitter/receiver should terminate the line due to an error and disconnect the line. Which of these three steps to use depends on the first step in transmitting the manuscript.
1il, that is, it must be communicated to the facsimile transmission 4 side at the front end. This pre-procedure is explained in Recommendation 30 of CC1'r '1', so its explanation is omitted here. After Nt, we will briefly discuss the second image transmission method. The following changes may be made to the image transmission method of 1. On the facsimile transmitter side, the pixel signal string of the -scanning line is not divided into blocks each consisting of a predetermined number of pixel signals, that is, black and white information is Accordingly, all pixel signals are modulated and sent out without controlling the image sending mechanism.Specifically, since they are not divided into blocks, there is no need to send out skipped signals.On the facsimile receiver side In this case, the control circuit 18 in FIG. 3 does not input the signal line 16b from the signal discrimination circuit 16, and performs one signal discrimination as shown in Table 8143.
Recognizes synchronization signal, card number M, and image signal. Further, the delay circuit 56 in FIG. 4 receives the signal line 16a instead of the signal line 161). That is, since the facsimile transmitting machine does not transmit an interlaced signal, it is naturally impossible to recognize an interlaced signal. One of the reasons why the receiver treats the interlaced signal sent by the transmitter as an image signal is that the high level duration time is 3.
It may be shorter than 84 μs. When electronic transmission of the original is not possible using the first image transmission method,
Second I [! Instead of transmitting the signal using the ll image transmission method, a method of transmitting the interlaced signal by slightly changing the structure (for example, doubling the high level duration time) may also be considered. Furthermore, in this embodiment, it has been explained that the check signal is sent and received immediately before image transmission, but once the line is connected, the line characteristics do not change over time.
It is clear that there is no need to check the line characteristics for each individual card using Che 7248 when communicating with multiple cards in succession. Based on the above explanation, according to the present invention, in analog speed facsimile, the line status is checked before image transmission, and depending on the result, the transmission method is changed or the line is disconnected, thereby making it easier for the user. The first image transmission method, which is very easy to use, divides in advance into blocks each consisting of N pixel signals, and transmits the image by controlling the amount of image transmission according to the black and white information of the pixel signals in the block. A synchronizing signal consisting of l bits is sent to the image sending AiJ of each scanning line, and when the block is the first block containing black information, N image signals are sent, - and when the block is the second block containing all white information. In some cases, a block number consisting of n bits smaller than N is modulated and transmitted, and only if the block immediately before the block before transmitting the block code of the first block is the second block. Changing the card signal consisting of m bits ii1. In a facsimile machine having a first image transmission method of transmitting a 'tl image, prior to transmitting a document, a check signal which is a certain -W image pattern is transmitted and received, the line condition is checked, and the above-mentioned image of $1 is transmitted and received. Transmit the original by a transmission method, or - do not divide the pixel signal string of the scanning line into blocks consisting of N pixel signals, that is, do not control the image sending amount according to black and white information, and The original is transmitted using the second image transmission method, in which a synchronization a signal consisting of l bits is transmitted before the image is transmitted, and then all pixel signals are modulated and transmitted, or the original is transmitted. It is now possible to disconnect the line of the facsimile transmitter/receiver as an error termination before doing so. As a result, the pixel signal string of a -scanning line is divided in advance into blocks each consisting of N pixels of 4m size, and the image transmission amount is controlled according to the black and white information of the pixel signals in each block to perform image transmission. In the first image transmission method, if the line condition is unstable where image disturbances occur, the system recognizes that the line condition is poor and image disturbances occur in the first image transmission method by sending and receiving check ID d'. 2.-The pixel signal string of the scanning line is not divided into blocks each consisting of N pixel signals. That is, the second image transmission method transmits a synchronizing signal consisting of l bits before transmitting an image of each scanning line without controlling the image transmission amount according to black and white information, and then modulates and transmits all pixel signals respectively. By transmitting the original using this method, image distortion no longer occurs. That is, to summarize, the adaptability of analog high-speed facsimile to lines has been greatly improved. In addition, if the line condition is such that image disturbance occurs also in the second image transmission method (in such a case, ()
(Even if you transmit the original in mode (mode), image distortion will occur), it is possible to mark the facsimile transmission or reception as an error and disconnect the line. The line status differs each time the line is set up, but it is the same in the trenches where the line is disconnected after the Hidadapi line is connected. Even in the second image transmission method, if the line condition is such that image disturbances occur, as in 17 above, when performing analog transmission, image disturbances will always occur. It is very effective to set the facsimile transceiver to error termination. In addition, as mentioned above, in this case, unless the line is disconnected, the condition of the same line will be poor, so if you transmit the image without disconnecting the line, image distortion will definitely occur, so the original will be transferred to It is very effective to set the facsimile transmitter/receiver to an error state and disconnect the line before the facsimile transmitter/receiver. In other words, before transmitting the manuscript, I realized that I really missed the recollection state, and I no longer had to transmit the manuscript unnecessarily.

[Brief explanation of drawings]

Figures 1 (a) and (b) are configuration diagrams of the transmission Iba signal by the first image transmission method, and Figures 2 (a) to (C) are configurations of the synchronization signal, interlaced signal, and card band signal. Figure 3 is
Block diagram of the process up to reception using the 1st programmer transmission power method, 4th
The figure is a block diagram of the Ig discrimination circuit 16 in Figure 3.
Figures (a) to f/) Timing chart of the operation of the receiving side according to the image transmission method in Figure 11 (al).
- (e), Figures 12 (a) - (e) are timing diagrams when an error occurs that prevents the reception of the 1st image at the correct position (1st image transmission method (' 13(a) to (fl are 1 to the present invention)
1-1 is a block diagram of the check signal required, 1AjJ14 is a memory map diagram of the small device 70, 16th is a control flowchart of the restraint j circuit 72 in FIG. 14, and 17(a) to (
fl is the check signal sending circuit diagram in Fig. 14, 2nd
Figure 0 is a memory map diagram of memo IJ H118 in Figure 18, section 21 (aL (bl is control 10... in Figure 18).
NCU equalizer 12... AljC14... Demodulator 16... Information cell division circuit 18... Control circuit
20...Printer 22...Timing clock 24-Pite buffer 26...Buffer memory 70...Pattern generator 72...Control circuit 74-
... Timing pulse generation circuit 76 ... Byte buffer 78 ... Variable Kane amplifier 80 ... Modulator 82
...Delay element 84...Delay element 114...
・Control circuit 116...Memo IJ A118...
・Memory +3 Applicant: Canon Co., Ltd. ! 1 Fig. 2 81 躬 6 蛎) 凰 6th counter (b) 0 10 26 Jl) A 廚吚(V,
Hz) (α) Figure 8 (α) 11 of the same group, Suzuki Hikari Yu, Figure 8 (α) 11.
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(b) (C) Figure 11
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(o) (Chang) (d) 7 Japanese Patent Application 0n5B
-139563 (23)

Claims (1)

[Claims] (1) High-speed transmission analog facsimile using a redundancy suppression method is characterized in that the redundancy suppression signal sent by the facsimile transmitter sends and receives a line status check signal to check whether the facsimile receiver (ill) can receive the redundancy suppression signal correctly. 2. A facsimile device according to claim (1), wherein the line status check signal has @! number of check signals depending on the error content of the redundancy suppression signal.