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JPS58134498A - Multilayer circuit board - Google Patents

Multilayer circuit board

Info

Publication number
JPS58134498A
JPS58134498A JP57017742A JP1774282A JPS58134498A JP S58134498 A JPS58134498 A JP S58134498A JP 57017742 A JP57017742 A JP 57017742A JP 1774282 A JP1774282 A JP 1774282A JP S58134498 A JPS58134498 A JP S58134498A
Authority
JP
Japan
Prior art keywords
adhesive
connection part
wiring pattern
wiring
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57017742A
Other languages
Japanese (ja)
Other versions
JPH0472399B2 (en
Inventor
健治 大沢
隆夫 伊藤
徳光 始
正美 石井
告原 信俊
大沢 正行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP57017742A priority Critical patent/JPS58134498A/en
Publication of JPS58134498A publication Critical patent/JPS58134498A/en
Publication of JPH0472399B2 publication Critical patent/JPH0472399B2/ja
Granted legal-status Critical Current

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は、電気部品挿入部においてその部品リード線及
び配線パターン間の接続を確実になしたsJgI頼性を
有する多層配線基板に係わる。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer wiring board with sJgI reliability that ensures reliable connection between component lead wires and wiring patterns in an electrical component insertion portion.

本発明の理解を容易にするために、本出願人が先に提案
した多層配線基板について述べる。この多層配線基板は
、#I1図に示すように絶縁基材(1)の−面に導電箔
例えば銅箔による第1の配線パターン(2)・を形成し
て後、第1の配線パターン(2)の接続部(2a)を除
いて所望の絶縁樹脂層(3)を形成し、さらにこの上の
裏面に接着剤(4)を付した導電箔例えば銅箔を積層合
体し、この銅箔を選択エツチングして第2の配線パター
ン、(5)を形成し、次に@2の配線パターン(5)の
接続部(5a) K設けられた開口部内の接着薊(4)
を除去し、さらにその開口部内に臨む@1の配線パター
ン(2)の接続部(2りの中央を貫通する如く電気部品
挿入孔(6)をプレス勢にて穿設して構成され、その後
、この挿入孔(6)に電気部品(7)のリード(8)を
挿入して半田、その他等の導電性物質(9)にてリード
(8)、接続部(2り及び(il)を電気的に接続する
ようになされる。この多層配線基板は従来の多層配線基
板に比して高書度回路が得られること、安価Km造でき
ること等の利点を有する。
In order to facilitate understanding of the present invention, a multilayer wiring board previously proposed by the present applicant will be described. This multilayer wiring board is manufactured by forming a first wiring pattern (2) made of conductive foil, for example, copper foil, on the - side of an insulating base material (1), as shown in Figure #I1, and then forming a first wiring pattern (2) made of conductive foil, for example, copper foil. A desired insulating resin layer (3) is formed except for the connection part (2a) of 2), and then a conductive foil, such as a copper foil, with an adhesive (4) applied to the back side is laminated and combined. selectively etching to form the second wiring pattern (5), and then attach the connection part (5a) of the wiring pattern (5) @2 to the adhesive hole (4) in the opening provided.
is removed, and an electrical component insertion hole (6) is drilled by pressing force so as to pass through the center of the connection part (2) of the wiring pattern (2) of @1 facing into the opening, and then Insert the lead (8) of the electrical component (7) into this insertion hole (6), and connect the lead (8), the connection part (2 and (il)) with solder or other conductive material (9). This multilayer wiring board has advantages over conventional multilayer wiring boards, such as being able to provide a highly accurate circuit and being manufactured at a low cost.

しかるに、この場合電気部品挿入孔(6)が形成された
配線パタ゛−ン(2)及び(5)の接続部分においては
、第2図の拡大図面で示すように上層の配線パターン(
5)の接続部(5畠)が−人孔(6)をとり囲むように
朗じた内周面を有する環状に形成されている。こめため
に、上層の配線パターン(5)を形成して後に、接続部
(5a)の開口部に臨む接着剤(4)を有機溶剤(剥離
液)Kよって膨潤させ、あるいはその後機゛械的ブラッ
シングによって剥離する(新開下層の配−パターンの接
続部(2a)上面の活性化)ときに、剥離液の溜まりに
よる接着剤再溶解汚染が生じ、また周壁の存在によって
開口部内における機械的ブラッシングが満足に行えず、
接続部(2m)上面の活性化が不充分となり、結果とし
て導電性物質(9)との電気的接触が不充分となり電気
抵抗が尚くなる慣れがあった。また例えば溶融半田ディ
ツプにより導電物質(9)を充填する場合、第2図に示
すように開口部内に空気腐りa鋳が生じ導電性物質(9
)の光槙即ち半田伺けを阻害し、さらに溶融牛田温腋に
もとづt!接続部(5りの接着剤(4)K残貿している
ガス、水分、気泡に・よる熱時のストレス::1 が導電性物質(9)K悪影響を与、、i、、える惰れが
あった。
However, in this case, at the connecting portion of the wiring patterns (2) and (5) where the electrical component insertion hole (6) is formed, the upper layer wiring pattern (
The connecting portion (5) of 5) is formed into an annular shape having a rounded inner peripheral surface so as to surround the human hole (6). For this purpose, after forming the upper layer wiring pattern (5), the adhesive (4) facing the opening of the connection part (5a) is swollen with an organic solvent (removal liquid) K, or mechanically removed. When peeling is performed by brushing (activation of the upper surface of the connecting part (2a) of the newly opened lower layer), adhesive re-dissolution contamination occurs due to pooling of the peeling liquid, and mechanical brushing within the opening is caused by the presence of the peripheral wall. I can't do it satisfactorily,
Activation of the upper surface of the connecting portion (2m) was insufficient, resulting in insufficient electrical contact with the conductive substance (9), resulting in increased electrical resistance. For example, when filling the conductive material (9) with molten solder dip, air corrosion occurs inside the opening as shown in Figure 2.
)'s Mitsumaki, that is, Handa Kake, is inhibited, and furthermore, it is based on the melted Ushida Atsushi armpit! Connecting parts (5) Adhesive (4) K Residual gas, moisture, air bubbles, heat stress: 1 The conductive material (9) K has an adverse effect, i, Increased stress There was that.

本発明は、上述の問題点、奄改善し、さらに信頼性の^
い多層配線基板を提供するものである。
The present invention solves the above-mentioned problems and further improves reliability.
The present invention provides a multilayer wiring board.

以下、図面を用いて本発明による多層配線基板の実施例
について評述する。
Embodiments of the multilayer wiring board according to the present invention will be described below with reference to the drawings.

第3図は本発明の一実施例で、工程J11K示すもので
ある。本例においては、第3図人に示すように絶縁基材
(例えば紙フェノール、紙エポキシ等の硬質絶縁基板、
又は可撓性絶縁基板も可)3υの一主面に導電箔例えば
、銅箔を被着した銅張積層板を用意し、七〇銅箔な選択
エツチングして票lの導電箔パターン即ち配線バターン
シシを形成する。
FIG. 3 shows an embodiment of the present invention, which shows step J11K. In this example, as shown in FIG.
Alternatively, a flexible insulating substrate is also possible) Prepare a copper-clad laminate with a conductive foil, such as copper foil, coated on one main surface of 3υ, and selectively etch the copper foil to form a conductive foil pattern, i.e., wiring, as shown in Table 1. Form Bataan Shishi.

このとき、配線パターン(2)と次に形成する絶縁層と
の密着性を良くするために、配線パターン四に対して表
面処理を施すを可とする。表面処理としては黒化処理の
他に表面K CuOlCum0勢の酸化膜を形成する化
学的粗面化処理、あるいはサンドブラスト又はプ2ツシ
ングによる機械的粗面化処理等がある。次に、第1の配
線パターンQ々を含む基&αυ上に例えば紫外線硬化型
の樹脂による絶縁層(至)を第1の配−パターン(2)
の接続部(図示の例’l’11.11・;・ では略円形状)(≠2りを除いて印刷により形成する。
At this time, in order to improve the adhesion between the wiring pattern (2) and the insulating layer to be formed next, the wiring pattern 4 may be subjected to surface treatment. Surface treatments include, in addition to blackening treatment, chemical roughening treatment to form an oxide film of K CuOlCum0 on the surface, mechanical roughening treatment by sandblasting or pushing, and the like. Next, on the base &αυ including the first wiring patterns Q, an insulating layer (through) made of, for example, an ultraviolet curing resin is applied to the first wiring pattern (2).
The connecting portion (in the illustrated example 'l'11.

この絶縁層(ハ)の形成に際してはスキージを往復さi
る所謂往復印刷によって行う、これによれば第1の配線
パターンの肩の部分が隙になっても往復塗りのために陰
の部分も十分に被着し、ピンホールのない絶縁層(ハ)
が形成できる。
When forming this insulating layer (c), move the squeegee back and forth.
According to this method, even if the shoulder part of the first wiring pattern becomes a gap, the shadow part is sufficiently coated due to the reciprocating coating, resulting in an insulating layer without pinholes (c).
can be formed.

次に1第3図C−示すように裏面に生硬化状態の接着剤
c!荀を付した導電箔例えば銅箔(ハ)をロールラミネ
ート装置(例えば180℃に熱せられた対の熱ロール間
に挿通せしめる)を用いて基板(211上に積層合体す
る。この生硬化状態の接着剤(2)は、後に選択エツチ
ングする導電箔(例えば銅箔)のエツチング液におかさ
れず、有機溶剤に溶解し、縦1的に一子線、熱等の硬化
エネルギーを加えることKよって3次元硬化する性質を
有するものである。
Next, as shown in Fig. 3C, the adhesive c is in a green hardened state on the back side! A conductive foil, such as a copper foil (c), with a rib attached is laminated onto the substrate (211) using a roll laminating device (for example, inserted between a pair of heated rolls heated to 180° C.). The adhesive (2) should not be exposed to the etching solution of the conductive foil (for example, copper foil) to be selectively etched later, but should be dissolved in an organic solvent, and curing energy such as a single beam or heat should be applied vertically. It has the property of three-dimensional hardening.

次に、第3図りに示すように銅箔(至)に対して塩化第
1鉄の水溶液(エツチング液)を用いて選択エツチング
を施し、第2の導電箔ノくターン即ち配−パターン四を
形成する。このとき第2の配線ノ(ターンシ呻の第1の
配線)(ターン(2)との接続部(26m)は閉じた内
周面を有する形状(新開環状)ではなく、図示するよう
に第1の配線ノ(ターン(2)の接続i (22a) 
K部分的に重なるように例えば−示の例では略半円形状
に形成する。こり銅箔四の選択エツチング時、裏面の接
着剤(2)は除去されない。
Next, as shown in the third diagram, the copper foil (1) is selectively etched using an aqueous solution of ferrous chloride (etching solution) to form the second conductive foil pattern (4). Form. At this time, the connection part (26m) with the second wiring (first wiring of the turn) (turn (2)) is not shaped with a closed inner peripheral surface (newly opened ring shape), but with the first wiring as shown in the figure. Wiring no. (connection i of turn (2) (22a)
For example, in the example shown in the figure, they are formed into a substantially semicircular shape so that they partially overlap. When selectively etching the stiff copper foil 4, the adhesive (2) on the back side is not removed.

次に、第3図EK示すように両接続5(22り及び(2
6a) K対応する部分を除いてソルダーレジスト層(
2)を印刷によつ(被着形成する。このソルダーレジス
ト層(2)としては例えばエポキシアクリレート系の如
き紫外線硬化型の樹脂を用いることができ、接着剤(財
)の剥離に使用する有機溶剤におかされない性質を有す
る。そして、このソルダーレジスト層鰭及び第2の配線
パターン(2)の接続部(26畠)即ち銅箔をiスフと
して第1の配縁ノ(ターン(2)の接続部(22al)
 K対応する部分の露出する生硬化状態の接着剤(財)
を有機溶剤(例えば塩化メチレンの溶液)で選択的に溶
解剥離し、接続w(22蟲)の表面な露わKする。
Next, as shown in Fig. 3EK, both connections 5 (22 and (2)
6a) Solder resist layer (except for the part corresponding to K) (
2) is formed by printing. For this solder resist layer (2), an ultraviolet curing resin such as an epoxy acrylate resin can be used, and an organic resin used for peeling off the adhesive (goods) can be used. It has the property of not being affected by solvents.Then, the connection part (26 holes) between this solder resist layer fin and the second wiring pattern (2), that is, the copper foil, is used as an i-splash to connect the first wiring pattern (turn (2)). Connection part (22al)
K-corresponding part exposed green adhesive (goods)
is selectively dissolved and peeled off with an organic solvent (for example, a methylene chloride solution) to expose the surface of the connection (22).

次に、第1の配線パターン(2)の接続部(22m)の
中央部に、この場合少くと一@2の配−I(メーンーの
接続部(2651)が重ならない部分−を含むように、
プレス等の機械釣手RKより基材C11)を貫通するよ
うに電気部品挿入孔(2)を形成する□・ついで、半硬
化状態の接着剤(2)を電子線硬化、又は熱硬化して第
3図PK示す多層配線基板(2)を得る。なお、挿入孔
(2)は第゛3図Fの工程で行ったが、その他第3図ム
の銅箔の選択エツチング前に予め挿入孔(ハ)を形成し
て置くことも良い。これは、プレスで孔あけするときの
衝撃で接続部(22a)の基材Ωに対する接着強度が低
下するのを防止するためであり、銅箔が基材(2)の全
面に被着された状態のときにプレス孔あけすれば接着強
度の低下は回避される。
Next, in this case, at least one@2 wiring I (a portion where the main connection portion (2651) does not overlap) is placed in the center of the connection portion (22m) of the first wiring pattern (2). ,
Form an electrical component insertion hole (2) so as to penetrate the base material C11) using a mechanical hook RK such as a press. □・Next, semi-cured adhesive (2) is cured with electron beam or heat. A multilayer wiring board (2) shown in FIG. 3 PK is obtained. Although the insertion hole (2) was formed in the process shown in FIG. 3F, the insertion hole (C) may also be formed in advance before the selective etching of the copper foil shown in FIG. This is to prevent the adhesive strength of the connection part (22a) to the base material Ω from decreasing due to the impact when drilling with a press, and the copper foil is applied to the entire surface of the base material (2). If press holes are punched in this state, a decrease in adhesive strength can be avoided.

その後、第3図GK示すように電気部品(至)のリード
線311を挿入孔(2)内に挿入し、リード* C31
1と両接続部(22m)及び(26a)の3者を導電性
物質■によって電気的に接続する。尋電性物質国として
は、半田(半田フロー、手半田付け、ソルダークリーム
によるリフロー、ソルダーコータレベラー)、ガリウム
合金(当初作業温度においてペースト状をなし、そのi
経時的和合全孔し凝固する性質な壱する)、銀ペイント
、カーボンペイント、銅ペイント等による導電材を用い
得る。
Then, as shown in Fig. 3GK, insert the lead wire 311 of the electrical component (to) into the insertion hole (2), and
1 and both connecting portions (22m) and (26a) are electrically connected using a conductive material (2). Electrically conductive materials include solder (solder flow, manual soldering, reflow with solder cream, solder coater leveler), gallium alloy (forms in a paste form at the initial working temperature, and its i
Conductive materials such as silver paint, carbon paint, copper paint, etc., which have the property of becoming fully integrated and solidified over time, can be used.

かかる構成の多層配線基板(2)によれば、電気部品挿
入孔におけるリード線と配線パターン間の接続部分にお
いて、上層の配線パターン(2)の接続部(26m)が
環状でなく部分れに下層の配線パターン(2つの′接続
部(22m) K重なる如き半円形状に形成されている
ので、リード線との接続部分(2)の接着剤(至)の剥
離に際して剥離液のたまりがなく、又機械的ブラッシン
グも充分に行え、確実に接着剤(2)の剥離ができる。
According to the multilayer wiring board (2) having such a configuration, in the connection portion between the lead wire and the wiring pattern in the electrical component insertion hole, the connection portion (26m) of the upper layer wiring pattern (2) is not annular but partially formed in the lower layer. The wiring pattern (two connecting parts (22 m)) is formed in a semicircular shape so that they overlap, so there is no buildup of release liquid when removing the adhesive (to) of the connecting part (2) with the lead wire. In addition, mechanical brushing can be performed sufficiently, and the adhesive (2) can be reliably removed.

その結果、下層の接続部(221)の上面がきれいに露
われ、導電性物質(2)との電気的接触が良好となる。
As a result, the upper surface of the lower layer connecting portion (221) is clearly exposed and electrical contact with the conductive material (2) is improved.

又、溶融半田ディツプで導電性物質国を付ける場合には
下層のM!続部分鉤における空気が逃げ易くなり手出上
りが良く、良好な半田付けが出来る。同時に、上層の接
続部(26m)が小面積のために−その下の接着剤(2
)に残wするガス、水分、気泡(少なく、従ってこれら
による熱時のストレスの導電性物質(至)に与える影響
が少′l□□′1.1□ くなる、さらに接続部(261)を第1−のように環状
和した場合には、空気の逃けを考慮して内径dが決まり
、またその巾1も0.3−以上は必要なため、結果とし
て接続部(26m)を小さくするに4眠界が)・つた。
Also, when attaching conductive material with molten solder dip, the lower layer M! Air in the connecting hook can easily escape, resulting in good soldering and good soldering. At the same time, due to the small area of the upper layer connection (26 m) - the adhesive below (26 m)
), there are fewer gases, moisture, and air bubbles (therefore, the influence of heat stress caused by these on the conductive material is reduced), and the connection part (261) is reduced. When the annular sum is made as shown in the first example, the inner diameter d is determined by taking air escape into account, and the width 1 is also required to be 0.3 or more, so as a result, the connection part (26 m) is To make it smaller, there are 4 sleeping worlds)・Ivy.

しかし、本発明のように形成した接続部(26a)では
このような制限がないので、より高密度の配線パターン
が形成できる。
However, since the connection portion (26a) formed as in the present invention does not have such limitations, a higher density wiring pattern can be formed.

尚、上層の接続部(26りの形状としては第3図及び第
4図に示す半円形状の他に1例えば第5図の巾111E
Kした形状、あるいは第6図の形状でもよく、喪は環状
でなく下層の接続部(22m)と−都電なるもので慶・
れば任意形状を選ぶことができる。
In addition to the semicircular shape shown in FIGS. 3 and 4, the upper layer connection part (26) may have a width of 111E as shown in FIG. 5, for example.
It may be a K shape or the shape shown in Figure 6, and the mourning is not a ring shape but a lower connection part (22 m) - a metropolitan train that connects Kei.
You can choose any shape.

第7図は本発明の他の実施例である。本例においては、
$7図Aに示すように絶縁基材(21)の−主面に上記
と同様に例えば鋼箔による菖lの配線パターンリ4を形
成し、この配線パターンcr4に表m処理を施して後、
第7図BK示すように第1の配線パターン(2)の接続
部(22m)及び之に@接する基材(I’llの一部(
21M)を除いて絶#1樹脂層(ハ)を印刷により形成
する。この基材&1)上の全面K117図CK示すよう
に半硬化状態の接着剤(至)を付した例えば銅箔(ハ)
を積層合体し、次で、との銅箔(ハ)を選択エツチング
して第2の配線パターン(2)を形成する。このtIp
J2の配線パターン(2)の形成において、その接続部
(26りは第7図DK示すように下層の配線パターン(
2)の接続部(22m)上には重らないようK。
FIG. 7 shows another embodiment of the invention. In this example,
$7 As shown in FIG. ,
As shown in FIG. 7B, the connection part (22m) of the first wiring pattern (2) and a part of the base material (I'll) in contact with it (
Except #21M), an absolute #1 resin layer (c) is formed by printing. For example, a copper foil (C) with a semi-cured adhesive (C) applied to the entire surface of this base material &1) as shown in Figure CK.
The copper foils (c) are then selectively etched to form a second wiring pattern (2). This time
In forming the wiring pattern (2) of J2, its connection part (26) is connected to the lower layer wiring pattern (26) as shown in Figure 7DK.
2) Be careful not to overlap the connection part (22m).

即ち接続部(2初)に隣接する基材なυの部分(211
に形成する。従って両接続部(22り及び(26りは段
差を生じることなく略画−の状態で形成される。
In other words, the base material υ portion (211
to form. Therefore, both the connecting portions (22 and 26) are formed roughly as shown in the drawing without creating a step.

次に、第7図EK示すように両接続部(22り及び(2
6畠)を除い【ソルダーレジスト層V0を印刷によって
被着形成し、ソルダーレジスト層(2)及び上層の配線
パターン(7)の巌ks(26M)即ち鋼itマスクと
して、接続部(22m)上の半硬化状態の接着剤c!4
1を有機滴剤により溶解剥離する。次に下層の接続部(
22りの中央sKプレス等によって基材なυを貰通する
電気部品挿入孔(至)を形成する。そして接着剤(2)
を硬化する。その後、纂7図OK示すように’ljt’
Am品側のり一部IIcIIIを挿入孔(2)内に挿入
し、リード線C(mlと両接続部(22m)及び(26
a)を導電性物質−によって電気的に接続する。
Next, as shown in Fig. 7EK, both connection parts (22 and (2)
A solder resist layer V0 was formed by printing, and was used as a mask (26M) or a steel IT mask for the solder resist layer (2) and the upper layer wiring pattern (7) on the connection part (22m). Semi-cured adhesive c! 4
1 is dissolved and peeled off using an organic droplet. Next, the lower layer connection (
An electric component insertion hole (through) through which the base material υ is inserted is formed using a 22-inch central sK press or the like. and adhesive (2)
harden. Then 'ljt' as shown in Figure 7 OK
Insert part of the glue IIcIII on the Am product side into the insertion hole (2), and connect the lead wire C (ml) and both connecting parts (22m) and (26m).
a) are electrically connected by a conductive substance.

かかる構成の多層配麿基4に−は、その電気部品挿入孔
におけるリード線と配線パターン間の接続部分において
両接続部(22m)及び(26m)が路面−の状態で形
成さ−れているために、第3図の実施例の場合と同様に
一方の接続部(22&)上の接着剤(財)の剥離が容易
に且つ確実に行なわれ、接続部(22m)の表面がきれ
いに繕われ、導電性物質(2)との電気的接続が良好と
1.なる。さらに溶融半田ディツプに際しても空気のた
まりがなく半田上りが良く、また導−性物514に対す
る熱時°のストレス<i着剤(財)K残留するガス、水
分、気泡によるもの)の影響も少くなる。
In the multilayer wiring board 4 having such a configuration, both the connecting portions (22m) and (26m) are formed in the state of the road surface at the connecting portion between the lead wire and the wiring pattern in the electrical component insertion hole. Therefore, as in the case of the embodiment shown in FIG. 3, the adhesive on one of the joints (22&) can be easily and reliably peeled off, and the surface of the joint (22m) can be neatly repaired. , 1. Good electrical connection with the conductive substance (2). Become. Furthermore, when dipping into molten solder, there is no air accumulation and the solder finishes well, and there is little effect of stress on the conductive material 514 during heating (due to residual gas, moisture, and air bubbles in the adhesive). Become.

第8図及びwJ9図は本発明の他の実施例であり、上層
の配崗パターン(2)の接続ill (261)の径を
下層の接続* (22m)の径より小さくした状態で接
婢部(22M)の中央部にまで延長し、互に重なり合っ
た内接続部(22M)及び(26M)の中央において電
気部品挿入孔(至)を形成した場合で今る。この場合に
も溶融半田デイツプ時に接続部棹22すにお〜・てガス
ll1liりが生ぜず、良好な半釘會1.,44が可能
となる。
Figures 8 and 9 show other embodiments of the present invention, in which the diameter of the connection ill (261) of the upper layer grating pattern (2) is smaller than the diameter of the connection * (22 m) of the lower layer. This is a case in which an electric component insertion hole (to) is formed in the center of the internal connection portions (22M) and (26M) which overlap each other and extend to the center of the portion (22M). In this case, no gas leaks from the connecting rod 22 when dipping the molten solder, resulting in a good half-nail connection. , 44 becomes possible.

なお、第8図の接続部の形状は電気部品挿入孔(至)を
南する場合[[らず、例えば第10図に示すように率に
上下配線)(ターン(2)及び四間を接続する接続部分
に適用することもで會る。また、この単なる上下配縁パ
ターン(2)及び翰間の接続部分k)いて、第11図に
示すよ、うに上層の接続部(215fi)の形状を前述
の第4図と同様に下層の接続部(22M)kWA分的に
重なる゛よ5に半円形等の形状とすることもできる。
In addition, the shape of the connection part in Figure 8 is when connecting the electrical component insertion hole (to) to the south (for example, as shown in Figure 10, upper and lower wiring) (connecting turn (2) and It can also be applied to the connection part of the upper layer (215fi) as shown in FIG. Similarly to the above-mentioned FIG. 4, the connecting portion (22M) of the lower layer may have a semicircular shape or the like, overlapping by kW.

第12図及び第13図は本発明の更に他の実施例である
。なお、第3図と対応する部分には同一符号を付す6本
例においては、下層の導電箔バターシθカを単なるダミ
ーパターンとし、この導電箔パターンQDKかい【電気
部品挿入孔(至)を形層すると共に、導電箔パターン−
上に存するように上層の配線パターン(2)の接続部(
260を形成する。すなわち、この導電箔パターシθ力
は必ずしも他の配線パターンにつながっている必要はな
く、他から分離独立した所lll−電一パターンとする
ものである。
FIGS. 12 and 13 show still other embodiments of the present invention. In this example, the parts corresponding to those in FIG. Along with layering, conductive foil pattern-
As shown above, the connection part of the upper layer wiring pattern (2) (
Form 260. In other words, this conductive foil pattern θ does not necessarily have to be connected to other wiring patterns, but rather is a pattern that is separate and independent from the others.

この様に、配線λ、ターンの接続部(26m) 7にダ
ミーの導電箔Ap−νQ1)が存在すると、電気部品−
のリードmanを半田付けするための溶融半田デイツプ
時において、絶縁基材(2珍からの脱ガスを遮蔽するこ
とが出来、脱ガスの接続部(261) K対する影響が
回避され、銅箔による接続部(26M)の接着力が向上
する。因みに脱ガスの影響を受けると銅箔の接着力は低
下する。なお、接続部(26m)以外の配線パターンの
部分では、その上にソルダーレジスト層面が被着されて
いるのでその部分での配41 パターンの接着力の低下
は起らない。このことは前述した第3嫡〜第5図の構成
においても同様の効果を奏する。また配縁パターンの接
続部が大面積のパターンの場合にも、その下にダ2−の
導電箔パターンを形成すれば同様の効果が期待出来る。
In this way, if there is a dummy conductive foil Ap-νQ1) at the connection part (26m) 7 of the wiring λ and the turn, the electric component
During the molten solder dip for soldering the lead man, it is possible to shield outgassing from the insulating base material (2 pieces), avoiding the influence of degassing on the connection part (261), and using copper foil. The adhesive force of the connection part (26M) is improved.Incidentally, the adhesion force of copper foil decreases when affected by degassing.In addition, in the part of the wiring pattern other than the connection part (26M), the solder resist layer surface is placed on top of it. is applied, so the adhesive force of the pattern 41 does not decrease at that part.This has the same effect in the configurations shown in Figs. 3 to 5 described above. Even if the connecting portion is a pattern with a large area, the same effect can be expected if a conductive foil pattern of 2- is formed below it.

内、1例においては絶に樹脂層(2)を設置た構成であ
るが、絶に樹脂層(ハ)を省略して接着剤(2)をもっ
て上下配線パターン@及び(至)間を絶縁する絶縁層と
することも川−能である。
In one example, the resin layer (2) is definitely installed, but the resin layer (c) is definitely omitted and the adhesive (2) is used to insulate the upper and lower wiring patterns @ and (to). It is also Kawa-Noh's idea to use it as an insulating layer.

上述せる如く本発明によれば、簡単な構成により電気部
品挿入孔におけるI’)−ド線と配線ノ(ターン関の相
互接続が確実となり、また高密−配線)くターンの形成
も可能となり、尚信頼性のある多層配線基板が得られる
ものである。
As described above, according to the present invention, with a simple configuration, the interconnection between the I')-do wire and the wiring (turn) in the electrical component insertion hole is ensured, and it is also possible to form turns with high density wiring. Furthermore, a reliable multilayer wiring board can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本、発明の説明に、供する多層配線基板の一例
を示す一部断面とした斜視図、第2図はその接続部分の
断面図、第3図は本発明の多層配線基板の一実施例を示
す工@順の一部断面とした斜視図、鮪4図乃至第6図は
夫々その接続部の形状例を示す要部の平面図、@7図は
本発明の多層配線基板の他め実施例を示す工!!4順の
一部断面とした斜視図、餠8図及び亀9図は本発明の多
層配線基板の他の実施例を示す要部の断面−及び平面−
1第1θ図及び第11図は夫々本発明゛の他の実施例を
示す断面図、′第12図及び謔13図は本発明のさらに
他の実施例を示す断面図及び平面図である。 Qυは絶縁基材、(ハ)(2)卿は導電箔ノ(ターン、
(2)は電気部品挿入孔、(7)は電気部品、clll
はリード縁、64は導電性物質である。 四    11 ” 1J翼
FIG. 1 is a partially sectional perspective view showing an example of a multilayer wiring board used in the explanation of the present invention, FIG. 2 is a sectional view of its connecting portion, and FIG. Figures 4 to 6 are plan views of the main parts showing examples of the shapes of the connection parts, and Figure 7 is a partially sectional perspective view of the process of the present invention. Work to show another example! ! The perspective views in partial cross section in the order of 4, Figure 8 and Figure 9 are cross sections and plane views of essential parts showing other embodiments of the multilayer wiring board of the present invention.
Figures 1 and 11 are cross-sectional views showing other embodiments of the present invention, and Figures 12 and 13 are cross-sectional views and plan views showing still other embodiments of the present invention. Qυ is the insulating base material, (c) (2) is the conductive foil (turn,
(2) is an electrical component insertion hole, (7) is an electrical component, clll
is a lead edge, and 64 is a conductive material. 4 11” 1J wing

Claims (1)

【特許請求の範囲】 絶縁基材上に@1の導電箔パターン及び絶縁層を介して
なる第2の導電箔パターンを有し、前記a111の導電
箔パターンの前記絶縁層に被覆されない領域に電気部品
挿入孔が形成され、前記第2の導電箔パターンの接続部
が前記第1の導電箔パターンの領域に部分的に重るか、
もしくは隣接して。 形成されて成る多層配線基板。
[Scope of Claims] A conductive foil pattern @1 and a second conductive foil pattern formed by interposing an insulating layer are provided on an insulating base material, and an area of the conductive foil pattern a11 that is not covered with the insulating layer is provided with electricity. A component insertion hole is formed, and the connection part of the second conductive foil pattern partially overlaps the area of the first conductive foil pattern,
Or adjacent. A multilayer wiring board made of
JP57017742A 1982-02-05 1982-02-05 Multilayer circuit board Granted JPS58134498A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57017742A JPS58134498A (en) 1982-02-05 1982-02-05 Multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57017742A JPS58134498A (en) 1982-02-05 1982-02-05 Multilayer circuit board

Publications (2)

Publication Number Publication Date
JPS58134498A true JPS58134498A (en) 1983-08-10
JPH0472399B2 JPH0472399B2 (en) 1992-11-18

Family

ID=11952197

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57017742A Granted JPS58134498A (en) 1982-02-05 1982-02-05 Multilayer circuit board

Country Status (1)

Country Link
JP (1) JPS58134498A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5632480U (en) * 1979-08-20 1981-03-30

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5192409A (en) * 1975-02-10 1976-08-13 Uzumaki jetsutokumiawasehonpu

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5632480U (en) * 1979-08-20 1981-03-30

Also Published As

Publication number Publication date
JPH0472399B2 (en) 1992-11-18

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