JP2002231756A - Mounting structure for chip component - Google Patents
Mounting structure for chip componentInfo
- Publication number
- JP2002231756A JP2002231756A JP2001021902A JP2001021902A JP2002231756A JP 2002231756 A JP2002231756 A JP 2002231756A JP 2001021902 A JP2001021902 A JP 2001021902A JP 2001021902 A JP2001021902 A JP 2001021902A JP 2002231756 A JP2002231756 A JP 2002231756A
- Authority
- JP
- Japan
- Prior art keywords
- chip component
- opening
- resist layer
- chip
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L24/743—Apparatus for manufacturing layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L2224/743—Apparatus for manufacturing layer connectors
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、チップ部品をプリ
ント基板上に接着剤を用いて実装するための実装構造に
係り、特に、フリップチップのように下面に電極（バン
プ）を有するチップ部品をプリント基板上に自動マウン
トするのに好適なチップ部品の実装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure for mounting a chip component on a printed circuit board using an adhesive, and more particularly, to a chip component having an electrode (bump) on a lower surface such as a flip chip. The present invention relates to a chip component mounting structure suitable for automatic mounting on a printed circuit board.
【０００２】[0002]
【従来の技術】図４は従来より知られているチップ部品
の実装構造を示す平面図、図５は図４のＶ−Ｖ線に沿う
断面図である。これらの図に示すように、プリント基板
１の表面には位置合わせマーク２と接続ランド３および
引き回しパターン（図示せず）が設けられており、これ
らはプリント基板１の全面に設けられた銅箔をエッチン
グすることによりパターン形成されている。プリント基
板１上には引き回しパターンを覆うように絶縁性のレジ
スト層４が設けられており、このレジスト層４には方形
状の開口４ａが形成されている。開口４ａで囲まれた部
分はチップ部品５の実装領域であり、チップ部品５に導
通される接続ランド２は開口４ａ内に露出している。位
置合わせマーク２はチップ部品５の位置決め基準となる
もので、チップ部品５の実装領域に近い位置、すなわ
ち、開口４ａの相対向する隅部外側の近傍位置にそれぞ
れ設けられている。チップ部品５は例えばフリップチッ
プ（ＩＣ）であり、その下面に接続ランド２と対応する
電極５ａが設けられている。開口４ａはチップ部品５の
外形寸法と同じ大きさに設定されており、この開口４ａ
内に例えばエポキシ系の熱硬化性接着剤６を塗布してチ
ップ部品５をプリント基板１上に固定することにより、
対応する接続ランド２と電極５ａ同士が導通されてい
る。なお、図示省略されているが、プリント基板１上の
他の領域にはチップ抵抗やチップコンデンサ等のチップ
部品を含む種々の回路部品が実装されており、これら回
路部品の電極は他の接続ランドに半田付けされている。2. Description of the Related Art FIG. 4 is a plan view showing a mounting structure of a conventionally known chip component, and FIG. 5 is a sectional view taken along the line V--V in FIG. As shown in these figures, a positioning mark 2, a connection land 3 and a routing pattern (not shown) are provided on the surface of the printed board 1, and these are copper foil provided on the entire surface of the printed board 1. Is etched to form a pattern. An insulating resist layer 4 is provided on the printed board 1 so as to cover the wiring pattern, and a rectangular opening 4a is formed in the resist layer 4. A portion surrounded by the opening 4a is a mounting area of the chip component 5, and the connection land 2 electrically connected to the chip component 5 is exposed in the opening 4a. The alignment mark 2 serves as a positioning reference for the chip component 5, and is provided at a position near the mounting area of the chip component 5, that is, at a position near the outside of the opposing corner of the opening 4a. The chip component 5 is, for example, a flip chip (IC), and an electrode 5a corresponding to the connection land 2 is provided on a lower surface thereof. The opening 4a is set to the same size as the external dimensions of the chip component 5, and the opening 4a
The chip component 5 is fixed on the printed circuit board 1 by applying, for example, an epoxy-based thermosetting adhesive 6 therein.
The corresponding connection lands 2 and the electrodes 5a are electrically connected. Although not shown, various circuit components including chip components such as chip resistors and chip capacitors are mounted in other regions on the printed circuit board 1, and the electrodes of these circuit components are connected to other connection lands. Soldered.
【０００３】このような構成において、チップ部品５は
自動マウント装置を用いてプリント基板１上に実装され
るようになっている。この場合、未硬化状態の接着剤６
を開口４ａ内に塗布した状態で、位置合わせマーク２を
カメラで撮影することによって求められる位置データに
基づいてバキューム吸着したチップ部品５を開口４ａに
一致させた後、チップ部品５に所定の加圧力（例えば
１．２Ｋｇ）を加えながら所定温度（例えば２５０°
Ｃ）で加熱すると、接着剤６が硬化してチップ部品５を
プリント基板１上に固定することができ、それによって
チップ部品５の電極５ａは対応する接続ランド２に導通
される。In such a configuration, the chip component 5 is mounted on the printed circuit board 1 using an automatic mounting device. In this case, the uncured adhesive 6
Is applied to the opening 4a, the vacuum-adsorbed chip component 5 is made to coincide with the opening 4a based on position data obtained by photographing the alignment mark 2 with a camera, and then a predetermined amount is applied to the chip component 5. While applying a pressure (for example, 1.2 kg), a predetermined temperature (for example, 250 °)
When heated in (C), the adhesive 6 is cured and the chip component 5 can be fixed on the printed circuit board 1, whereby the electrodes 5 a of the chip component 5 are conducted to the corresponding connection lands 2.
【０００４】[0004]
【発明が解決しようとする課題】ところで、前述した従
来技術においては、位置合わせマーク２をレジスト層４
の開口４ａの外側近傍に設ける必要があるため、図４に
示すように、接着剤６を硬化する際の加圧力によって余
剰分の接着剤６が開口４ａからはみ出すと、この接着剤
６がレジスト層４の表面のぬれ性の影響を受けて位置合
わせマーク２と開口４ａ間で幅狭部分となり、その結
果、当該部分において硬化後の接着剤６にクラックが発
生し、チップ部品５を実装する際の接着の信頼性が低下
するという問題があった。また、レジスト層４の開口４
ａがチップ部品５の外形寸法と同じ大きさに設定されて
おり、これら開口４ａとチップ部品５間の隙間Ｇが狭く
なっているため、図５に示すように、接着剤６を硬化す
る際の加熱によってボイド（空気だまり）が発生する
と、このボイドを隙間Ｇから接着剤６の外部へ抜くこと
ができず、この点からも接着の信頼性が低下するという
問題があった。By the way, in the above-mentioned prior art, the alignment mark 2 is formed on the resist layer 4.
As shown in FIG. 4, when the excess adhesive 6 protrudes from the opening 4a due to the pressing force at the time of curing the adhesive 6 as shown in FIG. Under the influence of the wettability of the surface of the layer 4, a narrow portion is formed between the alignment mark 2 and the opening 4a. As a result, a crack occurs in the cured adhesive 6 in the portion, and the chip component 5 is mounted. There is a problem that the reliability of the bonding at the time is reduced. The opening 4 of the resist layer 4
a is set to the same size as the external dimension of the chip component 5, and the gap G between the opening 4a and the chip component 5 is narrowed. Therefore, as shown in FIG. When voids (air pools) are generated due to the heating, the voids cannot be removed from the gap G to the outside of the adhesive 6, and there is a problem in that the reliability of bonding is also reduced.
【０００５】本発明は、このような従来技術の実情に鑑
みてなされたもので、その目的は、接着の信頼性が高い
チップ部品の実装構造を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of such a situation of the prior art, and an object of the present invention is to provide a mounting structure of a chip component having high bonding reliability.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
に、本発明によるチップ部品の実装構造は、プリント基
板上にチップ部品の外形よりも大きな開口を有するレジ
スト層が設けられると共に、この開口内に前記チップ部
品の接続ランドと位置合わせマークとが設けられ、前記
チップ部品を前記開口の内部で熱硬化性の接着剤を用い
て前記プリント基板上に固定することにより、該チップ
部品の下面に設けられた電極と前記接続ランドとが導通
されるように構成した。In order to achieve the above object, a chip component mounting structure according to the present invention is provided with a resist layer having an opening larger than the outer shape of a chip component on a printed circuit board. A connection land of the chip component and an alignment mark are provided therein, and the chip component is fixed on the printed circuit board using a thermosetting adhesive inside the opening, whereby a lower surface of the chip component is provided. And the connection lands are electrically connected to each other.
【０００７】このように構成すると、位置合わせマーク
がレジスト層の開口内に設けられているため、接着剤の
塗布形状がレジスト層の表面のぬれ性の影響を受けずに
均一化され、硬化後の接着剤にクラックが発生すること
を防止できるのみならず、レジスト層の開口寸法がチッ
プ部品の外形よりも大きく設定されているため、加熱時
に発生するボイドが接着剤の外部に抜けやすくなり、し
たがって、チップ部品をプリント基板に実装する際の接
着の信頼性が向上する。[0007] With this configuration, since the alignment mark is provided in the opening of the resist layer, the application shape of the adhesive is made uniform without being affected by the wettability of the surface of the resist layer. In addition to preventing the occurrence of cracks in the adhesive, the opening size of the resist layer is set to be larger than the outer shape of the chip component, so that voids generated during heating are easily released to the outside of the adhesive, Therefore, the reliability of bonding when mounting the chip component on the printed board is improved.
【０００８】上記の構成において、位置合わせマークは
開口の内側の相対向する隅部にそれぞれ設けることが好
ましく、また、接着剤の塗布量は開口からはみ出さない
ように設定されていることが好ましい。In the above arrangement, the alignment marks are preferably provided at opposing corners inside the opening, and the amount of adhesive applied is preferably set so as not to protrude from the opening. .
【０００９】[0009]
【発明の実施の形態】以下、発明の実施の形態について
図面を参照して説明すると、図１はチップ部品を実装す
る前の要部平面図、図２はチップ部品の実装状態の要部
平面図、図３は図２のIII−III線に沿う断面図であり、
図４と図５に対応する部分には同一符号を付してある。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a main part before mounting a chip component, and FIG. 2 is a plan view of a main part of a mounted state of the chip part. FIG. 3 is a sectional view taken along line III-III in FIG.
4 and 5 are denoted by the same reference numerals.
【００１０】本実施形態例に係るチップ部品の実装構造
が前述した従来例と相違する点は、レジスト層４の開口
４ａをチップ部品５の外形寸法よりも大きく設定し、こ
の開口４ａの相対向する隅部の内側に位置合わせマーク
２を設けたことにあり、それ以外の構成は基本的に同様
である。すなわち、図１に示すように、フリップチップ
等のチップ部品５を実装する前のプリント基板１上に
は、同図の２点鎖線で示すチップ部品５の実装領域Ｓ１
内に接続ランド３が設けられると共に、この実装領域Ｓ
１の外側に一対の位置合わせマーク２が設けられてお
り、これら位置合わせマーク２と接続ランド３はいずれ
もレジスト層４の開口４ａで囲まれた領域Ｓ２の内側に
位置している。換言すると、レジスト層４の開口４ａが
チップ部品５の外形寸法よりも大きく設定されており、
この開口４ａの相対向する隅部の内側に位置合わせマー
ク２が設けられている。なお、接続ランド３から導出す
る引き回しパターン７はレジスト層４によって覆われて
おり、また、プリント基板１上の他の領域には図示せぬ
チップ抵抗やチップコンデンサ等のチップ部品を含む種
々の回路部品が実装されるようになっている。The mounting structure of the chip component according to the present embodiment is different from the above-described conventional example in that the opening 4a of the resist layer 4 is set to be larger than the outer dimensions of the chip component 5, and the opening 4a is opposed to the opening 4a. The positioning mark 2 is provided inside the corner to be formed, and the other configuration is basically the same. That is, as shown in FIG. 1, the mounting area S1 of the chip component 5 indicated by the two-dot chain line in FIG.
A connection land 3 is provided in the mounting area S
A pair of alignment marks 2 are provided outside of 1, and both the alignment marks 2 and the connection lands 3 are located inside a region S <b> 2 surrounded by the opening 4 a of the resist layer 4. In other words, the opening 4a of the resist layer 4 is set to be larger than the outer dimensions of the chip component 5,
Alignment marks 2 are provided inside opposing corners of the opening 4a. Note that the routing pattern 7 derived from the connection land 3 is covered with the resist layer 4, and other areas on the printed circuit board 1 include various circuits including chip components such as chip resistors and chip capacitors (not shown). Parts are to be mounted.
【００１１】図２と図３に示すように、このように構成
されたプリント基板１上の実装領域Ｓ１にチップ部品５
が自動マウント装置を用いて実装され、このチップ部品
５は例えばエポキシ系の熱硬化性接着剤６を用いてプリ
ント基板１に固定される。この場合、未硬化状態の接着
剤６を開口４ａ内に塗布した状態で、位置合わせマーク
２をカメラで撮影することによって求められる位置デー
タに基づいてバキューム吸着したチップ部品５を実装領
域Ｓ１に一致させた後、チップ部品５に所定の加圧力
（例えば１．２Ｋｇ）を加えながら所定温度（例えば２
５０°Ｃ）で加熱すると、接着剤６が硬化してチップ部
品５をプリント基板１上に固定することができ、それに
よってチップ部品５の電極５ａと対応する接続ランド２
とが導通される。As shown in FIGS. 2 and 3, the chip component 5 is mounted on the mounting area S1 on the printed circuit board 1 thus configured.
Is mounted using an automatic mounting device, and the chip component 5 is fixed to the printed circuit board 1 using, for example, an epoxy-based thermosetting adhesive 6. In this case, with the uncured adhesive 6 applied in the opening 4a, the vacuum-adsorbed chip component 5 matches the mounting area S1 based on the position data obtained by photographing the alignment mark 2 with a camera. After that, a predetermined pressure (for example, 1.2 kg) is applied to the chip component 5 while a predetermined temperature (for example, 2 kg) is applied.
When heated at 50 ° C.), the adhesive 6 is hardened and the chip component 5 can be fixed on the printed circuit board 1, whereby the connection land 2 corresponding to the electrode 5 a of the chip component 5 is formed.
Are conducted.
【００１２】かかるチップ部品５の実装時において、位
置合わせマーク２がレジスト層４の開口４ａ内に設けら
れているため、図２に示すように、接着剤６は開口４ａ
からはみ出すことなく領域Ｓ２内に満遍無く行き渡る。
したがって、接着剤６の塗布形状がレジスト層の表面の
ぬれ性の影響を受けずに均一化され、硬化後の接着剤６
にクラックが発生することを防止できる。また、レジス
ト層４の開口４ａがチップ部品５の外形寸法よりも大き
く設定されているため、図３に示すように、開口４ａと
チップ部品５間の隙間Ｇが広くなり、加熱時に発生する
ボイドが接着剤６の外部に抜けやすくなる。その結果、
チップ部品５のプリント基板１に対する接着の信頼性が
向上し、チップ部品５の導通不良や剥離といった不具合
を確実に防止することができる。しかも、接着剤６の塗
布量をコントロールして開口４ａからはみ出さないよう
に設定すれば、チップ部品５の実装後にレジスト層４が
吸湿して膨潤したとしても、それに伴って接着剤６まで
持ち上げられことがないため、接着の信頼性を長期に亘
って維持することができる。At the time of mounting such a chip component 5, since the alignment mark 2 is provided in the opening 4a of the resist layer 4, as shown in FIG.
It spreads all over the area S2 without protruding.
Therefore, the application shape of the adhesive 6 is made uniform without being affected by the wettability of the surface of the resist layer, and the adhesive 6 after curing is formed.
Cracks can be prevented. Further, since the opening 4a of the resist layer 4 is set to be larger than the outer dimension of the chip component 5, the gap G between the opening 4a and the chip component 5 is widened as shown in FIG. Is easily released to the outside of the adhesive 6. as a result,
The reliability of adhesion of the chip component 5 to the printed circuit board 1 is improved, and defects such as poor conduction and peeling of the chip component 5 can be reliably prevented. In addition, if the amount of the adhesive 6 is controlled so as not to protrude from the opening 4a, even if the resist layer 4 absorbs moisture and swells after the chip component 5 is mounted, it is lifted up to the adhesive 6 accordingly. Therefore, the reliability of the bonding can be maintained for a long time.
【００１３】[0013]
【発明の効果】本発明は、以上説明したような形態で実
施され、以下に記載されるような効果を奏する。The present invention is embodied in the form described above, and has the following effects.
【００１４】レジスト層の開口をチップ部品の外形寸法
よりも大きく設定し、この開口内にチップ部品の位置合
わせマークを設けたため、接着剤の塗布形状がレジスト
層の表面のぬれ性の影響を受けずに均一化され、硬化後
の接着剤にクラックが発生することを防止できるのみな
らず、加熱時に発生するボイドが接着剤の外部に抜けや
すくなり、したがって、チップ部品をプリント基板に実
装する際の接着の信頼性が向上する。Since the opening of the resist layer is set to be larger than the outer dimension of the chip component and the alignment mark of the chip component is provided in the opening, the shape of the adhesive applied is affected by the wettability of the surface of the resist layer. Not only prevents the adhesive from cracking after curing, but also makes it easier for voids generated during heating to escape to the outside of the adhesive. The bonding reliability is improved.
【図１】実施形態例に係るチップ部品の実装構造を示す
実装前状態の要部平面図である。FIG. 1 is a plan view of a main part in a pre-mounting state showing a mounting structure of a chip component according to an embodiment.
【図２】チップ部品の実装状態の要部平面図である。FIG. 2 is a plan view of a main part of a mounted state of a chip component.
【図３】図２のIII−III線に沿う断面図である。FIG. 3 is a sectional view taken along line III-III in FIG. 2;
【図４】従来例に係るチップ部品の実装構造を示す平面
図である。FIG. 4 is a plan view showing a mounting structure of a chip component according to a conventional example.
【図５】図４のＶ−Ｖ線に沿う断面図である。FIG. 5 is a sectional view taken along line VV of FIG. 4;
１ プリント基板 ２ 位置合わせマーク ３ 接続ランド ４ レジスト層 ４ａ 開口 ５ チップ部品 ５ａ 電極 ６ 接着剤 ７ 引き回しパターン Ｓ１ 実装領域 Ｓ２ 領域 DESCRIPTION OF SYMBOLS 1 Printed board 2 Alignment mark 3 Connection land 4 Resist layer 4a Opening 5 Chip component 5a Electrode 6 Adhesive 7 Leading pattern S1 Mounting area S2 area
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０５Ｋ 3/32 Ｈ０５Ｋ 3/32 Ｚ ５Ｆ０４７ Ｆターム(参考） 4M109 AA01 BA04 CA22 DB06 5E319 AA03 AB05 AC01 CC61 CD04 CD15 CD25 5E336 AA04 BB01 CC32 CC58 5E338 AA01 BB63 BB75 CC01 CD33 DD11 DD32 EE21 EE43 5F044 LL11 LL15 QQ09 5F047 AA17 FA21 FA71 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H05K 3/32 H05K 3/32 Z 5F047 F Term (Reference) 4M109 AA01 BA04 CA22 DB06 5E319 AA03 AB05 AC01 CC61 CD04 CD15 CD25 5E336 AA04 BB01 CC32 CC58 5E338 AA01 BB63 BB75 CC01 CD33 DD11 DD32 EE21 EE43 5F044 LL11 LL15 QQ09 5F047 AA17 FA21 FA71
Claims (3)
も大きな開口を有するレジスト層が設けられると共に、
この開口内に前記チップ部品の接続ランドと位置合わせ
マークとが設けられ、前記チップ部品を前記開口の内部
で熱硬化性の接着剤を用いて前記プリント基板上に固定
することにより、該チップ部品の下面に設けられた電極
と前記接続ランドとが導通されていることを特徴とする
チップ部品の実装構造。A resist layer having an opening larger than an outer shape of a chip component is provided on a printed circuit board;
A connection land of the chip component and an alignment mark are provided in the opening, and the chip component is fixed on the printed circuit board by using a thermosetting adhesive inside the opening, thereby forming the chip component. Wherein the electrode provided on the lower surface of the chip and the connection land are electrically connected to each other.
せマークが前記開口の内側の相対向する隅部にそれぞれ
設けられていることを特徴とするチップ部品の実装構
造。2. The chip component mounting structure according to claim 1, wherein the alignment marks are provided at opposing corners inside the opening.
接着剤の塗布量が前記開口からはみ出さないように設定
されていることを特徴とするチップ部品の実装構造。3. The chip component mounting structure according to claim 1, wherein the amount of the adhesive applied is set so as not to protrude from the opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001021902A JP3668686B2 (en) | 2001-01-30 | 2001-01-30 | Mounting structure of chip parts |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001021902A JP3668686B2 (en) | 2001-01-30 | 2001-01-30 | Mounting structure of chip parts |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002231756A true JP2002231756A (en) | 2002-08-16 |
| JP3668686B2 JP3668686B2 (en) | 2005-07-06 |
Family
ID=18887384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001021902A Expired - Lifetime JP3668686B2 (en) | 2001-01-30 | 2001-01-30 | Mounting structure of chip parts |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3668686B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008047926A (en) * | 2007-08-24 | 2008-02-28 | Nitto Denko Corp | Dicing die bond film |
| JP2012142567A (en) * | 2010-12-17 | 2012-07-26 | Sumitomo Electric Printed Circuit Inc | Printed wiring board and manufacturing method of the same |
| JP2017022300A (en) * | 2015-07-14 | 2017-01-26 | 新光電気工業株式会社 | Electronic component device and method of manufacturing the same |
-
2001
- 2001-01-30 JP JP2001021902A patent/JP3668686B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008047926A (en) * | 2007-08-24 | 2008-02-28 | Nitto Denko Corp | Dicing die bond film |
| JP2012142567A (en) * | 2010-12-17 | 2012-07-26 | Sumitomo Electric Printed Circuit Inc | Printed wiring board and manufacturing method of the same |
| JP2017022300A (en) * | 2015-07-14 | 2017-01-26 | 新光電気工業株式会社 | Electronic component device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3668686B2 (en) | 2005-07-06 |
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