JPS58119672A - Semiconductor non-volatile memory device - Google Patents

Abstract

PURPOSE:To enhance the degree of integration and to charge high floating gates with high energy, by making the width of the floating gates equal to or narrower than the width of a drain region or a source region. CONSTITUTION:''Writing'' is made by applying a high voltage to a drain 3 and a control gate 2. For example, when the ratio of channel width/channel length of a transistors Tr 1 and Tr 3 is made to be 0.5mum and the ratio of channel width/channel length of a transistor Tr 2 is made to be 10/5mum, the parallel resistance of the transistors Tr 1 and Tr 3 becomes the high resistance about 10 times the transistor Tr 2. Therefore, when the high voltage is applied to the drain and the control gate of the floating gate type memory Tr 2, high energy electrons generated in the channel region exceed the energy gap in the conduction band of an insulating body 8, reach the floating gates 1, and charge the floating gates 1. The writing is performed in this way. ''Erase'' is performed by irradiating ultraviolet rays or light close to the ultraviolet rays thereby discharging the electrons in the floating gates.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor non-volatile semiconductor device.

Conventionally, a device of this type is shown in FIG. 1. Figure 1-) is a planar pattern diagram of an N-channel floating gate nonvolatile memory. +2H;
j second layer conductor (hereinafter referred to as control gate), 11) is the drain side N-type impurity diffusion layer, 14) is the source IINI
I impurity diffusion layer, (5) floating gate of drain side N type impurity diffusion layer (3)) (1) Downward digging region, +6
1tl! The region where the N-type impurity diffusion layer (4) on the source side sinks under the floating gate (1), (91t'! The area between the floating gates (1) of the memories that meet each other, αO)
The extension part 11 from the channel part, α) is the width of the diffusion region.

Figure 1(b) is a sectional view of the main part of Figure 1(a).
) is a P-silicon substrate, and (8) is an insulator. Next, the operation will be explained. Charging the floating gate (1) with electrons is called "writing," and releasing electrons from the floating gate (1) is called "erasing." First, "writing"
A high voltage is applied to the drain (3) and control gate (2), and high energy electrons generated in the channel region are transferred to the insulator (8).
Floating gate across the conduction band energy gap (1)
This is done by charging the floating gate (1). "Erasure" is performed by emitting electrons in the floating gate (lj) by irradiating with ultraviolet light or light close to the wavelength of the ultraviolet light.For reading, floating gate I
Since the threshold value of the memory transistor differs depending on the presence or absence of charge in ll, the amount of current flowing between the p-drain and source changes due to this, which is used to amplify this amount of current with a sense amplifier to distinguish between 10 and 11 pins. It is done by doing.

Since the conventional floating gate II nonvolatile memory is configured as described above, the width (Z) of the diffusion region of the drain (3) and source (4) must be adjusted to make one transistor and one memory.
T-Provided inside the width of the long side of the floating gate (1), the extended portion of the floating gate (1) (101ffi) must be at least 3 to 4 μm, and when multiple memory transistors are configured, The floating gate spacing (9) with the mesori transistor requires at least 3 to 4 μm, so the floating gate distance (9) is required. There was a drawback.

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional technology.To9, the width of the floating gate is made narrower than the width of the drain region and the source region, N, etc., and the integration K is increased. The present invention provides a semiconductor non-volatile memory device in which a floating gate can be charged with a high-energy transistor.

An embodiment of the present invention will be described below with reference to FIG.

FIG. 2(a) is a plan pattern diagram 611 of the N-channel floating gate type nonvolatile memory of the present invention.
1u floating gate), (is the control gate, (81 is the drain side N-type impurity diffusion layer, C4) is the source side N-type impurity diffusion layer, (fig (61 is the floating gate of the drain and source N-type impurity diffusion layers) ) Insertion area under fil, 01)
The region between the diffusion regions of the drain and source regions +3H41 located outside the H floating gate (1) and the adjacent memory in the comparison portion (2) -% (Zb) is the diffusion region width. @2 Figure (b) is a sectional view of the main part of Figure 2 (1). (7) is a P-type silicon substrate, (8) is an insulator. ◇ FIG. 3 is an equivalent circuit diagram of one memory portion of the N-channel floating gate nonvolatile memory of the present invention shown in FIG. tllti floating goo), +! li control gate,
+11? ! drain, (4) source, (Tr4)
rL A memory transistor with a floating gate (1) for charge storage, (Tri)i control gate (2) and a drain extending beyond the floating gate +11 'i with the width as the "channel length" of the transistor.

Transistor provided on the side of the floating gate (1) with the width of the protruding part (6) of the source diffusion region as the "channel width" of the transistor, (Tr3) u The side of the floating gate on the opposite side of Tri It is the same transistor as (Trl) above.

Next, the operation will be explained. "Write" is the drain (3
) and the control gate (2), which applies a high voltage to the channel width of the transistors (Tri) and (Tr3).
Channel length ratio f o, s,” 5. Un, channel width/channel length ratio of transistor (Tr2) is 11
0/Iμm, transistor (Tri) and (T
10 of the transistor (Tr 2 ) to the parallel resistance of r3)
Therefore, a high voltage is applied to the drain and control gate of the floating gate memory (Trjl), and a high voltage is generated in the cutout channel. Across the energy gap of floating gate (lb) (lc)
(ld) reached floating gate (lb) (lc) (ld)
The 0 "erase" performed by pointing t\rt is performed by emitting electrons in the floating gate by irradiating the element with ultraviolet rays or a wavelength close to ultraviolet rays, as in the conventional method. Next, read out transistor (Tri) (Tr).
The amount of current flowing from the drain (3) to the source (4) of the transistor (Tr2) changes depending on the presence or absence of charge in the floating gate of the transistor (Tr2). Therefore, data of 161 jl# is output through the sense amplifier.

Next, a method of making cloth according to an embodiment of the present invention will be explained with reference to Figure 4. First, a first conductive layer, which will become a floating gate (1), is formed using a mask υ.Next, an insulating film is stacked on this first conductive layer, and a control gate (2) is formed using a mask α4. The conductive material in the first layer of the helmet is etched using the mask α4, and the parts other than the mask α are removed to form the floating gate (
1) Dope impurities with mask 4 for zero-order impurity diffusion to form drain and source regions (fall).
14) '0 In this case, the V area for all impurity diffusion lines coincides with or does not include the floating gate (1) made with the mask α, at least.
must not.

In the above embodiment, both sides of the floating gate are within the impurity diffusion region, but as shown in FIG. Good too. In this case, the equivalent circuit diagram is No. 5l6)
Compared to the previous embodiment, only one high-resistance transistor is used, and the basic operation is exactly the same.

Furthermore, as shown in FIG. 6(&), at least one side of the floating gate may coincide with the ring of the impurity diffusion region. In this case, the equivalent circuit diagram of field H is as shown in FIG. , the spacing between adjacent mesoli on at least one side is narrower than in conventional memory9, the integration density in the direction of the control gate has been significantly revised, and high-energy charges can be charged to the floating gate. It has this excellent effect.

[Brief explanation of the drawing]

Figure 1 (-2) is a planar pattern diagram of a conventional N-channel floating gate nonvolatile memory, Figure 1 (a) is a cross-sectional view of the main part of Figure 4 (Figure 1-), and Figure 2 (a) is a cross-sectional view of the main part of this. A planar pattern diagram of an N-channel floating gate type nonvolatile memory according to an embodiment of the invention, Figure 92(b) is a sectional view of the main part, and Figure 3 is an equivalent of the floating gate type nonvolatile memory of Figure 2. A circuit diagram, FIG. 4 is a mask plan view showing the manufacturing method of the floating gate type non-volatile memory shown in FIG. 2, FIG.
b) is a planar pattern diagram and its equivalent circuit diagram showing another embodiment of the present invention, (1) t; The source impurity diffusion layer (7) is a silicon substrate (81r! insulator). In the figure, the same reference numerals indicate the same or equivalent parts. Agent Makoto Kuzuno - Figure 1 < 0) Second Fig. 3 Fig. 4 Fig. 5 (a and Fig. 6 (b)) Mr. Commissioner of the Japan Patent Office 1. Indication of the case Patent Application No. 100-100 2. Title of the invention Semiconductor non-volatile memory device 3. Amendment Table 5, Detailed explanation of the invention column 6 of the specification subject to amendment, Contents of amendment (1) Corrected r(Zb)J to r(Z)J on page 4, line 14 of the specification. (2) Insulator (8c) J on page 6, line 19 of the specification is corrected to "insulator (8)." (3) Specification, page 6, lines 20 to 6 The second line on the page says “Floating game.
) (tb) (tc) (ta) and floating gate (l
b) It is carried out by charging (lc) (1d). ” is changed to “The floating gate (1) is reached and the floating gate (
This is done by charging 1). ” he corrected. that's all

Claims (1)

[Claims] A semiconductor substrate of a first conductivity type, a source region and a drain region provided at a predetermined distance from each other on this semiconductor substrate, and a source region and a drain region provided so as to cover at least the surface of the semiconductor substrate between the source region and the drain region. a first insulating film, a floating gate provided on the first insulating film, and a control gate provided on the floating gate via a second insulating film, the width of the floating gate being equal to the width of the drain. A semiconductor non-volatile one-day device characterized in that the width is equal to or narrower than the width of a region and a source region.