CN102386188A - Three-dimensional array memory architecture with diodes in memory strings - Google Patents

Abstract

The invention discloses a three-dimensional array memory architecture with diodes in the memory strings. A three-dimensional memory device is described herein that includes a plurality of ridge-like stacks of elongated semiconductor materials separated by insulating layers arranged in series and coupled to sense amplifiers through decoding circuitry. The diode is coupled to the bit line structure at either the string select or common source select of the string. The strip of semiconductor material has side surfaces on the sides of the ridge-like stack. A plurality of conductive lines arranged as word lines and coupled to the row decoder extend orthogonally over the plurality of ridge-like stacks. Memory elements are located at the intersection regions of the multi-layer array between the side surfaces of the strip of semiconductor material in the stack and the conductive lines.

Description

Three-dimensional array memory architecture with diodes in memory strings

technical field

The present invention relates to high density memory devices, and more particularly to memory devices having multiple layers of planar memory cells to provide a three-dimensional array.

Background technique

As the critical dimensions of devices in integrated circuits shrink to the limits of conventional memory cell technology, designers are turning to multi-overlapping planar technology for memory cells to achieve higher storage densities and lower cost per bit. For example, thin-film transistor technology has been applied in charge-trapping memory. For example, see the paper "A multi-Layer Stackable Thin-FilmTransistor (TFT) NAND-Type Flash Memory" by Lai et al., IEEE Int'l Electron Device Meeting, December 11-13, 2006; and the paper "Three DimensionallyStack NAND Flash Memory Technology Using Stacking Single Crystal SiLayers on ILD and TANOS structure for Beyond 30nm Node" by Jung et al., IEEE Int′l Electron Device Meeting, December 1, 2006 ~13 days.

In addition, the rendezvous point array technology has also been applied in the antifuse memory. For example, the paper "512-Mb PROM with a Three Dimensional Array of Diode/Anti-fuse Memory Cells" by Johnson et al., IEEE J.of Solid- state Circuits, vol.38, no.11, November 2003. In the design described by Johnson et al., multiple layers of wordlines and bitlines are used with storage elements at intersection points. The memory element includes a p+ polysilicon anode connected to the word line, and an n+ polysilicon cathode connected to the bit line, and the cathode and the anode are separated by an antifuse material.

In the process described by Lai, Jung, et al., multiple critical photolithographic steps are used for each storage layer. Therefore, the number of critical photolithographic steps required to fabricate such a device would be a multiple of the number of memory layers it uses. Therefore, although a higher density can be achieved by using a three-dimensional array, the higher manufacturing cost also limits the scope of application of this technology.

Another technology that uses the vertical NAND gate memory cell structure in the charge trapping memory has also been described in the paper "Bit Cost Scaleable Technology with Punch and Plug Process for Ultra High Density Flash Memory" by Tanaka et al., 2007 Symposium on VLSI Technology Digest of Technical Papers , pp.14-15, June 12-14, 2007, described. Among the structures described by Tanaka et al., including a multi-gate field-effect transistor structure with a vertical channel that operates like a NAND gate, using a silicon-oxygen-oxynitride-oxygen-silicon (SONOS) type charge-trapping memory cell structure, in each A memory location is created at the gate/vertical channel interface. The memory structure is based on arranging pillars of semiconductor material as vertical channels to form a multi-gate memory cell, with a lower select gate close to the substrate and an upper select gate above it. A plurality of horizontal control gates are formed using planar electrode layers intersecting the pillars. The planar electrode layer as the horizontal control gate does not require critical photolithography, thereby saving costs. However, many critical photolithographic steps are still required for each vertical memory cell. In addition, the number of control gates in the multilayer structure of this method is still limited, which is determined by factors such as vertical channel conductivity, programming and erasing operations used, and so on.

There is therefore a need to provide a low manufacturing cost three dimensional integrated circuit memory structure that includes reliable, very small memory elements.

Contents of the invention

The technology described herein is a memory device that includes an integrated circuit substrate, multiple stacks of elongated semiconductor materials, multiple word lines, memory elements, and diodes. The plurality of elongated semiconductor material stacks extend out of the integrated circuit substrate, the plurality of stacked layers have a ridge shape and include at least two elongated semiconductor materials separated by an insulating layer to form different plane positions among the plurality of plane positions. The plurality of word lines are arranged to be perpendicular to the plurality of stacked layers and conform to the shape of the plurality of stacked layers, so that a three-dimensional array is established at the intersection points of the surfaces of the plurality of stacked layers and the plurality of word lines Rendezvous area. The memory element is in the intersection region, which establishes the three-dimensional array of memory cells accessible via the strip of semiconductor material and the plurality of word lines, the memory element is arranged in series between the bit line structure and the source line between. The diode is coupled to the string between the string of memory cells and one of the bit line structure and the source line.

In some embodiments, the series is a series of NAND gates.

In some embodiments, a combination selection of a specific bit line in the bit line structure, a specific source line in the source, and a specific word line in the plurality of word lines can identify the three-dimensional array A specific memory cell in the memory cell.

In some embodiments, the diode is coupled to the string between the string of memory cells and the bit line structure.

In some embodiments, the diode is coupled to the string between the string of memory cells and the source line.

Some embodiments include a string select line and a ground select line. The serial selection line is arranged to be orthogonal to and conformal to the plurality of stacks, such that a serial selection device is established at the intersection of the surfaces of the plurality of stacks with the serial selection line . The ground selection line is arranged to be perpendicular to the plurality of laminated layers and conform to the shape of the plurality of laminated layers, so that a ground selection device is established at the intersection points of the surfaces of the plurality of laminated layers and the ground selection line.

In some embodiments, the diode is coupled between the string select device and the bit line structure. In some embodiments, the diode is coupled between the ground selection device and the source line.

In some embodiments, the storage elements in the intersection region respectively include a tunneling layer, a charge trapping layer and a blocking layer.

In some embodiments, the strip of semiconductor material includes n-type silicon and the diode includes a p-type region in the strip of semiconductor material. In some embodiments, the strip of semiconductor material includes n-type silicon and the diode includes a p-type plug in contact with the strip of semiconductor material.

Some embodiments include logic to apply a reverse bias to diodes in unselected strings of memory cells when programming the memory cells.

Another object of the present invention is to provide a memory device comprising an integrated circuit substrate and a three-dimensional array of memory cells in the integrated circuit substrate. The three-dimensional array includes a stack of memory cells in series of NAND gates; and diodes coupled to the series are interposed between the series of memory cells and one of a bit line structure and a source line.

In some embodiments, the combined selection of a specific bit line in the bit line structure, a specific source line in the source electrodes, and a specific word line in the plurality of word lines can identify the three-dimensional array. A specific memory cell within a memory cell.

In some embodiments, the diode is coupled to the string between the string of memory cells and the bit line structure. In some embodiments, the diode is coupled to the string between the string of memory cells and the source line.

Some embodiments include a string select device between the bit line structure and the string of memory cells; and a ground select device between the source line and the string of memory cells.

In some embodiments, the diode is coupled between the string select device and the bit line structure. In some embodiments, the diode is coupled between the ground selection device and the source line.

In some embodiments, the charge trapping structures in the intersection region respectively include a tunneling layer, a charge trapping layer and a blocking layer.

Another object of the present invention is to provide a method for operating a three-dimensional NAND flash memory. The steps include applying a programming adjustment bias sequence to the three-dimensional NAND flash memory, the three-dimensional array including diodes coupled to the strings such that the diodes are interposed between the memory cell strings and the bit line structure and the source line structure between one.

One or more unselected strings that do not contain memory cells to be programmed by the programming adjustment bias are charged. In various embodiments, the charging is from the source line structure or from the bit line structure. In different embodiments, this charging is via a diode or without a diode. The bit line structure and source line structure are decoupled from the unselected string and a selected string including one or more memory cells to be programmed by the programming adjustment bias. A programming voltage is applied to the unselected string and the selected string via one or more word lines of the memory cells to be programmed by the programming adjustment bias.

The storage elements are arranged in series between the bit line structure and the common source line, and include diodes coupled to the series, between the respective series of memory cell series and the bit line structure and the source line between one of them. A first select gate (eg, string select gate SSL) may be coupled between the corresponding bit line structure and the memory cell string, and a second select gate (eg, ground select gate GSL) may be coupled to between the corresponding common source line and the series of memory cells. The diode can be coupled between the first select gate and the corresponding bit line structure. The diode can be coupled between the second select gate and the corresponding common source line.

The three-dimensional memory device includes a plurality of ridge-shaped stacks, which are formed by a plurality of strips of semiconductor material separated by insulating layers, arranged in series in the example described here, which can be connected with the sensing circuit through the decoding circuit. Amplifier coupling. The plurality of elongated semiconductor materials have side surfaces on sides of the plurality of stacked layers. In this example, the plurality of conductive lines serving as word lines may be coupled to the column decoders, arranged orthogonally on the plurality of stacked layers. The lead has a surface (eg, bottom surface) conforming to the plurality of stacks. Such a conformal surface configuration results in the creation of a multi-layer intersection region where the side surface of the strip of semiconductor material meets the plurality of wires. The memory element is disposed in the intersection area between the side surface of the strip of semiconductor material and the wire. The memory element is programmable, similar to the programmable resistance structure or the charge trapping structure described in the following embodiments. The combination of the conformal wire, the memory element and the elongated semiconductor material within the stack in a specific intersection area constitutes a stack of memory cells. The result of this array structure can provide the three-dimensional array of memory cells.

The plurality of ridge-shaped stacks and the plurality of wires form memory cells by means of automatic alignment. For example, strips of semiconductor material in multiple ridge-like stacks can be defined using a single etch mask, resulting in the formation of interleaved channels, which can be relatively deep and side surfaces of the strips of semiconductor material in the stack Either vertically or aligned with the sloped sides of the ridge forming the channel. The memory element may be formed using one or more layers of material deposited across the stack and using other processes that do not require critical alignment steps. In addition, a plurality of wires can be deposited on one or more layers of the material used as the memory element by means of antegrade deposition, and then perform an etching process using the single etching mask to define the wires. As a result, only one alignment step is used to define the long strips of semiconductor material in the stack, and one alignment step to define the multiple wires.

In addition, a three-dimensional, buried channel, junction-free NAND flash structure based on bandgap engineered polysilicon-silicon oxide-silicon nitride-silicon oxide-silicon oxide (BE-SONOS) technology is also described herein.

The invention provides a very efficient array decoding method for the three-dimensional vertical gate NAND flash design. Its die size can fit into current floating-gate NAND flash designs while scaling densities to one megabit.

The invention also provides a feasible circuit design framework for ultra-high-density three-dimensional NAND gate flash design.

The objects, features, and embodiments of the present invention will be described with accompanying drawings in the following sections of the embodiments.

Description of drawings

Figure 1 shows a schematic diagram of a three-dimensional memory structure described here, which includes a plurality of long semiconductor material planes parallel to the Y axis and arranged in a plurality of ridge-like stacks, a storage layer on the side of the long semiconductor material, and multiple The strip has a conductive line with a bottom surface conforming to the underlying plurality of ridge-like stacks.

FIG. 2 shows a cross-sectional view of the memory cell structure in FIG. 1 along the Z-X plane.

FIG. 3 shows a cross-sectional view of the memory cell structure of FIG. 1 along the Y-X plane.

FIG. 4 shows a schematic diagram of an antifuse-based memory having the structure of FIG. 1 .

Figure 5 shows a schematic diagram of a three-dimensional NAND flash memory structure described here, which includes a plurality of strips of semiconductor material planes parallel to the Y axis and arranged in a plurality of ridge-shaped stacks, a charge trapping storage layer on the strip A side surface of the semiconductor material, and a plurality of wires having a bottom surface in conformity with the underlying plurality of ridge-shaped stacks.

FIG. 6 shows a cross-sectional view of the memory cell structure in FIG. 5 along the Z-X plane.

FIG. 7 shows a cross-sectional view of the memory cell structure of FIG. 5 along the Y-X plane.

FIG. 8 shows a schematic diagram of a NAND flash memory having the structure of FIG. 5 and FIG. 23 .

FIG. 9 shows a schematic diagram of an alternative embodiment of a three-dimensional NAND flash memory structure similar to FIG. 5, in which the layer of memory material is removed from between the wires.

FIG. 10 shows a cross-sectional view of the memory cell structure in FIG. 9 along the Z-X plane.

FIG. 11 shows a cross-sectional view of the memory cell structure of FIG. 9 along the Y-X plane.

FIG. 12 shows a schematic cross-sectional view of a first stage of a process for manufacturing a memory device as shown in FIGS. 1 , 5 and 9 .

FIG. 13 shows a schematic cross-sectional view of a second stage of the process for manufacturing a memory device as shown in FIG. 1 , FIG. 5 and FIG. 9 .

FIG. 14A is a schematic cross-sectional view showing a third stage of the process for manufacturing a memory device as in FIG. 1 .

FIG. 14B is a schematic cross-sectional view showing a third stage of the process for manufacturing a memory device as in FIG. 5 .

FIG. 15 shows a schematic cross-sectional view of a third stage of the process for manufacturing a memory device as shown in FIG. 1 , FIG. 5 and FIG. 9 .

FIG. 16 shows a schematic cross-sectional view of a fourth stage of the process for manufacturing a memory device as shown in FIG. 1 , FIG. 5 and FIG. 9 .

17 shows a simplified block diagram of an integrated circuit according to an embodiment of the present invention, wherein the integrated circuit includes a three-dimensional programmable resistive read-only memory array with row, column and plane decoding circuits.

FIG. 18 shows a simplified block diagram of an integrated circuit according to another embodiment of the present invention, wherein the integrated circuit includes a three-dimensional NAND flash memory array with row, column and plane decoding circuits.

FIG. 19 is a tunneling electron microscope image of a portion of a three-dimensional NAND flash memory array.

FIG. 20 shows a cross-sectional view between the memory string and the bit line structure with diodes in the string in a three-dimensional NAND flash memory structure.

Figure 21 shows a schematic diagram between a bit line structure and a memory string with diodes in this string in a three-dimensional NAND flash memory structure, which shows two memory cell planes, each plane has 6 charge trapping memory cells Arranged into a NAND gate configuration.

FIG. 22 shows a timing diagram of a programming operation for an array similar to that of FIG. 20 .

FIG. 23 shows a cross-sectional view of a three-dimensional NAND flash memory structure with diodes between the bit line structure of the string and the memory string during a read operation.

FIG. 24 shows a cross-sectional view of a three-dimensional NAND flash memory structure with diodes between the bit line structure of the string and the memory string during a programming operation.

FIG. 25 shows a schematic diagram of a three-dimensional NAND flash memory structure with diodes between the bit line structure and memory strings in the strings, which uses polysilicon plugs as diodes.

FIG. 26 shows a cross-sectional view between the source line structure and the memory string with diodes in the string in a three-dimensional NAND flash memory structure.

FIG. 27 shows a schematic diagram of a three-dimensional NAND flash memory structure with diodes between the source line structure of the string and the memory string, showing two planes of memory cells.

FIG. 28 is a timing diagram showing a first example of a programming operation for the array in FIG. 21 .

FIG. 29 shows a timing diagram of a second example of the programming operation of the array shown in FIG. 21 .

FIG. 30 is a timing diagram showing another example of the programming operation of the array shown in FIG. 21 .

FIG. 31 shows a schematic diagram of a three-dimensional NAND flash memory structure similar to that in FIG. 27. In this figure, it is shown that the string includes diodes formed between the source line structure and the memory string.

FIG. 32 shows a timing diagram of an example of a programming operation of the array shown in FIG. 31 .

33A and 33B are tunneling electron microscope photographs of a portion of a 3D NAND flash memory array.

FIG. 34 is a graph of current-voltage (IV) characteristics of a polysilicon diode measured experimentally.

FIG. 35 is a characteristic diagram of the reading current of a polysilicon diode connected to a three-dimensional NAND gate memory measured experimentally.

FIG. 36 is a diagram of the programming inhibition characteristic of a polysilicon diode connected to a three-dimensional NAND memory, which is experimentally measured.

FIG. 37 shows the influence of the source bias voltage effect of the polysilicon diode connected to the three-dimensional NAND memory on the programming disturbance measured experimentally.

FIG. 38 shows the influence of the turn-on gate voltage effect of the polysilicon diode connected to the three-dimensional NAND memory on the programming disturbance measured experimentally.

FIG. 39 is a schematic diagram of the block erase switching current of a polysilicon diode connected to a three-dimensional NAND memory, measured experimentally.

FIG. 40 is a schematic diagram of the experimentally measured current-voltage characteristics of a polysilicon diode connected with a three-dimensional NAND gate memory in programming and erasing states with different numbers of programming/erasing cycles.

FIG. 41 is a schematic diagram of the threshold voltage distribution of a polysilicon diode connected to a three-dimensional NAND memory, which has programmed/erased memory cells distributed in a lookup table, measured experimentally.

[Description of main component symbols]

10, 110: insulation layer

11～14, 111～114: strip semiconductor material

15, 115: storage materials

16, 17, 116, 117: wire

18, 19, 118, 119: metal silicides

20, 120: channel

21～24, 121～124: insulating material

25, 26, 125, 126: active area

30～35, 40～45, 70～78, 80, 82, 84: storage unit

51~56: Lamination of long strip semiconductor materials

60(60-1, 60-2, 60-3), 61, 160~162: word line

86, 87: source line

90~95: block selection transistor

97, 397: tunneling dielectric layer

98, 398: charge storage layer

99, 399: blocking dielectric layer

83: Serial selection line

85, 88, 89: Serial select transistors

106, 107, 108: bit lines

128, 129, 130: source/drain regions

210, 212, 214: insulating layer

211, 213: Semiconductors

215: storage material layer

250: Ridge Laminate

315: charge trapping layer

225: wire

226, 1426: metal silicide

875, 975: integrated circuits

860: Three-Dimensional Programmable Resistor ROM Array with Diodes in Strings

960: 3D NAND Flash Array with Diodes in Strings

858, 958: planar decoder

859, 959: serial selection line

861, 961: column decoder

862, 962: word line

863, 963: row decoder

864, 964: bit line

865, 965, 867, 967: bus

866, 966: Sense Amplifier/Data Input Structure

874, 974: other circuits

869, 969: State agencies

868, 968: Bias adjustment supply voltage

871, 971: data input line

872, 972: data output line

410, 1410: Substrate

1412～1414: Strip semiconductor materials

1415, 1515: area

1425-1 to 1425-n: wires

1427: Serial selection line SSL

1428: Integral source line GSL

1449: P+ implantation area

1450, 1451, 1550, 1551: embolization

1491: Conductive Materials

1492, 1592: Diodes

1106: Serial selection line

1110～1113: diode

1160～1162: Wire

1170～1175, 1180, 1182: storage unit

1190, 1191: Ground selection transistors

1196, 1197: Serial select transistors

Detailed ways

The following description of the embodiments of the present invention is illustrated with reference to FIG. 1 to FIG. 41 .

FIG. 1 shows a schematic diagram of a 2×2 memory cell portion of a three-dimensional programmable resistance memory array. In the figure, the filling material is omitted to clearly show the stacked layers of long strips of semiconductor material and the orthogonal wires constituting the three-dimensional array. In this illustration, only two planes are shown. However, the number of planes can be extended to a very large number. As shown in FIG. 1, the memory array is formed on an integrated circuit substrate above a semiconductor or other structure (not shown) with an insulating layer 10 underneath. The memory array comprises a plurality of elongated stacks 11 , 12 , 13 , 14 of semiconductor material separated from each other by insulating material 21 , 22 , 23 , 24 . The stack is in the shape of a ridge and extends along the Y-axis in the figure, so the strips of semiconductor materials 11-14 can be configured as bit lines and extend out of the substrate. The long strips of semiconductor material 11, 13 can be used as bit lines on the first storage plane, and the long strips of semiconductor material 12, 14 can be used as bit lines on the second storage plane. A layer of memory material 15 , such as an antifuse material, is coated on the strip of semiconductor material in this example, and is formed at least on the sidewalls of the strip of semiconductor material in other examples. A plurality of conductive lines 16, 17 are orthogonal to these elongated stacks of semiconductor material. A plurality of wires 16, 17 have conformal surfaces to these strips of semiconductor material stacks, and are filled in channels (eg 20) defined by these stacks, and between the strips of semiconductor materials 11-14 The intersection of the side surfaces between the stack and the plurality of conductors 16, 17 defines the interface area of the multilayer array. A layer of metal silicide (such as tungsten silicide, cobalt silicide, titanium silicide) 18 , 19 is formed on the upper surfaces of the plurality of wires 16 , 17 .

The storage material layer 15 may include antifuse materials such as silicon dioxide, silicon oxynitride or other silicon oxides, for example, with a thickness on the order of 1 to 5 nanometers. Other antifuse materials may also be utilized, such as silicon nitride. The strips of semiconductor materials 11-14 may be semiconductor materials with a first conductivity type (eg, p-type). The wires 16, 17 may be a semiconductor material with a second conductivity type (eg, n-type). For example, the strips of semiconductor materials 11 - 14 can use p-type polysilicon and the wires 16 , 17 can use heavily doped n+ type polysilicon. The width of the strip of semiconductor material must be sufficient to provide the depletion region required for diode operation. Thus, the memory cell includes a PN junction formed between the slivers of polysilicon and the wire rectifiers in a three-dimensional array of junctions, the PN junction having a programmable antifuse layer between the cathode and anode. In other embodiments, different programmable resistive memory materials may be used, including switching metal oxides such as tungsten oxide over tungsten or strips of semiconductor material doped with metal oxides. Such materials can be programmed and erased, and can be used in storage operations that reside in multiple memory cells.

FIG. 2 shows a cross-sectional view along the Z-X plane of the memory cell at the intersection of the wire 16 and the strip of semiconductor material 14 . The active regions 25 and 26 form two sides of the elongated semiconductor material 14 and are located between the wire 16 and the elongated semiconductor material 14 . In a natural state, the antifuse memory material layer 15 has high resistance. After programming, the antifuse memory material collapses, causing one or both of the active regions 25, 26 within the antifuse memory material to return to a low resistance state. In the embodiment described here, each memory cell has two active regions 25 , 26 forming either side of the strip of semiconductor material 14 . FIG. 3 shows a cross-sectional view along the X-Y plane of the memory cell where the wires 16, 17 meet the strip of semiconductor material 14. As shown in FIG. The figure shows the current path from the word line defined by the wire 16 through the antifuse storage material layer 15 to the long strip of semiconductor material 14 .

The flow of electrons is shown by the dotted line in FIG. 3 , enters the p-type strip semiconductor material 14 from the n+ wire 16, and reaches the sense amplifier along the strip semiconductor material 14 (dashed arrow), and can be measured at the sense amplifier with Indicates the status of the selected memory cell. In a typical embodiment, silicon oxide with a thickness of about 1 nanometer is used as the antifuse material, and the on-chip control circuit in FIG. . The read pulse is applied by using the on-chip control circuit in FIG. 17 , which includes a pulse of 1-2 volts and a pulse width related to the configuration. This read pulse can be much shorter than the programming pulse.

Figure 4 shows two planes of memory cells, each plane having six memory cells. These memory cells are represented by diode designations with a layer of antifuse material (represented by dashed lines) between the cathode and anode. The two memory cell planes are composed of wires 60 and 61 as the first word line WLn and the second word line WLn+1 and first, second and third long wires as the bit lines BLn, BLn+1 and BLn+2 respectively. The junctions of the stacks of strips of semiconductor material 51, 52, 53, 54 and 55, 56 define the first and second layers of the array. The first plane of memory cells includes the memory cells 30, 31 on the elongated stack 52 of semiconductor material, the memory cells 32, 33 on the elongated stack 54 of semiconductor material, and the memory cells on the elongated stack 56 of semiconductor material. Units 34, 35. The second plane of memory cells includes memory cells 40, 41 on the elongated stack 51 of semiconductor material, memory cells 42, 43 on the elongated stack 53 of semiconductor material, and memory cells on the elongated stack 55 of semiconductor material. Units 44, 45. As shown in the figure, the wire 60 is used as a word line WLn, which includes vertically extending 60-1, 60-2, 60-3 corresponding to the material in the trench between the stacks in FIG. Three instantiated strips of semiconductor material stacks in each plane are coupled. An array can be implemented with many layers as described herein to form very high density memory approaching or reaching megabits per chip.

Figure 5 shows a schematic diagram of a 2 x 2 memory cell portion of a three-dimensional programmable resistive memory array, with fill material in the figure to clearly represent the stacks of long strips of semiconductor material and orthogonal conductors that make up the three-dimensional array relation. In this diagram, only two layers are shown. However, the number of levels can be extended to a very large number. As shown in FIG. 5, the memory array is formed on an integrated circuit substrate above a semiconductor or other structure (not shown) with an insulating layer 110 underneath. The memory array comprises a plurality of elongated stacks of semiconductor material 111 , 112 , 113 , 114 separated from each other by insulating material 121 , 122 , 123 , 124 . The stack is in the shape of a ridge and extends along the Y-axis in the figure, so the strips of semiconductor material 111 - 114 can be configured as bit lines and extend out of the substrate. The long strips of semiconductor material 111, 113 can serve as bit lines on the first storage plane, and the long strips of semiconductor material 112, 114 can serve as bit lines on the second storage plane.

The insulating material 121 between the strips of semiconductor material 111 and 112 in the first stack and the insulating material 123 between the strips of semiconductor material 113 and 114 in the second stack have an equivalent diameter of about 40 nanometers or more. Oxide thickness (EOT), wherein the equivalent oxide thickness (EOT) is the thickness of the insulating material multiplied by the ratio of the dielectric constant of silicon oxide to the insulating layer to convert the oxide thickness. The term "about 40 nanometers" as used herein is to account for variations of the order of about 10% in processing typical of such devices. The thickness of the insulating layer has an important effect on reducing the interference between adjacent memory cells in this structure. In some embodiments, the equivalent oxide thickness (EOT) of the insulating material can be as small as 30 nanometers and still provide sufficient separation between adjacent layers.

A layer of storage material 115, such as a dielectric charge trapping structure, is coated on the strip of semiconductor material in this example. A plurality of conductive lines 116, 117 are orthogonal to the elongated stacks of semiconductor material. A plurality of wires 116, 117 have surfaces conforming to these strips of semiconductor material stacks, and are filled in channels (for example, 120) defined by these stacks, and between the strips of semiconductor materials 111-114 The intersection of the side surfaces between the laminate and the plurality of conductors 116, 117 defines the interface region of the multilayer array. A layer of metal silicide (such as tungsten silicide, cobalt silicide, titanium silicide) 118 , 119 is formed on the upper surface of the plurality of wires 116 , 117 .

The nanowire mosfet configuration is also configured in this way by providing a nanowire or nanotube structure in the channel region above the wires 111-114, as described in the paper "Impact of a Process Variation on Nanowire and Nanotube DevicePerformance", IEEE Transactions on Electron Device, Vo1.54, No.9, September 11-13, 2007, hereby cited as reference data.

Thus, a SONOS type memory cell configured as a three-dimensional array of NAND flash arrays can be formed. The source, drain and channel are formed in silicon strip semiconductor materials 111-114, and the storage material layer 115 includes a tunneling dielectric layer 97 of silicon oxide (O), a charge storage layer 98 of silicon nitride (N), an oxide A blocking dielectric layer 99 of silicon (O) and conductive lines 116, 117 of polysilicon (S).

The strips of semiconductor materials 111 - 114 can be p-type semiconductor materials and the wires 116 , 117 can use the same or different semiconductor materials (eg p+ type). For example, the strips of semiconductor materials 111 - 114 can be p-type polysilicon or p-type epitaxial single crystal silicon, and the wires 116 , 117 can use relatively densely doped p+ polysilicon.

Alternatively, the strips of semiconductor materials 111 - 114 can be n-type semiconductor materials and the wires 116 , 117 can use semiconductor materials of the same or different conductivity type (eg, p+ type). This n-type semiconductor material arrangement results in a charge-trapping memory cell of the buried-channel depletion regime. For example, the strips of semiconductor materials 111 - 114 can be n-type polysilicon, or n-type epitaxial single crystal silicon, and the wires 116 and 117 can use relatively densely doped p+ polysilicon. The doping concentration of a typical n-type elongated semiconductor material is about 10 ¹⁸ /cm ³ , and the range of applicable embodiments is about 10 ¹⁷ /cm ³ to 10 ¹⁹ /cm ³ . The use of n-type strips of semiconductor material is preferred for junctionless embodiments, as the conductivity along the string of NAND gates can be improved and thus allow higher read currents.

Therefore, the memory cell including field effect transistors has charge storage structures formed in the three-dimensional array structure of the intersection points. Using elongated semiconductor material and wire thickness on the order of about 25 nanometers, and the pitch of stacked layers with a ridge shape is also on the order of 25 nanometers, devices with tens of layers (for example, thirty layers) can reach mega (10 ^{12 )} in a single chip. ) bit capacity.

The storage material layer 115 may contain other charge storage structures. For example, a bandgap engineered (BE) SONOS charge storage structure can be used instead, which includes a dielectric tunneling layer 97 and has an inverted U-shaped valence band between layers at 0V bias. In one embodiment, the multi-layer tunneling layer includes a first layer called a hole tunneling layer, a second layer called an energy band compensation layer and a third layer called an isolation layer. In this embodiment, the hole tunneling layer 97 includes a silicon dioxide layer formed on the side surface of the elongated semiconductor material, which can be formed by a method such as in-situ steam generation (ISSG), and selectively Nitriding can be performed by nitric oxide annealing after deposition or by adding nitric oxide during deposition. The thickness of the silicon dioxide in the first layer is less than 20 angstroms, and preferably less than 15 angstroms, and in a representative embodiment is 10 or 12 angstroms.

In this embodiment, the energy band compensating layer comprising a silicon nitride layer is located on the hole tunneling layer, and it utilizes techniques such as low pressure chemical vapor deposition (LPCVD) at 680° C. using dichlorosilane (dichlorosilane, DCS) and ammonia precursors to form. In other processes, the band compensation layer includes silicon oxynitride, which is formed using a similar process and a nitrous oxide precursor. The thickness of the silicon nitride layer in the energy band compensation layer is less than 30 angstroms, and preferably 25 angstroms or less.

In this embodiment, an isolation layer comprising a silicon dioxide layer is located on the band compensation layer, and it is formed using a method such as LPCVD high temperature oxide HTO deposition. The thickness of the silicon dioxide layer in the isolation layer is less than 35 angstroms, and preferably 25 angstroms or less. Such a three-layer tunneling dielectric layer produces an "inverted U"-shaped valence band energy level.

The valence band level at the first location is such that the electric field is sufficient to induce hole tunneling through the thin region between the first location and the semiconductor body (or strip of semiconductor material) interface, and it is also sufficient to elevate the valence band after the first location energy level, so as to effectively eliminate hole tunneling phenomenon in the composite tunneling dielectric layer after the first one. This structure, in addition to establishing the "inverted U"-shaped valence band of the three-layer tunneling dielectric layer, can also achieve electric field-assisted high-speed hole tunneling, which can also be used in the absence of an electric field or for other operating purposes (such as In the case of reading data from a memory cell or programming an adjacent memory cell), only a small electric field is induced, effectively preventing charge loss through the composite tunneling dielectric layer structure.

In a representative device, the memory material layer 115 comprises a bandgap engineered (BE) composite tunneling dielectric layer comprising a first layer of silicon dioxide having a thickness of less than 2 nanometers, a layer of silicon nitride having a thickness of is less than 3 nanometers and a silicon dioxide layer thickness of the second layer is less than 4 nanometers. In one embodiment, the composite tunneling dielectric layer includes an ultra-thin silicon oxide layer O1 (for example, less than or equal to 15 angstroms), an ultra-thin silicon nitride layer N1 (for example, less than or equal to 30 angstroms), and an ultra-thin silicon oxide layer O2 ( For example, less than or equal to 35 angstroms), and it can increase the valence band energy level by about 2.6 eV with a compensation of 15 angstroms or less from the interface with the semiconductor body or the long semiconductor material. The O2 layer can separate the N1 layer from the charge trapping layer by a low valence band region (high hole tunneling barrier) and a high conduction band level—a second compensation (eg, about 30 angstroms to 45 angstroms from the interface) . Since the second location is far from the interface, the electric field sufficient to induce hole tunneling can increase the energy level of the valence band after the second location, so that it can effectively eliminate the hole tunneling barrier. Therefore, the O2 layer does not seriously interfere with the electric field-assisted hole tunneling, and at the same time, it can enhance the ability of the engineered tunneling dielectric structure to block charge loss at low electric fields.

The charge trapping layer in the storage material layer 115 in this embodiment includes a silicon nitride layer with a thickness greater than 50 angstroms, including, for example, a silicon nitride layer with a thickness of about 70 angstroms, and is formed by means such as LPCVD. Other charge-trapping materials and structures can also be used in the present invention, including, for example, silicon oxynitride ( _SixOyNz ), high-silicon-content nitrides, _high -silicon-content _oxides , including trapping embedded nanoparticles. layers and so on.

The blocking dielectric layer in the storage material layer 115 in this embodiment is silicon oxide, its thickness is greater than 50 angstroms, and includes 90 angstroms in this embodiment, and a wet furnace for wet conversion of silicon nitride can be used tube oxidation process. In other embodiments, high temperature oxide (HTO) or silicon oxide deposited by LPCVD may be used. Other blocking dielectric materials such as high-k dielectric materials such as aluminum oxide may also be used.

In a representative embodiment, the thickness of the silicon dioxide in the hole tunneling layer is 13 angstroms; the thickness of the silicon nitride layer in the energy band compensation layer is 20 angstroms; the thickness of the silicon dioxide layer in the isolation layer is 25 angstroms ; The thickness of the silicon nitride layer of the charge trapping layer is 70 angstroms; and the blocking dielectric layer may be silicon oxide with a thickness of 90 angstroms. The gate material of the wires 116, 117 may be p+ polysilicon (with a work function of 5.1 eV).

FIG. 6 shows a cross-sectional view of the charge trapping memory cell formed at the intersection of the wire 116 and the elongated semiconductor material 114 along the Z-X plane of the memory cell. The active regions 125 and 126 form two sides of the long semiconductor material 114 between the wire 116 and the long semiconductor material 114 . In the embodiment depicted in FIG. 6 , each memory cell is a double gate field effect transistor with two active regions 125 , 126 formed on either side of the strip of semiconductor material 114 .

FIG. 7 shows a cross-sectional view of the charge trapping memory cell formed at the intersection of the wire 116 and the elongated semiconductor material 114 along the X-Y plane of the memory cell. The current path to the strip of semiconductor material 114 is also shown. The flow of electrons, shown by the dotted lines in the figure, is along the p-type strip semiconductor material to the sense amplifier, which can be measured to indicate the state of the selected memory cell. The source/drain regions 128, 129, 130 between the conductive lines 116, 117 used as word lines can be "junctionless", that is, the doping type of the source/drain does not need to be connected with the channel under the word line. The doping types of the regions are different. In this "junctionless" embodiment, the charge trapping field effect transistor may have a p-type channel structure. In addition, in some embodiments, the source/drain doping can be formed by self-alignment implantation after defining the word lines.

In an alternative embodiment, the strips of semiconductor material 111-114 can use lightly doped n-type semiconductor bodies in a "junction-free" arrangement, resulting in the formation of buried-channel field-effect transistors that can operate in depletion mode, the charge trapping Memory cells have a naturally shifted to lower threshold voltage distribution.

Figure 8 shows two planes of memory cells, each with 9 charge-trapping memory cells arranged in a NAND configuration, which is a representative example of a cube, which may include many planes and many word lines. The two memory cell planes are composed of wires 160, 161 and 162 as word lines WLn-1, WLn and WLn+1, which are first, second and third elongated semiconductor material stacks, respectively.

The first plane of memory cells includes memory cells 70, 71 and 72 in a series of NAND gates on top of the elongated stack of semiconductor material, and memory cells 73, 74 and 75 in a series of NAND gates , and are located on the elongated semiconductor material stack, and the memory cells 76, 77 and 78 are in a series of NAND gates, and are located on the elongated semiconductor material stack. In this illustration, the second plane of memory cells corresponds to the base plane of the cube and includes memory cells (eg, 80, 82, and 84) arranged in series of NAND gates in a similar manner to the first plane.

As shown in the figure, the wire 161 as the word line WLn includes a vertical extension corresponding to the material in the channel 120 between the stacks in FIG. The memory cells (for example, memory cells 71, 74 and 77 in the first plane) of the interface region in the channel of the first plane are coupled.

The bit line and the source line are located at opposite ends of the memory string. Bitlines 106, 107 and 108 are connected to different stacks in the memory string by control of bitline signals BLn-1, BLn and BLn+1. A source line 86 controlled by signal SLn in this arrangement terminates the series of NAND gates in the upper half plane. Similarly, source line 87 controlled by signal SLn+1 in this arrangement terminates the lower half-plane train of NAND gates.

In this arrangement, string select transistors 85, 88 and 89 are connected between respective strings of NAND gates and bit lines BLn-1, BLn and BLn+1. A string select line 83 is parallel to the word lines.

In this arrangement, block select transistors 90-95 couple the series of NAND gates to one of the source lines. In this example, the ground selection line GSL is connected to the block selection transistors 90 - 95 and may be implemented in a manner similar to the wires 160 , 161 and 162 . In some embodiments, the string select transistor and block select transistor may use the same dielectric stack as the gate oxide in the memory cell. In other embodiments, a typical gate oxide may be used instead. In addition, the channel length and width can be adjusted according to design requirements to provide proper switching functions of these transistors.

Fig. 9 shows a schematic diagram of an alternative structure similar to that of Fig. 5, and the same reference numerals are used in similar structures in the figure and will not be described again. The difference between FIG. 9 and FIG. 5 is that the surface 110A of the insulating layer 110 and the side surfaces 113A, 114A of the elongated semiconductor materials 113, 114 are exposed between the wires (such as 160) used as word lines after the word lines are formed by etching. . Therefore, the storage material layer 115 can be completely or partially etched between the word lines without affecting the operation. In some structures, however, general etching through the storage material layer 115 as described herein is not required to form the dielectric charge trapping structure.

FIG. 10 shows a cross-sectional view of a memory cell similar to FIG. 6 along the Z-X plane. FIG. 10 is identical to FIG. 6, showing the structure in the memory cell of FIG. 9, in this cross-sectional view the same as the cross-sectional view of the structure implemented in FIG. 5. FIG. FIG. 11 shows a cross-sectional view of a memory cell similar to FIG. 7 along the X-Y plane. The difference between FIG. 11 and FIG. 7 is that the memory material in regions 128a, 129a, and 130a along the side surface (eg, 114A) of the strip of semiconductor material 114 is removed.

Figures 12 to 16 show a flowchart of the basic process stages for implementing a 3D memory array as described herein using only 2 patterning masking steps that are critical to the alignment of the array. In FIG. 12 , the structure after alternately depositing insulating layers 210 , 212 , 214 and semiconductor layers 211 , 213 is shown. For example, the semiconductor layer can be formed in the array area of the chip by using doped semiconductor deposited all over the surface. According to different embodiments, polysilicon or epitaxial single crystal silicon with n-type or p-type doping can be used for the semiconductor layer. The interlayer insulating layers 210 , 212 , 214 can be, for example, silicon dioxide, other silicon oxides or silicon nitride. These layers can be formed using many different methods, including techniques such as low pressure chemical vapor deposition (LPCVD), which are well known in the industry.

FIG. 13 shows the result of the first photolithographic patterning step, which is used to define a plurality of ridge-shaped elongated semiconductor material stacks 250, wherein the elongated semiconductor material is composed of semiconductor layers 211, 213 and is formed by insulating layers 210, 212, 214 are separated. Trenches with very deep and high aspect ratios can be formed between multilayer stacks using photolithography-based processes with the application of carbon-containing hard masks and reactive ion etching.

14A and FIG. 14B respectively show a programmable resistance memory structure including, for example, an antifuse memory cell structure and a programmable charge trapping memory structure including, for example, a silicon-oxygen-nitride-oxygen-silicon (SONOS) type memory cell structure. Sectional view of a stage.

FIG. 14A shows the result of depositing a memory material 215 across the surface of an embodiment of a programmable resistive memory structure including the single-layer antifuse memory cell structure shown in FIG. 1 . Alternatively, an oxidation process may be performed without blanket deposition to form oxide on the exposed sides of the elongated semiconductor material, where the oxide acts as the memory material.

FIG. 14B shows the result of depositing a storage material 315 in the embodiment of the programmable resistance storage structure including the multilayer charge trapping structure shown in FIG. 4. The multilayer charge trapping structure includes a tunneling layer 397, a charge trapping layer 398 and a blocking layer 399. As shown in FIG. 14A and FIG. 14B , the storage material layers 235 and 315 are deposited on the ridge-shaped elongated semiconductor material stack (250 in FIG. 13 ) in a conformal manner.

FIG. 15 shows the result after the step of filling the high aspect ratio channel with conductive material, such as with n-type or p-type doping, which is used as a conductor for a word line, deposited to form layer 225 . Additionally, a layer of suicide 226 is formed over layer 225 in embodiments using polysilicon. As shown in the figure, a high aspect ratio deposition technique such as polysilicon by low pressure chemical vapor deposition (LPCVD) is used in this embodiment to fill the trenches between the ridge-like stacks, even very narrow high aspect ratio Channels on the order of 10 nanometers are also feasible.

FIG. 16 diagrammatically shows the result of the second photolithographic patterning step used to define the plurality of conductive lines 260 used as word lines in the three-dimensional memory array. This second photolithographic patterning step uses a single mask to define the critical dimension for etching high aspect ratio trenches between lines in the array without the need to etch through the ridge-like stack. Polysilicon can be etched using an etch process that is highly selective to polysilicon and silicon oxide or silicon nitride. Therefore, an alternative etching process can be performed using the same mask used to etch the semiconductor and insulating layers, the process stopping at the bottom insulating layer 210 .

An optional process step includes forming a hard mask over a plurality of conductive lines including word lines, ground select lines, and string select lines. The hard mask can be formed using a relatively thick nitride or other material that blocks ion implantation. After the hard mask is formed, ion implantation may be performed to increase the dopant concentration in the strips of semiconductor material and thereby reduce the resistance along the current paths along the strips of semiconductor material. By using controlled implant energy, implants can be caused through the bottom strip of semiconductor material, and each of the upper strips of semiconductor material in the stack.

Afterwards, the hard mask is removed to expose the silicide above the plurality of wires. After the interlayer dielectric layer is formed over the array, vias are formed and filled therein, for example using plugs of tungsten. The upper metal line as the bit line BL is patterned and connected to the decoding circuit. A three-dimensional decoding circuit is established in the manner shown in the figure, using a word line, a bit line, and a source line to access a selected memory cell. See US Patent No. 6,906,940 entitled "Plane Decoding Method and Device for Three Dimensional Memories".

To program a selected antifuse type memory cell, the selected word line is biased to -7V in this embodiment, unselected word lines can be set to 0V, and selected bit lines can also be set to 0V, Unselected bit lines may be set to 0V, selected source lines may be set to -3.3V, and unselected source lines may be set to 0V. In order to read a selected memory cell, the selected word line is biased to -1.5V in this embodiment, the unselected word lines can be set to 0V, the selected bit lines can also be set to 0V, the unselected bits line can be set to 0V, the selected source line SL can be set to -3.3V, and the unselected source line can be set to 0V.

Figure 17 shows a simplified schematic diagram of an integrated circuit according to an embodiment of the present invention. The integrated circuit 875 includes the use of a three-dimensional programmable resistive read-only memory (RRAM) array 860 as described herein on a semiconductor substrate. A column decoder 861 is coupled and electrically communicated with a plurality of word lines 862 arranged along the column direction of the memory array 860 . The row decoder 863 is in electrical communication with a plurality of bit lines 864 (or the previously described serial selection lines) arranged along the row direction of the memory array 860 to perform read and program data operations on the memory cells from the array 860 . A plane decoder 858 is coupled to the previously described source string select line 859 (or previously described bit line) on the array 860 plane. The address is provided by bus 865 to row decoder 863 , column decoder 861 and plane decoder 858 . The sense amplifier and data input structures in block 866 are coupled to row decoder 863 via data bus 867 . Data is provided to the data input line 871 by an input/output port on the integrated circuit 875 , or input to the data input structure in block 866 by other internal/external data sources of the integrated circuit 875 . Other circuits 874 are included within the integrated circuit 875, such as general purpose processors or special purpose application circuits, or modules combined to provide SoC functions supported by programmable resistive memory cell arrays. Data is provided by the sense amplifier in block 866 to the integrated circuit 875 via the data output line 872 , or to other data terminals inside/outside the integrated circuit 875 .

The controller used in this embodiment uses the bias adjustment state mechanism 869 and controls the application of bias adjustment supply voltages generated or provided by the voltage supply source or block 868, such as read and program voltages. The controller can be implemented using special purpose logic circuitry, as is well known to those skilled in the art. In an alternative embodiment, the controller includes a general purpose processor that can be used on the same integrated circuit to execute a computer program to control the operation of the device. In yet another embodiment, the controller is a combination of special purpose logic and a general purpose processor.

Figure 18 shows a simplified schematic diagram of an integrated circuit according to an embodiment of the invention. The integrated circuit 975 includes the use of the three-dimensional NAND flash memory array 960 described herein on a semiconductor substrate. A column decoder 961 is coupled and electrically communicated with a plurality of word lines 962 arranged along the column direction of the memory array 960 . The row decoder 963 is in electrical communication with a plurality of bit lines 964 (or the previously described serial selection lines) arranged along the row direction of the memory array 960 to perform read and program data operations on the memory cells from the array 960 . A plane decoder 958 is coupled to the previously described string select line 959 (or previously described bit line) on the array 960 plane. The address is provided by bus 965 to row decoder 963 , column decoder 961 and plane decoder 958 . The sense amplifier and data input structures in block 966 are coupled to row decoder 963 via data bus 967 . Data is provided to the data input line 971 by an input/output port on the integrated circuit 975 , or input to the data input structure in block 966 by other internal/external data sources of the integrated circuit 975 . In this exemplary embodiment, other circuits 974 are included within the integrated circuit 975, such as general purpose processors or special purpose application circuits, or modules combined to provide SoC functions supported by NAND flash arrays. Data is provided by the sense amplifier in block 966 to the integrated circuit 975 via the data output line 972 , or to other data terminals inside/outside the integrated circuit 975 .

The controller used in this embodiment uses the bias adjustment state mechanism 969, and controls the application of the bias adjustment supply voltage generated or provided by the voltage supply source or block 868, such as reading, programming, erasing erase, erase verify, and program verify voltages. The controller can be implemented using special purpose logic circuitry, as is well known to those skilled in the art. In an alternative embodiment, the controller includes a general purpose processor that can be used on the same integrated circuit to execute a computer program to control the operation of the device. In yet another embodiment, the controller is a combination of special purpose logic and a general purpose processor.

19 is a cross-sectional view of a tunneling electron microscope of a part of the charge trapping NAND gate device of an 8-layer vertical channel thin film transistor energy gap engineering polysilicon-silicon oxide-silicon nitride-silicon oxide-silicon oxide (BE-SONOS), which Manufactured, tested and arranged for decoding in the manner shown in Figure 8 and Figure 23. The device was formed using a half-pitch of 75nm. Its channels are n-type polysilicon approximately 18 nanometers thick. No additional junction implants are performed to form a junction-free structure. The insulating material used to isolate the channels between the semiconductor strips is in the Z-axis direction, and it is silicon oxide with a thickness of about 40 nanometers. The gate provided is a P+ polysilicon line. The string select and ground select devices have longer channel lengths than memory cells. The test setup has 32 wordline, junctionless NAND gate strings. Because the channel etching used to form the shown structure has a sloped shape, there are wide silicon lines at the bottom of the channel, and the insulating material between the thin lines is etched more from the polysilicon, so in Figure 19 The width of the lower thin line is wider than the width of the upper thin line.

FIG. 20 shows a cross-sectional view of a memory cell with a diode, such as diode 1492, within the semiconductor body of the NAND series in one embodiment. The structure includes a plurality of ridge-like stacks comprising elongated strips of semiconductor material 1414, 1413, 1412 on the substrate in the respective ridge-like stack planes. A plurality of conductive lines 1425-1 to 1425-n (only two are shown for simplicity) are orthogonal to and extend across the stack and are conformally formed on the memory layer as previously described. The conductive wire 1427 as the serial selection line SSL and the conductive wire 1428 as the global source line GSL and other such lines are arranged in parallel with the plurality of conductive wires as the word lines. These wires can be formed using, for example, n-type or p-type doped polysilicon conductive material 1491 for use as wires for word lines. The silicide layer 1426 may be formed over a plurality of wires serving as word lines, string selection lines SSL, and global source lines GSL.

In region 1415, the strips of semiconductor material 1414, 1413, 1412 are interconnected via bulk source lines to other strips of semiconductor material in the same plane and to a plane decoder (not shown). The strips of semiconductor material are extended in-line within the bulk source line using the previously described stepped contact regions.

Diodes (eg, 1492) are placed between memory cells connected to wires 1425-1 through 1425-n and plugs 1450, 1451 connecting bit lines BLn and BLn+1 to strips of semiconductor material 1414, 1413, 1412. In this illustrative example, the diode is formed from a P+ implanted region (eg, 1449 ) in a long strip of semiconductor material. Plugs 1450, 1451 may comprise doped polysilicon, tungsten, or other vertical interconnect technologies. Upper bitlines BLn and BLn+1 are connected between plugs 1450, 1451 and a row decoding circuit (not shown).

In the structure shown in FIG. 20, it is not necessary to make contacts on the serial select gates and the common source select gates in the array.

Figure 21 shows two memory cell planes, each with 6 charge trapping memory cells arranged in a NAND configuration, which is a representative illustration of a cube, which may include many planes and many word lines. The two memory cell planes are composed of wires 1160, 1161 and 1162 as word lines WLn-1, WLn and WLn+1, which are respectively first, second and third elongated semiconductor material stacks.

The first plane of memory cells includes memory cells 1170, 1171, and 1172 in a series of NAND gates on top of the elongated stack of semiconductor material, and memory cells 1173, 1174, and 1175 in a series of NAND gates , and located on the elongated semiconductor material stack. In this illustration, the second plane of memory cells corresponds to the base plane of the cube and includes memory cells (eg, 1182 and 1184 ) arranged in series of NAND gates in a similar manner to the first plane.

As shown in the figure, the wire 1161 as the word line WLn includes a vertical extension corresponding to the material in the channel 120 between the stacks in FIG. The memory cells (for example, 1171 and 1174 of the memory cells in the first plane) of the interface region in the channel of the channel are coupled.

String select transistors 1196, 1197 are connected between respective strings of NAND gates and bit lines BL1 and BL2. Similarly, in this arrangement, similar string select transistors in the bottom plane of the cube are connected between respective strings of NAND gates and bit lines BL1 and BL2, so that row decoding is applied to these bit lines. String select line 1106 is connected to string select transistors 1196, 1197 and is parallel to the word line, as shown in FIG.

In this example, diodes 1110, 1111, 1112, 1113 are connected between this string and the corresponding bit line.

Grounded select transistors 1190, 1191 are arranged on opposite sides of the series of NAND gates and are used to couple the series of NAND gates in a select layer to a common source reference line. This common source reference line is decoded by the planar decoder in this structure. The ground selection line GSL may be implemented in a manner similar to the wires 1160 , 1161 , and 1162 . In some embodiments, the string select transistor and the ground select transistor may use the same dielectric stack as the gate oxide in the memory cell. In other embodiments, a typical gate oxide may be used instead. In addition, the channel length and width can be adjusted according to design requirements to provide proper switching functions of these transistors. The programming operation will be described below, wherein the target memory cell is memory cell A in FIG. Memory cell B is on the same row/bit line and column/word line as target memory cell A, but memory cell C on a different plane/source line is on the same column/word line as target memory cell A, However, the memory cell D in a different row/bit line and different plane/source line, for the memory cell E in the same plane/source line and the same row/bit line as the target memory cell A, but in a different column/word line, Consider the disturbance condition of the storage unit.

According to this arrangement, the serial select line and the common source select line can be decoded in a cube in a cube-based manner. The wordlines can be decoded on a column-by-column basis within a column. The common source line can be decoded in a plane on a plane basis. The bitlines can be decoded on a row-by-row basis.

FIG. 22 shows a timing diagram of a programming operation for an array similar to that of FIG. 20 . This programming interval is divided into three main sectors labeled T1, T2 and T3. During the first part of T1, the ground select line GSL and the unselected common source line CSL (shown as SL in the figure) in the cube are set to VCC, which is approximately 3.3V while the selected common source Line CSL remains at about 0V. In addition, the serial select line SSL is also kept at about 0V. In this way, the coupling effect of the selected plane to 0V can be achieved and the unselected plane is floating, so that the difference between the unselected common source line and the common source selection line is not enough to turn on the common source Select the gate of the line. After a short transition time, the unselected word lines and other pass gates (eg, dummy word lines and select gates) in this circuit are coupled to a turn-on voltage value of approximately 10V. Similarly, the selected word line is coupled to the same or close voltage value, while the grounded select line GSL and the unselected common source line CSL are left at VCC. This will cause a self-pumping effect of the body area in the unselected plane of the cube. Referring to FIG. 21, memory cells C and D have boosted regions in interval T1 as a result of this operation.

In the T2 segment, the ground select line GSL and the unselected common source line CSL transition back to 0V, while the word line and pass gate remain at the turn-on voltage. A short time after the ground select line GSL and the unselected common source line CSL transition back to 0V, the string select line SSL in the cube transitions to VCC, which may be about 3.3V as previously described. Similarly, unselected bit lines also transition to VCC. The result of the bias voltage in T2 time will cause the channel of the memory cell (such as memory cell B) on the same plane/source line and the same column/word line, but different row/bit line and on the same column/word line, but different Channels of memory cells (such as memory cell D) of row/bit line and different plane/source line are boosted by self-boosting. The boosted channel voltage of the memory cell C will not leak from the bit line BL due to this diode. After the T2 period, the string select line SSL and the unselected bit lines transition back to 0V.

In the T3 segment, after the ground select line GSL and the unselected common source line CSL transition back to 0V, the voltage of the selected word line is raised to a programming potential such as 20V, while the string select line SSL, ground The selection line GSL, the selected bit line, the unselected bit line, the selected common source line CSL, and the unselected common source line CSL are kept at 0V. An inverted channel is formed in the selected memory cells during the T1 and T2 intervals, and thus programming can be achieved even with both the string select gate and the select common source gate closed. It must be noted that the memory cell E on the same plane/source line and the same row/bit line as the target memory cell A, but on a different column/word line, will only be disturbed by the conduction voltage applied to the unselected word line . Therefore, the applied turn-on voltage must be low enough (for example, less than 10V) to prevent the data stored in these memory cells from being disturbed.

After the programming interval, all voltages return to about 0V.

A different embodiment of the structure in Figure 20 uses drain terminal (bit line) forward sensing. In various embodiments, the diode suppresses lost current paths during read and program inhibit operations.

FIG. 23 shows a schematic diagram of bias conditions for a read operation of an array similar to that in FIG. 20 . According to the bias voltage conditions applied to the structure on the substrate 410 shown in FIG. 23, the read bias voltage of the memory cells on a plane in a cube is to apply a conduction voltage to an unselected word line, and a read reference voltage to a selected word line. word line. The selected common source line CSL is coupled to approximately 0V, the unselected common source line CSL is coupled to approximately VCC, and both the ground select line GSL and the string select line SSL in the cube are coupled to approximately 3.3V. Bit lines BLn and BLn+1 in the cube are then coupled to a precharge stage of approximately 1.5V.

Page decoding in this example can be achieved by plane decoding using common source lines. Thus, for a given bias condition, since each selected common source line or plane in the cube has a page of bit lines with the same number of bits that can be read. The selected common source line CSL is coupled to approximately 0V or set as a reference voltage, while the other common source lines CSL are set to approximately 3.3V. In this case, the unselected common source lines are floating. Diodes to prevent current divergence for bit line paths on unselected planes.

In a page read operation, each word line on each plane in a cube is read once. Similarly, in a page-based programming operation, the program inhibition condition must be sufficient to sustain the number of times the program needs to program the page, ie, one per plane. Therefore, for a cube containing 8 memory cells, the program inhibit conditions of unselected memory cells must be sufficient to withstand 8 programming cycles.

It must be noted that the diodes in this bitline string need to slightly boost the bias of the bitlines by about 0.7V to compensate for the typical voltage drop of the diodes.

FIG. 24 shows a schematic diagram of bias conditions for a cube erase operation. According to the bias conditions shown in FIG. 24, the word line is coupled to a negative voltage such as -5V, the common source line CSL and the bit line are coupled to a positive voltage such as +8V, and the ground select line GSL is coupled to a A suitable high turn-on voltage coupling is eg +8V. In this way, the breakdown scale of the source line bias can be suppressed. The ground selection line GSL and the serial selection line SSL of other blocks are turned off. The high voltage required by the bit line can be satisfied by the bit line driver design. Alternatively, the word line and string select line may be grounded while the common source line CSL and ground select line GSL are coupled to a high voltage such as +13V.

Figure 25 shows an alternative embodiment where the diode 1492 is formed using polysilicon plugs 1550, 1551 formed using in-situ p+ doping when forming the plugs. In this case, the diodes are self-aligned and process steps can be reduced. Other structures are the same as those shown in FIG. 20 . Twisted contact layouts can be used below 40nm (Figure 27).

During self-boosting, the PN diode must withstand a boost channel potential of about 8V within tens of milliseconds. The estimated leakage current at 8V reverse bias should be less than 100pA to withstand this boost potential. Of course, the breakdown potential should be well above 8V. A lower turn-on voltage (approximately less than 0.7V) helps prevent sensing difficulties.

Figure 26 shows an alternative embodiment in which the diodes are placed at the common source line CSL terminals of the strings of memory cells. Therefore, in region 1515, the source lines in each plane are coupled together by p+ lines or doping, forming a PN between the common source line decoder of each serial line and the ground selection line GSL. diode. Other structures are the same as those shown in FIG. 20 .

A different embodiment of the structure in Figure 26 uses reverse sensing at the source terminal (source line). In various embodiments, the diode suppresses lost current paths during read and program inhibit operations.

Figure 27 shows a schematic diagram of a cube, in which two planes of memory cells are shown, corresponding to common source line CSL0 and common source line CSL1, two rows of memory cells, corresponding to bit line BL0 and bit line BL1, memory cells The four columns correspond to the word lines in the diagram respectively. The serial select line SSL in the cube is coupled to the serial select gate, and the ground select line GSL is coupled to the ground select gate. A self-boost programming operation similar to that described previously is used for programming, with a two-stage programming voltage applied to selected word lines as described in more detail below. The diodes are coupled between the corresponding memory cell series and the common source line CSL0 or the common source line CSL1 .

In the following discussion, a field bit line is another term for a string. In this structure, all common source lines CSL can be applied with a high voltage to inhibit programming. When the selected common source line CSL goes low, the high voltage of the local bit line does not go low. The page buffer can determine which memory cells should be programmed. When the bit line voltage is VDD, programming does not occur. Programming occurs when the bit line voltage is ground.

For a NAND flash memory cell, Fuller-Nordham electron tunneling can be used to program selected memory cells. In order to inhibit the programming of non-selected memory cells, a high voltage should be applied to the local bit line or channel of this memory cell. To achieve program inhibition, a program sequence as shown in Figure 28 and Figure 29 can be applied.

This programming operation includes applying a high voltage to the unselected common source lines, and applying VCC (about 3.3V) to the unselected bit lines. When the word line changes to VCC or the turn-on voltage of the high voltage, the bit lines in the area where the bit line is not selected are boosted to the high voltage. The region where the bit line is selected will be forced to a high voltage by the common source line or forced down to the ground common source line by the bit line. When the word line of the selected memory cell is changed to programming potential, all local bit lines are floating. The power applied during the program operation must be sufficient so that any current flow (from VCC/high voltage to ground) caused by the voltage level of a region of an unselected bit line does not interfere with programming or cause a program disturb condition occur.

Figure 28 shows a five-stage programming sequence. In step 1, the ground select line turns on the ground select gate, and the serial select line turns off the serial select gate. The high voltage on the unselected common source line charges the local bit lines in the unselected planes of the cube to a high voltage. The word line voltages of all the word lines are boosted to a first word line voltage. In step 2, the local bit lines in the unselected rows apply a supply potential to the unselected bit lines and ground the selected bit line by turning the string select gate on and the ground select gate off. In step 3, the word line is biased to the next turn-on voltage while the string select gate remains on and the ground select gate remains off. This causes the local bit lines in the unselected local bit lines to be coupled to a high voltage. In step 4, the bit line of the area sharing the selected bit line and an unselected common source line is charged to a high voltage. During this phase, the serial select line is off and the ground select line is on. In step 5, the word line voltage is biased to the programming voltage while the string select line and the ground select line remain closed.

Figure 29 shows an alternate five-stage programming sequence. In step 1, all local bit lines are charged to high voltage by biasing the common source line in the cube to high voltage, the grounded select gate in the cube is turned on, and the string select gate is turned off. Afterwards, the ground select gates in the cube are turned off, and the string select gates are turned on, which drives the local bitlines in the selected local bitlines to ground.

In step 3, the word line is biased to a turn-on voltage while the string select gate remains on and the ground select gate remains off. This results in the local bitlines in the selected regional bitlines being held at ground while the regional bitlines in the unselected regional bitlines are floating and boosted by the wordlines. In step 4, the selected bit line and an area bit line of an unselected common source line are charged to high by turning on the grounded select gate in the cube and closing the serial select gate to bias the unselected common source line Voltage. In step 5, the selected word line receives the programming voltage while the string select gate and the ground select gate remain closed. Compared with the algorithm in FIG. 28, the algorithm in FIG. 29 may have better boost suppression characteristics and consume more power. The self-boosting local bit line LBL3 self-high voltage can improve the boost suppression result, so the local bit line voltage will be higher and the suppression is improved. The result of changing from the common source line to high voltage and discharging to ground increases power consumption.

Therefore, in this operating technique, the high voltage applied from the source line can inhibit programming. The programmed bit line is floating when a programming voltage is applied to the selected bit line while the unselected source lines are pulled down to ground. In addition, this sequence of bias voltages is applied in such a way as to maintain proper boosting to inhibit programming. When programming, the current path of the diode is used to prevent the current from returning to the common source.

Because the common source line is integral, the common source line can only decode the entire array once. In contrast, decoding the serial select lines requires additional serial select line drivers and contact areas.

In various embodiments, the diode-decoded memory array reduces the number of string select line gates to only one string select line configuration per block, or only one string select line per NAND gate string wire grid. Such a structure greatly reduces the difficulty of the process, and has high symmetry and miniaturization. This architecture does not require a large number of serial selection lines when increasing the number of memory cell layers in a three-dimensional memory array. Similarly, only one ground select line is required in a block.

The three-dimensional vertical gate device is preferably a TFT bandgap engineered polysilicon-silicon oxide-silicon nitride-silicon oxide-silicon oxide (BE-SONOS) device. On the other hand, similar devices using antifuse or other memory technologies (eg using other charge trapping devices with high-k dielectric layers) can also be developed.

FIG. 30 shows a timing diagram of another example programming operation for an array similar to that of FIG. 21 .

During the T1 phase, the source line is self-boosted by the ground select line GSL and the Vcc of the unselected source lines.

During the T2 phase, the unselected bit lines are boosted to a high voltage HV by the string select line SSL and the high voltage HV of the unselected bit lines. The channel voltage Vch of memory cell B is also boosted. The boosted channel voltage Vch of the memory cell C does not leak because of the diode on the bit line BL.

During the T3 phase, memory cell A is programmed. Its reversal channel has been formed at the T1 phase.

FIG. 31 shows a schematic diagram of a three-dimensional NAND flash memory structure similar to that in FIG. 27. In this figure, it is shown that the string includes diodes formed between the source line structure and the memory string. The placement of these diodes can be used to support program inhibition.

The target memory cell is memory cell A in the figure, and the following memory cell interference conditions will be considered: memory cell B represents the same plane/source line and same column/word line as target memory cell A, but different row/bit line memory cell, memory cell C represents a memory cell in the same row/bit line and column/word line as target memory cell A, but a different plane/source line, and memory cell D represents a memory cell in the same column/source line as target memory cell A Word line, but different row/bit line and different plane/source line memory cell, memory cell E represents target memory cell A in the same plane/source line and same row/bit line, but different column/word line storage unit. Memory cell E is disturbed by pass voltage Vpass and can be ignored in many embodiments.

FIG. 32 shows a timing diagram of an example programming operation for an array similar to that of FIG. 31 .

During the T1 phase, the unselected bit lines (memory cells B and D) are self-boosted by the string select line SSL and the voltage Vcc of the unselected bit lines.

During the T2 phase, the unselected source lines are boosted to a high voltage HV by the ground selection line GSL and the high voltage HV of the unselected source lines. For example, the channel voltage Vch of the unselected source line of the memory cell C is also directly boosted. When the voltage of the source line SL is 0V and the ground selection line GSL is turned on, for example, the boosted channel voltage Vch of the memory cell B will not leak due to the small leakage of the reverse biased diode on the source line SL .

During the T3 phase, memory cell A is still programmed although the serial select line SSL is turned off. Its reversal channel has been formed at the T1 phase.

33A and 33B are tunneling electron microscope photographs of a portion of a 3D NAND flash memory array.

Shown in the figure is a tunneling electron micrograph of a 75nm half-pitch (4F2) virtual ground device. Its channel width and length are 30 and 40 nm, respectively, while the channel height is 30 nm. Each device is a dual gate (vertical gate) vertical channel device, where the channel (buried channel device) is lightly doped n-type to increase read current. The profile of the bit line BL is a shape suitable for use with a planar ONO. Smaller sidewall dishing is achieved by properly tuning the process. A very flat ONO is formed on the sidewall of the bit line BL.

FIG. 33A is a cross-sectional view of the array along the X-axis direction. The figure shows two charge-trapping bandgap engineered polysilicon-silicon oxide-silicon nitride-silicon oxide-silicon oxide (BE-SONOS) devices formed on the sidewalls of each channel. Each device is a dual gate device. The channel current flows horizontally, while the gates are arranged vertically. Has minimal ONO sidewall dishing.

Fig. 33B is a cross-sectional view of the array along the Y-axis direction. Due to the tighter spacing and smaller bitline width, FIB tunneling electron micrographs show double images including polysilicon gates on the bitlines (horizontal semiconductor strips) and spacing. The device shown in the figure has a channel length of about 40 nm.

FIG. 34 is a graph of current-voltage (IV) characteristics of a polysilicon diode measured experimentally.

The forward and reverse current-voltage (IV) characteristics of polysilicon PN diodes were measured directly from the PN diodes connected to a three-dimensional array of NAND gates with vertical gates of virtual grounded NAND gates. The polysilicon has height/width dimensions of 30/30 nm. The leakage current at -8 is well below 10pA, which already meets the needs of self-boosting and helps eliminate program disturb. Apply a source bias voltage Vs and a turn-on voltage Vpass of 7V to all word lines. This P+-N diode (30nm width and 30nm height) showed a successful turn-on/turn-off ratio of over 6 numbers and above. This forward current is clamped by the series series resistor of the NAND gate.

FIG. 35 is a characteristic diagram of the reading current of a polysilicon diode connected to a three-dimensional NAND gate memory measured experimentally.

The three-dimensional NAND memory has 32 word lines. Both Vpass and Vread of the word line are 7V. The source line voltage Vsl varies among the following values: 2.5V, 2.0V, 1.0V, 0.5V and 0.1V. In this diagram, source line voltage Vsl exceeding 1.0V results in a suitable sense current. The read voltage applied at the source terminal (source terminal sensing technique), in this case a positive voltage. The required bias voltage is boosted by this PN diode, which requires sufficient turn-on voltage so that a source bias voltage in excess of 1.5V can generate sufficient read current.

FIG. 36 is a diagram of the programming inhibition characteristic of a polysilicon diode connected to a three-dimensional NAND memory, which is experimentally measured.

Typical program inhibit characteristics of memory cells A, B, C, D are shown in the figure. In this case, Vcc=3.3V, HV=8V, Vpass=9V. In memory cell A is the ISSP method of applying incremental stepping pulses. This graph shows a glitch-free interval beyond 5V. This is due to the isolation characteristics of the diode.

FIG. 37 shows the influence of the source bias voltage effect of the polysilicon diode connected to the three-dimensional NAND memory on the programming disturbance measured experimentally.

The source line inhibit bias (HV) has an effect on the program disturb interval. The interference of memory cell C can be minimized by HV>7V.

FIG. 38 shows the influence of the turn-on gate voltage effect of the polysilicon diode connected to the three-dimensional NAND memory on the programming disturbance measured experimentally.

Turning on the gate voltage has an effect on program disturb. The disturbance of memory cell C can be reduced by Vpass>6V.

FIG. 39 is a schematic diagram of the block erase switching current of a polysilicon diode connected to a three-dimensional NAND memory, measured experimentally.

Different bias voltages on the source line SL will change the block erase transition characteristics. Erasing is achieved by applying a positive source line bias and grounding all word lines WL. This means floating the main body of the three-dimensional NAND gate array. Source select line SSL/ground select line GSL apply a suitable positive voltage to avoid interference. This erase transition is also shown in FIG. 10 . In some embodiments the array does not use electric field enhancement (due to flat ONOs), so that the erase is primarily performed by bandgap engineered polysilicon-silicon oxide-silicon nitride-silicon oxide-silicon oxide (BE-SONOS) Hole tunneling injection support.

FIG. 40 is a schematic diagram of the experimentally measured current-voltage characteristics of a polysilicon diode connected with a three-dimensional NAND gate memory in programming and erasing states with different numbers of programming/erasing cycles.

The current-voltage curves show minor degradation for less than 10,000 erase operations, especially at 1,000 and one. Stamina degradation is usually due to sub-threshold slope degradation due to interface state (Dit) generation, while the memory interval does not change. By tuning the bandgap engineered polysilicon-silicon oxide-silicon nitride-silicon oxide-silicon oxide (BE-SONOS) stack this device showed reasonably little degradation after 10,000 erase operations compared to giant devices.

FIG. 41 is a schematic diagram of the threshold voltage distribution of a polysilicon diode connected to a three-dimensional NAND memory, which has programmed/erased memory cells distributed in a lookup table, measured experimentally.

A lookup table distribution of a single level of memory cells is used in the PN polysilicon diode connected to the 3D NAND memory. (In this three-dimensional sensing) the closest memory cells are programmed to the opposite state to represent the worst disturb case. In each layer, conventional page program and program inhibit methods are used, and then the other unselected source lines (memory cells C and D) are inhibited. Page programming is performed on other layers in turn. Unselected memory cells in a three-dimensional array are damaged by column stress and row stress many times.

In many different embodiments, the diode of the alternate embodiment is connected to the drain terminal (bit line) or the source terminal (source line), and has the source select line SSL/ground select line GSL connected to the bit line/source Polar roles reversed. These alternate operations are validated at the device class. However, in the circuit design, the source line has a small capacitive load, so that when the high voltage HV is applied to the source line, it can perform better in speed and power consumption.

The preferred embodiments and examples of the present invention are disclosed above in detail, but it should be understood that the above examples are only examples, not intended to limit the scope of the patent. Those skilled in the art can easily modify and combine related technologies according to the scope of the appended claims.

Claims (25)

1. storage device comprises:

One ic substrate;

A plurality of rectangular semi-conducting material laminations extend this ic substrate, and these a plurality of laminations have the ridge shape and comprise that at least two rectangular semi-conducting materials are separated by insulating barrier and are the Different Plane position in a plurality of plan position approachs;

Many word lines are arranged to and are orthogonal on these a plurality of laminations, and have and these a plurality of laminations along the surface of shape, the intersection of so setting up a cubical array in these a plurality of laminations and plotted point that should many word lines surfaces is regional;

Memory element is in this intersection zone, and it sets up the memory cell of accessible this cubical array via these a plurality of rectangular semi-conducting materials and these many word lines, and this memory element is arranged to serial between bit line structure and source electrode line; And

Diode and this serial couple, between memory cell serial and bit line structure and source electrode line wherein between one.

2. storage device according to claim 1, wherein this serial right and wrong door serial.

3. storage device according to claim 1; The combination selection of particular source polar curve in the specific bit line in this bit line structure, this source electrode line and the particular word line in this many word lines wherein can pick out the particular memory location in the memory cell of this cubical array.

4. storage device according to claim 1, wherein this diode and this serial couple, and are between memory cell serial and this bit line structure.

5. storage device according to claim 1, wherein this diode and this serial couple, and are between memory cell serial and this source electrode line.

6. storage device according to claim 1 more comprises:

One serial selection wire is arranged to and is orthogonal on these a plurality of laminations, and have and these a plurality of laminations along the surface of shape, so set up the serial choice device in these a plurality of laminations and the surperficial plotted point of this serial selection wire; And

One ground connection selection wire is arranged to and is orthogonal on these a plurality of laminations, and have and these a plurality of laminations along the surface of shape, so set up grounding selection device in these a plurality of laminations and the surperficial plotted point of this ground connection selection wire.

7. storage device according to claim 6, wherein this diode is coupled between this serial choice device and this bit line structure.

8. storage device according to claim 6, wherein this diode is coupled between this grounding selection device and this source electrode line.

9. storage device according to claim 1, wherein this memory element comprises a tunnel layer, an electric charge capture layer and a barrier layer respectively.

10. storage device according to claim 1, wherein this rectangular semi-conducting material comprises n type silicon and this diode comprises a p type zone in this rectangular semi-conducting material.

11. storage device according to claim 1, wherein this rectangular semi-conducting material comprises n type silicon and this diode comprises a p type embolism contacts with this rectangular semi-conducting material.

12. storage device according to claim 1 more comprises logic and does not choose the diode in the serial when programming this memory cell, to apply reverse biased to this memory cell.

13. a storage device comprises:

One ic substrate;

The memory cell of a cubical array is in this ic substrate, and this cubical array comprises:

The lamination of NAND gate serial memory cell; And

Diode and this serial couple, and are between memory cell serial and bit line structure and source electrode line wherein between one.

14. storage device according to claim 13; The combination selection of particular source polar curve in the specific bit line in this bit line structure, this source electrode line and the particular word line in this many word lines wherein can pick out the particular memory location in the memory cell of this cubical array.

15. storage device according to claim 13, wherein this diode and this serial couple, and are between memory cell serial and this bit line structure.

16. storage device according to claim 13, wherein this diode and this serial couple, and are between memory cell serial and this source electrode line.

17. storage device according to claim 13 more comprises:

One serial choice device is between this bit line structure and this memory cell serial; And

One grounding selection device is between this source electrode line and this memory cell serial.

18. storage device according to claim 17, wherein this diode is coupled between this serial choice device and this bit line structure.

19. storage device according to claim 17, wherein this diode is coupled between this grounding selection device and this source electrode line.

20. storage device according to claim 13, wherein this memory element comprises a tunnel layer, an electric charge capture layer and a barrier layer respectively.

21. a method of operating three-dimensional NAND gate flash memory comprises:

Apply a programming adjustment bias voltage sequence to this three-dimensional NAND gate flash memory, this cubical array comprises diode and this serial couples, and makes that this diode is between memory cell serial and bit line structure and source electrode line structure wherein between one.

22. method according to claim 21, wherein this applies this programming adjustment bias voltage sequence and comprises:

From one or more of source electrode line structure through one or more of this diode to not choosing one or more charging of serial, wherein this is not chosen serial and does not comprise soon the memory cell of being programmed by this programming adjustment bias voltage;

This bit line structure and source electrode line structure are not chosen serial and comprised soon by one or more one choose serial and remove and couple of the memory cell of this programming adjustment bias voltage programming from this;

Apply a program voltage via one or more word line of the memory cell that is about to be programmed and do not choose serial and this chooses serial to this by this programming adjustment bias voltage.

23. method according to claim 21, wherein this applies this programming adjustment bias voltage sequence and comprises:

Not through this diode one or more and from one or more of source electrode line structure to not choosing one or more charging of serial, wherein this is not chosen serial and does not comprise the memory cell of soon being programmed by this programming adjustment bias voltage;

This bit line structure and source electrode line structure are not chosen serial and comprised soon by one or more one choose serial and remove and couple of the memory cell of this programming adjustment bias voltage programming from this; And

Apply a program voltage via one or more word line of the memory cell that is about to be programmed and do not choose serial and this chooses serial to this by this programming adjustment bias voltage.

24. method according to claim 21, wherein this applies this programming adjustment bias voltage sequence and comprises:

Through this diode one or more and from one or more of bit line structure to not choosing one or more charging of serial, wherein this is not chosen serial and does not comprise soon the memory cell of being programmed by this programming adjustment bias voltage;

This bit line structure and source electrode line structure are not chosen serial and comprised soon by one or more one choose serial and remove and couple of the memory cell of this programming adjustment bias voltage programming from this; And

Apply a program voltage via one or more word line of the memory cell that is about to be programmed and do not choose serial and this chooses serial to this by this programming adjustment bias voltage.

25. method according to claim 21, wherein this applies this programming adjustment bias voltage sequence and comprises:

Not through this diode one or more and from one or more of bit line structure to not choosing one or more charging of serial, wherein this is not chosen serial and does not comprise the memory cell of soon being programmed by this programming adjustment bias voltage;

This bit line structure and source electrode line structure are not chosen serial and comprised soon by one or more one choose serial and remove and couple of the memory cell of this programming adjustment bias voltage programming from this; And

Apply a program voltage via one or more word line of the memory cell that is about to be programmed and do not choose serial and this chooses serial to this by this programming adjustment bias voltage.

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