JPS58114235A - Two-dimensional data converting and operating circuit - Google Patents

Abstract

PURPOSE:To constitute a code converting circuit for executing plural pieces of code information stored in one memory, by simultaneously accessing data of plural two-dimensional arrays, through a bus connected to a memory with a pipeline. CONSTITUTION:One memory unit is provided, and an address bus and a data bus are provided only one each. By one memory, a two-dimensional code operation is executed at a high speed, reading and writing an input data and an output data by a data converting circuit. The data converting circuit generates 4 modes by a counter CT40 by making a fundamental clock CLK its base, sets an address of counters CT1-CT4 to addresses AD1-AD4 in time division in accordance with each mode, and reads an input code data in buffers BR1-BR3. Also, the result of operation stored in a two-dimensional buffer BF4 is sent to the memory and the operation is executed. In this way, it is possible to constitute a converting circuit whose memory and bus are simple.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The subject of the present invention is a code conversion operation for code information of a two-dimensional array of image data% graphic data, which is performed for processing lIi image processing, m% graphic processing, etc. Regarding episode 11.

(2) Disadvantages between the conventional technology and the code conversion circuit, which was constructed using conventional hardware, is one in which the memory in which code information is stored is connected to one two-dimensional circuit through a pipeline bus to simplify the circuit configuration. Since only array data can be accessed, the input bus and output bus are configured separately, and each bus has a memory t-
A connected operation is being performed. □In this case, when performing operations between multiple input codes, it is not necessary to have as many memory modules as there are input codes, and one memory module and bus are required for each code information. A drawback arises in that it must be connected to an arithmetic circuit.

This will be explained in detail below using figures.

Conventionally, when performing data/event conversion calculations using hardware, 1. - It has nine configurations as shown in Figure 1. Memory modules MM1 to MM4 are required to store input data and output data.9 Each memory module has an address bus D.
i～mu D4. Data buses Dm1-DA4 are connected, so that data (code information) corresponding to the address generated from the data conversion circuit DC can be accessed independently. The disadvantage of this data conversion circuit is that there are many types of a-dimensional data that can be input.

As the number of memory modules increases, the number of address buses and data buses also increases, and there is a tendency for the number of buses to increase relative to the memory capacity. This configuration uses a second module to process data conversion at high speed. As shown in the figure, the conversion circuit has counters CTI to O'r4 corresponding to address buses ^Di to D4, respectively, and data transfer is performed in parallel.

Sue, BFI ~ BF4 is a two-dimensional by 77s OC is a code conversion time @OLK is a clock.

(3) Purpose of the Invention The purpose of the present invention is to simultaneously access data in a plurality of two-dimensional arrays by connecting the memory with a pipeline and through a bus, and in particular to access data in a plurality of code information stored in one memory. It is an object of the present invention to provide a code conversion circuit that can perform calculations.

(4) Structure of the Invention The present invention improves the pipeline processing of input/output data of the code conversion circuit by making the speed of time-division data transfer in memory access and the speed of two-dimensional calculation in code conversion synchronous. This is what made it possible.

(5) Examples of the invention FIG. 3 is a diagram showing an embodiment of the present invention.

This configuration includes one memory unit Mσ, address bus AD, and data bus shim. Figure 4 shows the configuration of the data conversion circuit Do. FIG.

This circuit uses the basic clock cLx as a pace and generates four modes using the counters OT and OK. Corresponding to each mode, the address values of counters OT, ~CT, are time-divided into address buses D1~AD.

Set K and input code data to buffers BR1 to BR.
Load into Lu.

Also, the two-dimensional buffer B IF 41c sends the stored calculation results to the memory. In the state of the mode number, calculations can be performed at the same timing as conventional data conversion circuits.

This time Ili! By adopting this, the memory for storing code data and the bus became simple and could be constructed using a general-purpose memory board.

Note that DEC is a decoder, DR is a phase driver/receiver, and MPX is a multiplier.

Figure 6 shows the 4th FjAo two-dimensional buffer circuit BFI to BF.
4 is a diagram showing the configuration of No. 4. FIG.

C.N.T. is empty/re, COM is comparator, RAM
is a memory, and LTI NLT3 is a latch.

Figure 6 shows the three-man powered 3X3 code conversion circuit C shown in Figure 4.
It is a block diagram of C.

In the figure, LT, ... ~LT, are latches, ()1 to G are gates, and RAM is memory.

(6) Effects of the Invention According to the present invention, since it is possible to reduce the number of memories (t-1) to store code information necessary for code conversion, the bus necessary for data transfer can be simplified, and the memory The unit also has an effect that can be easily achieved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing connections of a conventional data conversion circuit. FIG. 2 is a diagram showing a conventional data conversion circuit, FIG. 3 is a diagram showing an embodiment of the present invention, FIG. 4 is a diagram showing an embodiment of the data conversion circuit of the present invention, and FIG. 5 is a diagram showing an embodiment of the data conversion circuit of the present invention. FIG. 4 is a block diagram of the two-dimensional buffer, and FIG. 6 is a diagram showing the ;-code conversion circuit in FIG. 4.

Claims (1)

[Claims] It stores secondary data and simultaneously reads multiple two-dimensional data from the same memory, performs two-dimensional operations on one input data and mutual operations between 11 or more input data, and stores the operation results simultaneously in the same memory. A two-dimensional data conversion calculation circuit that stores data in ◎