JPS63118965A - DMA word transfer method - Google Patents

Abstract

PURPOSE:To realize transfer faster than conventional byte transfer, by performing DMA transfer at odd-th access in a word unit. CONSTITUTION:Word data in a memory system are stored once in plural byte registers 30A-30N. Then, plural multiplexers 40A-40N select and output byte data consisting of the word data of another memory system out of the byte register 30A-30N by the control of a multiplexer control circuit 50. In such way, the word data in a certain memory system can be converted and outputted at high speed to the word data in another memory system.

Description

[Detailed Description of the Invention] [Summary] In direct memory access (DMA) between different memory systems, multiple sets of 8-bit data registers, multiple sets of multiplexers, and multiplexer control circuits are used. By providing this, word transfer with access to odd and even addresses is possible.

[Industrial application field]

The present invention provides DMA between different systems of memory systems.
It concerns word transfer.

[Conventional technology]

Various microprocessors are currently in use, but the memory configuration of each microprocessor can be divided into two types when considered in word units.

FIG. 6 is an explanatory diagram of the memory configuration of a conventional microprocessor. The same symbols represent the same objects throughout all the figures below.

For example, one of them is the memory configuration used in the 68000 series memory system, etc., as shown in Figure 6(a), in which the upper pie) (D8 to D15) of one word of 16 bytes are even-numbered addresses. , lower byte (
DO-D7) is at an odd address.

The other one is the memory configuration used in the 8086 series memory system, etc., as shown in Figure 6(b), in which the upper part of one word (16 bytes) (08 to D15) is an odd address, lower pie)
(Do-07) has an even address.

Recently, there have been cases in which two microprocessors with different memory configurations are used in one device.

For example, in audio processing equipment, it is often seen that a 68000 series microprocessor is used for the host microprocessor, and an 8086 series is used for the audio processing section microprocessor (sub). DMA transfer between memories is also frequently performed.

[Problem that the invention seeks to solve]

FIG. 7 is an explanatory diagram of conventional data transfer.

In the conventional data transfer method, when performing DMA word transfer between a 68000-series memory system and an 8086-series memory system, when a word is transferred from an even address to an even address as shown in FIG. 7(a), after the word transfer, Upper byte (D
8 to D15) and the lower byte (Do to D?).

However, as shown in Figure 7(b), from an odd number address to an odd number address,
Word transfer cannot be performed from an even address to an odd address as shown in FIG. 7(C), or from an odd address to an even address as shown in FIG. 7(d). Therefore, in the conventional method, transfers other than word transfer from an even address to an even address are performed by byte transfer, which has the problem that it takes more than twice as long as a word transfer.

[Means for solving problems]

The above problem is caused by the fact that, as shown in the principle diagram in Figure 1, a unit of processing word data is stored in multiple storage addresses, and one memory is In a DMA transfer circuit that transfers word data stored in a memory to another memory, a plurality of byte registers 30A to 30A that store data from the transfer source are used.
30N and byte register 30A to be output to the transfer destination
Multiple multiplexers to select 30N 40A~40M
This can be solved by providing a multiplexer control circuit (50) that controls a plurality of multiplexers 40A to 40M in accordance with the memory configuration of the transfer destination.

[Effect]

The word data of the memory system according to the present invention is temporarily stored in a plurality of byte registers 30A to 30N, and under the control of the multiplexer control circuit 50, the plurality of multiplexers 40A to 40M are stored in the byte registers 30A to 30N.
Since the byte data constituting the word data of another memory system is selected and output from among them, it becomes possible to convert and output the word data of the other memory system into the word data of another memory system.

〔Example〕

FIG. 2 is a diagram showing an embodiment of the DMA word transfer method according to the present invention.

In the figure, 1.3 is an address buffer, 2.4 is an address register, 5 is a counter, and 6 is a sequence ROM.
, 7 is a sequence register, 8.9 is an address counter, 10 is a bus control, lla, llb, 12
a, 12b are data buffers, 13.14 are multiplexers (MPX), and t5. , 15□, 15i
, t5. are data registers, 16 and 17 are multiplexers (MPX), and 18 is DMA-END-IRQ.
19 is an AND gate, 20 is an inverter, and 21, 22, 23, and 24 are Nant gates, respectively.

In addition, the bit resistors 30A to 30 in the principle diagram of Fig. 1
N corresponds to data buffers lla and llb in FIG.
Multiplexers 40A to 40M are multiplexers 13.
14.16.17, multiplexer control circuit 5
0 is counter 5, sequence ROM 6, sequence register 7, address counter 8.9, bus control 1
Consists of 0.

In the present invention, four sets of 8-bit data registers 15 are used.
．． , 15□, 152.154 and a sequence ROM 6 are provided, and even in odd number accesses, by reading two words of source side data, it is possible to perform word transfer successively.

The functions of each part in FIG. 2 will be explained.

Address buffer 1 is connected to the 68000 series memory system, and addresses of the 68000 series memory system are input and output.

Address register 2 is a register that stores an address sent from the 68000 series memory system.

The address buffer 3 is connected to the 8086 series memory system, and addresses of the 8086 series memory system are input and output.

Address register 4 is a register that stores addresses sent from the 8086 series memory system.

Counter 5 is a DMA length counter that stores the number of DMA transfer words and decrements every time one word is transferred.

Sequence ROM6 and sequence register 7 are read,
This is a circuit for generating internal control signals of this circuit such as write and CHG.

Address counter 8 is a counter for incrementing the address of the 68000 series memory system.

Address counter 9 is a counter for incrementing the address of the 8086 series memory system.

The bus control 10 is a control circuit that generates signals for controlling various buffers.

Data buffers ylla and llb are connected to the 68000 series memory system and temporarily store data.

The data buffers 12a and 12b are connected to an 8086-based memory system and temporarily store data.

The multiplexers 13 and 14 are selection circuits for selecting data on the source side.

Data register 15. , 15□, 151.154 are registers for latching data.

Multiplexers 16 and 17 are selection circuits that select data to be output.

DMA-END/IRQ control circuit 18 is DM
This circuit generates an interrupt signal after completion of A.

FIG. 3 is an explanatory diagram of the present invention.

When performing DMA transfer from a 68000 series memory system to an 8086 series memory system, four cases can be considered as shown in FIG.

That is, (al from an even number address to an even number address, (bl from an odd number address to an odd number address, (C1 from an even number address to an odd number address, +d) from an odd number address to an even number address.

In the present invention, data from the 68000 series memory system is once stored in data buffers lla and llb, and then stored in data registers 151 to 154, depending on whether the address is an odd number or an even number, that is, (a), (bl,
(C1, (Depending on whether the dl is Shirakawa or not, the 8086 series data buffer 12a, 12
sent to b.

Figure i4 is an explanatory diagram of the operation of the present invention.

In the case of (a), the upper byte and lower byte may be exchanged as shown in FIG. 4(a).

In the case of (b), as shown in Figure 4 (b), put the first word into the data register 151.15□, and put the second word into the data register 151.15□.
・Data register 15s, 15. and mask the lower byte only when writing the first word (masking the data register 154 with data register 151.15. output).

Next, the third word is stored in data register 15. ．． 15□, data register 15□, 15. Output.

Next, the fourth word is stored in data register 15. ．． 15. and data register 151.15. Output.

By repeating this process, only when writing the last word, the upper part is masked and output.

In the case of (C), as shown in FIG. 4(C), the first word is placed in the data registers 15I, 152, and the second word is placed in the data registers 153, 15. and data register 1
The data register 153 is masked by the output of 5□ and 153.

Next, data register 15. ．． 15. Output.

Put the third word into the data register 151, 15□,
Output data register 152.15i, data register 15. ．． Outputs 151.

Only when writing the last word, mask and output the upper part.

In the case of (d), the first word is stored in the data register 15. as shown in FIG. 4(d). ．． 15□, put the second word into data register 1'53.154, and put the second word into data register 1'53.154.
5. 154 and the third word to register 15°,
15z, output the data register 15z, IF)+, put the fourth word into the data register 15t, 154, and output the data register 15z. ．． Outputs 154.

All of the operating procedures described above are stored in the sequence ROM 6, and are executed by internal control signals such as read, write, CHG, etc. generated by the sequence ROM 6 and the sequence register 7.

That is, when a DMA activation command is issued to this circuit, the sequence ROM 6 receives this command. At the same time, a 68000 series address is input to the address buffer 1, an 8086 series address is input to the address buffer 3, and the number of DMA transfer words is input to the counter 5.

The bus control 10 operates according to an internal signal generated by the sequence ROM 6, and transfers the 68000 series address stored in the address buffer 1 to the address register 2, and the 8086 series address stored in the address buffer 3 to the address register 4. Transfer each, sequence R
This will be communicated to OM6.

68 by the read signal generated by sequence ROM6.
The data stored in the 000 series data buffers lla, llb or the 8086 series data buffers 12a, 12b is selected by the multiplexer 13.14, and the data is stored in the data registers 15+115z115i,
Enter 154.

Similarly, the data registers 15° and 15° are set by the write signal.
g, 15? , 154 is selected by the multiplexer 16.17 and output to the 68000 series data buffers lla, llb or the 8086 series data buffers 12a, 12b.

Similarly, the CHG signal is transmitted to data register 15. ．． 15□ and data register 153, 15. This is a signal to replace the

These internal control signals are applied to the data register, data buffer, address buffer, etc. through various gate circuits (Nant gates 21, 22, 23, 24, AND gate 19) together with the internal clock CLK to perform the above-mentioned operations. When the specified number of words have been transferred, the DMA-END
IRQ control 10 outputs an interrupt signal IRQ.

FIG. 5 is a flowchart of data transfer from an odd address to an odd address according to the present invention.

(The data transfer from an odd-numbered address to an odd-numbered address has been described above, but it will be explained in more detail with reference to the flowchart of FIG. 5.

First, after setting the odd address to the previous even address, read the first word DO~D7 from the data buffer lla and transfer it to the data register 15+.
is read from data buffer llb and input to data register 15□. At this time, multiplexer 13.1
4 performs a selection operation.

■ Read the second word Do-D7 from the data buffer lla and transfer it to the data register 153;
~D15 is read from data buffer llb and input to data register 154. At this time, multiplexers 13 and 14 perform selection operations.

(2) Take out the data stored in the data register 15+ 1154 and write it to the data buffers 12a and 12b. When writing the first word, the data register 154 is masked and the value of the counter 5 is decremented by 1. At this time, multiplexers 16 and 17 perform selection operations.

■ Check whether counter 5 (DMA length counter) is O or not. If it is 0, it is END, and if it is 0
If not, move on to ■.

Read the 0th order 1 word (3rd word) DO~D7 from the data buffer lla and transfer it to the data register 15+.
The first word D8 to D15 is read from the data buffer llb and input to the data register 15□.

(2) Check whether the counter 5 is O or not. If it is 0, move to @; if not, move to (2).

(2) Take out data registers 15z and 153 and write to data buffers 12a and 12b. At this time, the data register 153 is masked and END occurs.

■Data register 15□, 15. is taken out and written to the data buffers 12a and 12b.

The 0th order 1 word Do-D7 is read from the data buffer 11a and is transferred to the data register 153.
8 to D15 are read from data buffer llb and data register 15.8 to D15 are read from data buffer llb. Enter.

(2) Check whether the counter 5 is O or not. If it is O, move to (2), and if not O, move to [phase].

■Data register 15. ．． 154 and writes it to the data buffers 12a and 12b. At this time, the data register 15+ is masked and END occurs.

[Phase] Data register 15. ．． 15. is taken out, written to the data buffers 12a and 12b, and the process returns to (2).

Data transfer is performed by repeating these operations.

Note that DMA transfer from an 8086 series memory system to a 68000 series memory system can be performed in the same manner.

Furthermore, although this explanation has been made using a case between 16-byte memory systems as an example, it is possible to carry out the same procedure between 32-byte memory systems.

〔Effect of the invention〕

As described in detail above, according to the present invention, DMA transfer in odd number access can be performed in units of words, and there is a great effect that transfer can be performed at a higher speed than conventional byte transfer.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention. FIG. 2 is a diagram showing an embodiment of the DMA word transfer method according to the present invention. FIG. 3 is an explanatory diagram of the present invention. FIG. 4 is an explanatory diagram of the operation of the present invention. 'FIG. 5 is a flowchart of data transfer from an odd numbered address to an odd numbered address according to the present invention. FIG. 6 is an explanatory diagram of the memory configuration of a conventional microprocessor. FIG. 7 is an explanatory diagram of conventional data transfer. In the figure, 1.3 is an address buffer, 2.4 is an address register, 5 is a counter, and 6 is a sequence ROM.
, 7 is a sequence register, 8.9 is an address counter, 10 is a bus control, lla, llb, 12
a, 12b are data buffers, 13.14 are multiplexers (MPX), 15, . 15□, 153.1
54 is a data register, 6.17 is a multiplexer (MPX), 18 is a DMA-END-IRQ control, 19 is an AND gate, 20 is an inverter, 2
1.22.23.24 respectively Nantes Gate, 30A~3
0N is a byte register, 40A to 40M are multiplexers, and 50 is a multiplexer control circuit. 1yBooO+, δo a 6+
. (a) (6) Sushikira's Micro Araya 110 Memo Soo Achievement Diagram Figure 61 qχ End Technique -! Transfer n words and excuses 4 diagrams (Rerenemi ≧ Shi 5 Sun/Month/7th motion.. No. ・ (d,) ('F 匈し 0月 Figure 4

Claims (1)

[Claims] Between a pair of memories in which unit of processing word data is stored in a plurality of storage addresses, and the storage addresses of the data constituting the word data are different, the word data stored in one memory is transferred to the other memory. In the DMA transfer circuit that transfers to the memory of
), multiple multiplexers (40A to 40M
), and a multiplexer control circuit (50) that controls the plurality of multiplexers (40A to 40M) in accordance with the memory configuration of the transfer destination.
A word transfer method.