JPS58101445A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPS58101445A JPS58101445A JP56200522A JP20052281A JPS58101445A JP S58101445 A JPS58101445 A JP S58101445A JP 56200522 A JP56200522 A JP 56200522A JP 20052281 A JP20052281 A JP 20052281A JP S58101445 A JPS58101445 A JP S58101445A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- lead
- semiconductor device
- die pad
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 239000011347 resin Substances 0.000 claims abstract description 23
- 229920005989 resin Polymers 0.000 claims abstract description 23
- 230000017525 heat dissipation Effects 0.000 claims description 16
- 238000007789 sealing Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 description 9
- 238000000465 moulding Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- -1 lubrication Chemical compound 0.000 description 1
- 238000005461 lubrication Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 239000004071 soot Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for individual devices of subclass H10D
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
この考案は、放熱を改良した平形パンケージの電力用の
樹脂封止半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION This invention relates to a resin-sealed semiconductor device for electric power in a flat pancage with improved heat dissipation.
電子機器の小形化に対応し、従前からのＴＯ−９２形、
ＴＯ−２０２形、あるいはＴｏ−２２０形のものに対し
、プリント基板などへの実装密度を上げるために、小形
の平形パッケージにし平面実装に適したものが工夫され
ている。In response to the miniaturization of electronic equipment, the conventional TO-92 type,
Compared to the TO-202 type or To-220 type, a small flat package suitable for flat surface mounting has been devised in order to increase the mounting density on a printed circuit board or the like.
この種の従来の半導体装置は、第１図に斜視図で示すよ
うになっていた。図は小信号用トランジスタの場合を示
し、（１）はトランジスタで、内部には半導体素子（チ
ップ）（図示は略す）が装着されている０（２）はエミ
ッタリード、（３）はペースリード、（４）はコレクタ
リード、（５）は半導体素子部を封止した成形樹脂封止
体である。A conventional semiconductor device of this type is shown in a perspective view in FIG. The figure shows the case of a small signal transistor, where (1) is a transistor with a semiconductor element (chip) (not shown) installed inside, (2) is an emitter lead, and (3) is a pace lead. , (4) is a collector lead, and (5) is a molded resin sealing body in which the semiconductor element portion is sealed.
上記トランジスタ＜１）の樹脂封止前の組立状態を、第
２図に示す。（６）は鋼板あるいは鉄ニツケル合金板な
どから打抜かれてなるリードフレームで、厚さ０．１〜
０．３ｍｍ程度である。（２ａ）はエミッタリード部、
（３ａ）はベースリード部、（４ａ）はコレクタリ−ド
部、（７）はダイパッド部、（３）は両縁部、（９）は
連結部である。ダイパッド部（７）に半導体素子（テラ
乃（ト）がダイボンディングされ、この素子と各リード
の電極とが金網細線（１りでワイヤボンディングされで
ある。この後、鎖線で示すように１樹脂封止成形される
０つづいて、各リードの先端を切断し、下方に折曲げ加
工をし、第１図に示す小形外形のトランジスタ（１）が
完成される。FIG. 2 shows the assembled state of the transistor <1) before resin sealing. (6) is a lead frame punched from a steel plate or iron-nickel alloy plate, and has a thickness of 0.1 to
It is about 0.3 mm. (2a) is the emitter lead part,
(3a) is a base lead part, (4a) is a collector lead part, (7) is a die pad part, (3) is both edge parts, and (9) is a connecting part. A semiconductor element (Terano) is die-bonded to the die pad part (7), and this element and the electrodes of each lead are wire-bonded with wire mesh wire (1).After this, one resin is bonded as shown by the chain line. After sealing and molding, the tips of each lead are cut and bent downward to complete the small external transistor (1) shown in FIG.
この従来の小形パッケージのトランジスタ（１）では、
許容電力損失が１００〜３００ ｍＷと小電力用途に限
定されていた。これは、半導体素子（６）を載置しであ
るダイパッド部（７）及びその周囲が封止樹脂で覆われ
ており、半導体素子部からの熱放散が悪い丸めである。In this conventional small package transistor (1),
The allowable power loss was 100 to 300 mW, which was limited to low power applications. This is because the die pad part (7) on which the semiconductor element (6) is placed and its surroundings are covered with sealing resin, and the round shape has poor heat dissipation from the semiconductor element part.
この発明は、リードフレームの中央部のダイパッド部を
他のリード部より厚くシ、ダイパッド部下面に放熱突起
面を設け、この突起面を樹脂封止体の下面から露出させ
、熱放散を良好にして小形にし、価格を低下した平面実
装に適した電力用の樹脂封止半導体装置を提供すること
を目的とじている。This invention makes the die pad section at the center of the lead frame thicker than the other lead sections, provides a heat dissipating protrusion surface on the lower surface of the die pad, and exposes this protrusion surface from the lower surface of the resin sealing body to improve heat dissipation. The object of the present invention is to provide a resin-sealed semiconductor device for power use that is small in size and suitable for planar mounting at a reduced price.
以下、この発明の一実施例を２〜６アンペア級の中電力
用サイリスタの場合について、第３図ないし第６図によ
り説明する。まず、第３図において、図は下部を上にし
た斜視図であり、−は完成されたサイリスタで、内部に
は半導体素子（テップ）（図示は略す）が装着されてい
る。（２）はカンードリード、（ホ）はゲートリード、
（財）はアノードリード、（２５ａ）は放熱の突起面で
、リードフレームのダイパッド部（図示は略す）の下面
をなし、アノードリード（財）とは内部でつながってお
り、上記各リードのプリント基板（図示は略す）への装
着面とほぼ同一水平面にあるようＫしている。（至）は
半導体素子部を封止した成形樹脂封止体であり、この樹
脂封止体の下面（図では上側になっている）に対し、突
起面（２５ａ）は同一面か少し出張らしである。Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 3 to 6 for the case of a 2 to 6 ampere class medium power thyristor. First, in FIG. 3, the figure is a perspective view with the bottom facing up, and - indicates a completed thyristor, with a semiconductor element (TEP) (not shown) mounted inside. (2) is cando lead, (e) is gate lead,
(25a) is the anode lead, and (25a) is the heat dissipation protrusion surface, which forms the lower surface of the die pad part (not shown) of the lead frame, and is connected internally to the anode lead. It is arranged so that it is on almost the same horizontal plane as the mounting surface to the substrate (not shown). (to) is a molded resin encapsulation body that encapsulates the semiconductor element part, and the protrusion surface (25a) is on the same level or slightly protrudes from the bottom surface (upper side in the figure) of this resin encapsulation body. It is.
上記サイリスタ（財）が取付けられる外部のヒートシン
ク（図示していない）に放熱突起面（２ｂａ）を接続す
ることにょシ、第１図の従来の構造の半導体装置では得
られなかった、大きな放熱効果が得られ、従来に比べ大
きな電力容量に使用することが可能となる。By connecting the heat dissipation protrusion surface (2ba) to an external heat sink (not shown) to which the above thyristor is attached, a large heat dissipation effect that could not be obtained with the semiconductor device with the conventional structure shown in Fig. 1 is achieved. can be obtained, making it possible to use it for a larger power capacity than before.
上記各リード（４）、＠、（財）及びダイパッド部と放
熱突起面（Ａａａ）を形成するためのリードフレームの
素材を、第４因に斜視図で示す。リードフレームの薄帯
状の素材−は、中央部に突起部（１９ａ）が長手方向に
設けられ肉厚にされ、両側部（１９ｂ）は薄肉にされて
いる。この形成は、平条の母材よシ圧延、プレスあるい
は切削により連続加工される＾この母材は銅、るるいは
銅に微量のりん、すす。The material of the lead frame for forming each of the leads (4), the die pad portion, and the heat dissipating protrusion surface (Aaa) is shown in a perspective view as the fourth factor. The thin strip-shaped material of the lead frame has a protrusion (19a) provided in the longitudinal direction at the center and is made thicker, and both side parts (19b) are made thinner. This formation is performed continuously by rolling, pressing, or cutting the flat base material. This base material is made of copper, lubrication, or copper with trace amounts of phosphorus and soot.
又は鉄を含有させ硬度を高めた金属材が用いられる。素
材（ＩＣ４の突起部（１９ａ）が設けられた中央肉厚部
の厚さは０．５〜１ｍｍ程度で、両側部（ｘｓｂ）の厚
さはＯ，１〜０．４ｍｍ程度であり、条の幅は１５〜３
０ｍｍ程度である。Alternatively, a metal material containing iron to increase hardness is used. The thickness of the central thick part where the protrusion (19a) of the material (IC4) is provided is about 0.5 to 1 mm, and the thickness of both side parts (xsb) is about 0.1 to 0.4 mm. The width is 15 to 3
It is about 0 mm.
この素材−はリボン状のまま、プレス機により打抜加工
され、第５図に斜視図で示すように、リードフレーム（
２）が形成される。（２２ａ）はカンードリード部、（
２３ａ）はゲートリード部、（２４ａ）はアノードリー
ド部で、これらは両側部（ｌａｂ）の薄肉からなる。に
）は−ダイパッド部で、中央部の厚肉部から形成され、
下面が放熱突起面（２５１Ｌ）をなしている。（２１ａ
）は両わく部、（２１ｂ）は連結部である。This material is punched out using a press machine while still in the form of a ribbon, and as shown in the perspective view in Figure 5, a lead frame (
2) is formed. (22a) is the canned lead part, (
23a) is a gate lead part, and (24a) is an anode lead part, which are made of thin walls on both sides (lab). - is the die pad part, formed from the thick part in the center,
The lower surface forms a heat dissipation protrusion surface (251L). (21a
) are both frame portions, and (21b) is a connecting portion.
ダイパッド部（２）には半導体素子（ロ）がダイボンデ
ィングされ、この半導体素子（ロ）の各電極とこれに対
応する各リード部（２ａａ） 、 （ｚｓａ）間に金属
細線（１りでワイヤボンディングされている。この後、
各リード部（２２ａ）、（２３ａ）、（２４ａ）の先端
側を残し、半導体素子（財）部を樹脂封止成形により封
止する。各リードの先端を切断し、下方に折曲は加工を
してカソードリード磐、ゲートリード磐及びアノードリ
ード（財）を成形し、第６図に示すサイリスターができ
上る。第６図では、樹脂封止体（ホ）は鎖線で示してい
る。なお、リードフレーム（ロ）の各連結部（２１１）
）は、樹脂封止成形時に成形金型の型締めの効果を助け
、樹脂が不必要な個所にばりとなって流れ出ないように
防止する役目をもしており、樹脂封止後切除かれる。こ
の第６図のサイリスターを下部を上側にして示したのが
、第３図である。A semiconductor element (b) is die-bonded to the die pad part (2), and thin metal wires (1 wire) are connected between each electrode of this semiconductor element (b) and the corresponding lead parts (2aa) and (zsa). It is bonded.After this,
The semiconductor element (goods) part is sealed by resin sealing molding, leaving the leading ends of each lead part (22a), (23a), and (24a) intact. The tip of each lead is cut and bent downward to form a cathode lead, a gate lead, and an anode lead, thereby completing the thyristor shown in FIG. 6. In FIG. 6, the resin sealing body (E) is indicated by a chain line. In addition, each connection part (211) of the lead frame (b)
) assists in the clamping effect of the mold during resin sealing molding, and also serves to prevent the resin from flowing out as burrs in unnecessary areas, and is removed after resin sealing. FIG. 3 shows the thyristor of FIG. 6 with the lower part facing upward.
ｊ１７図に側面図で示すように、ダイパッド部に）の厚
さが０．５ｍｍ以上おるので、リードフレームＱ■の下
面側の放熱突起面（２５ａ）を外部に露出させた成形樹
脂封止が可能となる。これは、従来の装置では、リード
フレーム（６）の厚さが一様の０．１〜０．２ｍｍ程度
であり、リードフレーム（６）材と樹脂封止体（５）と
の接着保持力が弱く、したがって、必要な強度を有する
半導体装置ができなかったが、この一実施例では、ダイ
パッド部に）が厚くて、製作されるようになったのであ
る。As shown in the side view in Figure j17, the die pad part has a thickness of 0.5 mm or more, so the molded resin sealing with the heat dissipation protrusion surface (25a) on the bottom side of the lead frame Q■ exposed to the outside is necessary. It becomes possible. In conventional devices, the lead frame (6) has a uniform thickness of about 0.1 to 0.2 mm, and this is due to the adhesive holding strength between the lead frame (6) material and the resin sealing body (5). However, in this embodiment, the die pad portion had a thick layer), so that a semiconductor device with the necessary strength could not be produced.
このように、ダイパッド部員が肉厚であるため、自体が
半導体素子（財）から出る瞬時の発熱を、従来のものに
比べよシよく吸収し、さらに外部に熱伝達する重要な作
用をなしている。In this way, because the die pad member is thick, it absorbs the instantaneous heat generated by the semiconductor element (goods) better than conventional ones, and also plays an important role in transmitting heat to the outside. There is.
ｊ１８図はこの発明の他の実施例による半導体装置のａ
ｔｉｉ図でめる０図はサイリスタ■の場合を示し、カソ
ードリード（ロ）、ゲートリードに）、アノードリード
（至）は、折曲げられることなく、水平に引出されてい
る。Figure j18 is a diagram of a semiconductor device according to another embodiment of the present invention.
Figure 0 in Figure 2 shows the case of thyristor (2), in which the cathode lead (b), gate lead (to), and anode lead (to) are drawn out horizontally without being bent.
第９図はこの発明の他の異なる実施例による半導体装置
の側面図で、サイリスタの場合を示す。FIG. 9 is a side view of a semiconductor device according to another different embodiment of the present invention, showing the case of a thyristor.
サイリスターのアノードリード部を放熱突起面（２５ａ
）部で兼用し取出すようにし、アノードリード部（２４
ａ）は途中で切除いである。こうして、外形をさらに小
形化している。The anode lead part of the thyristor is connected to the heat dissipation protrusion surface (25a
) section so that it can be taken out and the anode lead section (24
A) is a cut in the middle. In this way, the external shape is further reduced.
上記この発明では、冷却伝達面をなす放熱突起面（２ａ
ａ）部は、リードフレーム素材−の成形時一体に形成し
ており、ダイパッド部（２５ａ）の厚さを精度高く作成
でき、樹脂成形時に樹脂封止体（７）の下面に突起面（
２５ａ）を精度よく露出させることができる。これによ
り、従来の装置では平板条材からなるリードフレーム（
６）であり、放熱を向上するため、ダイパッド部（７）
の下面に銅板などの放熱板を接着することがあったが、
この発明では下僚となる。In the above invention, the heat dissipation protrusion surface (2a
Part a) is formed integrally when molding the lead frame material, allowing the thickness of the die pad part (25a) to be created with high precision, and a protruding surface (
25a) can be exposed with high precision. As a result, in conventional equipment, lead frames (
6), and in order to improve heat dissipation, the die pad part (7)
A heat dissipation plate such as a copper plate was sometimes glued to the bottom surface of the
In this invention, it becomes a subordinate.
なお、上記実施例では、半導体装置としてサイリスタの
場合について説明したが、他の種の半導体装置にも適用
できるものである。In the above embodiments, a thyristor is used as the semiconductor device, but the present invention can also be applied to other types of semiconductor devices.
以上のように、この発明によれば、リードフレームにダ
イパッド部の下面位置に放熱突起面部を設けて肉厚にし
、この突起面を樹脂封止体の下面から露出させ熱放散を
曳好にしたので、外形が小形になり、価格が低減され、
平置実装に適することができる。また、用途に応じ外部
取付はヒート￥／りを適宜選択して突起面に接触させて
取付けることにより、広範囲の要求に対応することがで
き、はん用柱を高めることができる０As described above, according to the present invention, the lead frame is provided with a heat dissipating protruding surface portion at the lower surface position of the die pad portion to make the wall thicker, and this protruding surface is exposed from the lower surface of the resin sealing body to improve heat dissipation. Therefore, the external size is smaller and the price is reduced.
Can be suitable for horizontal mounting. In addition, by selecting an appropriate amount of heat for external installation depending on the application and attaching it in contact with the protruding surface, it is possible to meet a wide range of requirements and increase the height of the utility pole.
＃！１図は従来の半導体装置を示すトランジスタの斜視
図、第２図は第１図の装置の樹脂封止前の組立状態の平
面図、第３図はこの発明の一実施例による半導体装置を
示すサイリスタの下部を上側にした斜視図、第４図は第
３図のリードフレームの素材の斜視図、第５図は第３図
の装置の樹脂封止前の組立状態の斜視図、第６図は第５
図の状態の組立体から完成された半導体装置を樹脂封止
体は鎖線で示す斜視図、第７図は第６図の装置の樹脂封
止体は鎖線で示す側面図、第８図及び第９図はこの発明
の他のそれぞれ異なる実施例による半導体装置を示すサ
イリスタの樹脂封止体は鎖線で示す側面図でめる０
１９・・・リードフレーム素材、１９ａ・・・央起面部
、２０・・・サイリスタ、２１・・・リードフレーム、
２２・・・カソードリード、２３・・・ゲートリード、
２４・・・アノードリード、２５・・・ダイノ（ラド部
、２６ａ・・・放熱突起面、２６・・・樹脂封止体、２
）・・・半導体素子、３０・・・サイリスタ、３１・・
・カソードリード、３２・・・ゲートリード、３３・・
・アノードリード、４０・・・サイリスタ
なお、図中同一符号は同−又は和尚部分を示す。
代理人 葛野信−（外１名）
第１図
第２図
第３図
勿
６
第４図
第５図
第６図
第７図
第８図
第９図
’５２＆ｔ#! 1 is a perspective view of a transistor showing a conventional semiconductor device, FIG. 2 is a plan view of the device in FIG. 1 in an assembled state before resin sealing, and FIG. 3 shows a semiconductor device according to an embodiment of the present invention. FIG. 4 is a perspective view of the lead frame material shown in FIG. 3; FIG. 5 is a perspective view of the device shown in FIG. 3 in an assembled state before resin sealing; FIG. 6 is the fifth
The semiconductor device completed from the assembly in the state shown in the figure is a perspective view in which the resin molded body is shown in chain lines, FIG. 7 is a side view of the resin molded body of the device in FIG. 9 shows semiconductor devices according to other different embodiments of the present invention. The resin-sealed body of the thyristor is shown in a side view indicated by a chain line. ...thyristor, 21...lead frame,
22...Cathode lead, 23...Gate lead,
24... Anode lead, 25... Dyno (rad part, 26a... Heat dissipation projection surface, 26... Resin sealing body, 2
)...Semiconductor element, 30...Thyristor, 31...
・Cathode lead, 32...Gate lead, 33...
-Anode lead, 40...Thyristor Note that the same reference numerals in the drawings indicate the same or similar parts. Agent Makoto Kuzuno (1 other person) Figure 1 Figure 2 Figure 3 Figure 6 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 '52&t
Claims (3)
脂封止体の側面から引出された半導体装置において、リ
ードフレームのダイパッド部を他の電極リード部より肉
厚にして下面に放熱突起面を形成してあり、この突起面
を上記樹脂封止体の下面から露出していることを特徴と
する樹脂封止半導体装置。(1) In a semiconductor device in which a semiconductor element is resin-sealed and each electrode lead is drawn out from the side surface of the resin-sealed body, the die pad part of the lead frame is made thicker than other electrode lead parts and has heat dissipation protrusions on the bottom surface. 1. A resin-sealed semiconductor device characterized in that a surface is formed, and this protruding surface is exposed from a lower surface of the resin-sealed body.
、同極の引出リードを途中で切断しであるこ・とを特徴
とする特許＃求の範囲第１項記載の樹脂封止半導体装置
。(2) The resin sealing described in item 1 of the scope of the patent request, characterized in that the heat dissipation protrusion surface is also used as a contact part for the lead-out connection of the pole, and the lead-out lead of the same pole is cut midway. Semiconductor equipment.
る中央部を他よシ厚くシ、下面に長手方向の突起面部を
形成し帯状に形成したことを特徴とする特許１１ｉ末の
範囲第１項又は第２項記載の樹脂封止半導体装置。(3) Paragraph 1 of the scope at the end of Patent No. 11i, or 2. The resin-sealed semiconductor device according to item 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56200522A JPS58101445A (en) | 1981-12-11 | 1981-12-11 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56200522A JPS58101445A (en) | 1981-12-11 | 1981-12-11 | Resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58101445A true JPS58101445A (en) | 1983-06-16 |
Family
ID=16425705
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56200522A Pending JPS58101445A (en) | 1981-12-11 | 1981-12-11 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58101445A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60138944A (en) * | 1983-12-27 | 1985-07-23 | Toshiba Corp | Sealed semiconductor device |
| JP2007184642A (en) * | 2007-03-28 | 2007-07-19 | Toshiba Electronic Engineering Corp | Optical semiconductor package |
| JP2007184643A (en) * | 2007-03-28 | 2007-07-19 | Toshiba Electronic Engineering Corp | Optical semiconductor package |
| JP2010287914A (en) * | 2010-09-14 | 2010-12-24 | Toshiba Electronic Engineering Corp | Optical semiconductor package |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5325361A (en) * | 1976-08-23 | 1978-03-09 | Hitachi Ltd | Semiconductor device |
-
1981
- 1981-12-11 JP JP56200522A patent/JPS58101445A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5325361A (en) * | 1976-08-23 | 1978-03-09 | Hitachi Ltd | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60138944A (en) * | 1983-12-27 | 1985-07-23 | Toshiba Corp | Sealed semiconductor device |
| JP2007184642A (en) * | 2007-03-28 | 2007-07-19 | Toshiba Electronic Engineering Corp | Optical semiconductor package |
| JP2007184643A (en) * | 2007-03-28 | 2007-07-19 | Toshiba Electronic Engineering Corp | Optical semiconductor package |
| JP2010287914A (en) * | 2010-09-14 | 2010-12-24 | Toshiba Electronic Engineering Corp | Optical semiconductor package |
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